D8( P*rockchip,rk3288-evb-rk808rockchip,rk3288&7Rockchip RK3288 EVB RK808aliases=/ethernet@ff290000G/pinctrl/gpio@ff750000M/pinctrl/gpio@ff780000S/pinctrl/gpio@ff790000Y/pinctrl/gpio@ff7a0000_/pinctrl/gpio@ff7b0000e/pinctrl/gpio@ff7c0000k/pinctrl/gpio@ff7d0000q/pinctrl/gpio@ff7e0000w/pinctrl/gpio@ff7f0000}/i2c@ff650000/i2c@ff140000/i2c@ff660000/i2c@ff150000/i2c@ff160000/i2c@ff170000/mmc@ff0f0000/mmc@ff0c0000/mmc@ff0d0000/mmc@ff0e0000/serial@ff180000/serial@ff190000/serial@ff690000/serial@ff1b0000/serial@ff1c0000/spi@ff110000/spi@ff120000/spi@ff130000arm-pmuarm,cortex-a12-pmu0cpusrockchip,rk3066-smpcpu@500#cpuarm,cortex-a12/3:N]@krr cpu@501#cpuarm,cortex-a12/3:N]@krrcpu@502#cpuarm,cortex-a12/3:N]@krrcpu@503#cpuarm,cortex-a12/3:N]@krropp-table-0operating-points-v2opp-126000000 opp-216000000  opp-312000000 opp-408000000Q opp-600000000#F opp-696000000)|~opp-8160000000,B@opp-1008000000<opp-1200000000Gopp-1416000000TfrOopp-1512000000ZJ opp-1608000000_"preserved-memorydma-unusable@fe000000/oscillator fixed-clockn6xin24m timerarm,armv7-timer0   n6timer@ff810000rockchip,rk3288-timer/  H ka  2pclktimerdisplay-subsystemrockchip,display-subsystem> mmc@ff0c0000rockchip,rk3288-dw-mshcDр kDrv2biuciuciu-driveciu-sampleR / @3]resetiokaypzdefault mmc@ff0d0000rockchip,rk3288-dw-mshcDр kEsw2biuciuciu-driveciu-sampleR !/ @3]reset idisabledmmc@ff0e0000rockchip,rk3288-dw-mshcDр kFtx2biuciuciu-driveciu-sampleR "/@3]reset idisabledmmc@ff0f0000rockchip,rk3288-dw-mshcDр kGuy2biuciuciu-driveciu-sampleR #/@3]resetiokaypzdefaultsaradc@ff100000rockchip,saradc/ $kI[2saradcapb_pclk3W ]saradc-apbiokay {spi@ff110000(rockchip,rk3288-spirockchip,rk3066-spikAR2spiclkapb_pclk  txrx ,default/ idisabledspi@ff120000(rockchip,rk3288-spirockchip,rk3066-spikBS2spiclkapb_pclk txrx -default / idisabledspi@ff130000(rockchip,rk3288-spirockchip,rk3066-spikCT2spiclkapb_pclktxrx .default!"#$/ idisabledi2c@ff140000rockchip,rk3288-i2c/ >2i2ckMdefault% idisabledi2c@ff150000rockchip,rk3288-i2c/ ?2i2ckOdefault& idisabledi2c@ff160000rockchip,rk3288-i2c/ @2i2ckPdefault' idisabledi2c@ff170000rockchip,rk3288-i2c/ A2i2ckQdefault(iokaynserial@ff180000&rockchip,rk3288-uartsnps,dw-apb-uart/ 7&0kMU2baudclkapb_pclktxrxdefault)iokayserial@ff190000&rockchip,rk3288-uartsnps,dw-apb-uart/ 8&0kNV2baudclkapb_pclktxrxdefault*iokayserial@ff690000&rockchip,rk3288-uartsnps,dw-apb-uart/i 9&0kOW2baudclkapb_pclkdefault+iokayserial@ff1b0000&rockchip,rk3288-uartsnps,dw-apb-uart/ :&0kPX2baudclkapb_pclktxrxdefault,iokayserial@ff1c0000&rockchip,rk3288-uartsnps,dw-apb-uart/ ;&0kQY2baudclkapb_pclk  txrxdefault-iokaydma-controller@ff250000arm,pl330arm,primecell/%@=Hck 2apb_pclkthermal-zonesreserve-thermalz.cpu-thermalzd.tripscpu_alert0p*passive/cpu_alert1$*passive0cpu_crit_ *criticalcooling-mapsmap0/0map100gpu-thermalzd.tripsgpu_alert0p*passive1gpu_crit_ *criticalcooling-mapsmap01 2tsadc@ff280000rockchip,rk3288-tsadc/( %kHZ2tsadcapb_pclk3 ]tsadc-apbinitdefaultsleep3435siokay'>.ethernet@ff290000rockchip,rk3288-gmac/)Ymacirqeth_wake_irq58kfgc]M2stmmacethmac_clk_rxmac_clk_txclk_mac_refclk_mac_refoutaclk_macpclk_mac3B ]stmmacethiokayi6trgmii}input 7 'B@8default90usb@ff500000 generic-ehci/P k:usbiokayusb@ff520000 generic-ohci/R )k:usb idisabledusb@ff5400002rockchip,rk3288-usbrockchip,rk3066-usbsnps,dwc2/T k2otg host; usb2-phyiokayusb@ff5800002rockchip,rk3288-usbrockchip,rk3066-usbsnps,dwc2/X k2otg otg,>M@@ < usb2-phy idisabledusb@ff5c0000 generic-ehci/\ k idisableddma-controller@ff600000arm,pl330arm,primecell/`@=Hck 2apb_pclk idisabledi2c@ff650000rockchip,rk3288-i2c/e <2i2ckLdefault=iokaypmic@1brockchip,rk808/&>default?@\}xin32krk808-clkout2AAAAAABBABCregulatorsDCDC_REG13E q]puvdd_arm regulator-state-memDCDC_REG23E P]uvdd_gpusregulator-state-memB@DCDC_REG33uvcc_ddrregulator-state-memDCDC_REG43E2Z]2Zuvcc_ioBregulator-state-mem2ZLDO_REG13E2Z]2Z uvccio_pmuCregulator-state-mem2ZLDO_REG23E2Z]2Zuvcc_tpregulator-state-memLDO_REG33EB@]B@uvdd_10regulator-state-memB@LDO_REG43Ew@]w@ uvcc18_lcdregulator-state-memw@LDO_REG53Ew@]2Z uvccio_sdregulator-state-mem2ZLDO_REG63EB@]B@ uvdd10_lcdregulator-state-memB@LDO_REG73Ew@]w@uvcc_18regulator-state-memw@LDO_REG83E2Z]2Z uvcca_codecregulator-state-mem2ZSWITCH_REG13uvcc_wlregulator-state-memSWITCH_REG23uvcc_lcdregulator-state-memi2c@ff660000rockchip,rk3288-i2c/f =2i2ckNdefaultD idisabledpwm@ff680000rockchip,rk3288-pwm/hdefaultEk_iokay~pwm@ff680010rockchip,rk3288-pwm/hdefaultFk_ idisabledpwm@ff680020rockchip,rk3288-pwm/h defaultGk_ idisabledpwm@ff680030rockchip,rk3288-pwm/h0defaultHk_ idisabledsram@ff700000 mmio-sram/ppsmp-sram@0rockchip,rk3066-smp-sram/sram@ff720000#rockchip,rk3288-pmu-srammmio-sram/rpower-management@ff730000&rockchip,rk3288-pmusysconsimple-mfd/spower-controller!rockchip,rk3288-power-controllerh Zpower-domain@9/ kchgfdehilkj$IJKLMNOPQpower-domain@11/ kopRSpower-domain@12/ kTpower-domain@13/ kUVreboot-modesyscon-reboot-modeRB RBRB (RBsyscon@ff740000rockchip,rk3288-sgrfsyscon/tclock-controller@ff760000rockchip,rk3288-cru/vk 2xin24m54Hjk$A#gׄeрxhрxhsyscon@ff770000&rockchip,rk3288-grfsysconsimple-mfd/w5edp-phyrockchip,rk3288-dp-phykh224mViokayjio-domains"rockchip,rk3288-io-voltage-domain idisabledusbphyrockchip,rk3288-usb-phyiokayusb-phy@320V/ k]2phyclk3 ]phy-reset<usb-phy@334V/4k^2phyclk3 ]phy-reset:usb-phy@348V/Hk_2phyclk3 ]phy-reset;watchdog@ff800000 rockchip,rk3288-wdtsnps,dw-wdt/kp Oiokaysound@ff8b0000,rockchip,rk3288-spdifrockchip,rk3066-spdif/akT 2mclkhclkWtx 6defaultX5 idisabledi2s@ff890000(rockchip,rk3288-i2srockchip,rk3066-i2s/a 5kR2i2s_clki2s_hclkWWtxrxdefaultYr idisabledcrypto@ff8a0000rockchip,rk3288-crypto/@ 0 k}2aclkhclksclkapb_pclk3 ]crypto-rstiommu@ff900800rockchip,iommu/@ k 2aclkiface idisablediommu@ff914000rockchip,iommu /@P k 2aclkiface idisabledrga@ff920000rockchip,rk3288-rga/ kj2aclkhclksclkZ 3ilm ]coreaxiahbvop@ff930000rockchip,rk3288-vop / k2aclk_vopdclk_vophclk_vopZ 3def ]axiahbdclk[iokayport endpoint@0/\oendpoint@1/]kendpoint@2/^eendpoint@3/_hiommu@ff930300rockchip,iommu/ k 2aclkifaceZ iokay[vop@ff940000rockchip,rk3288-vop / k2aclk_vopdclk_vophclk_vopZ 3 ]axiahbdclk`iokayport endpoint@0/apendpoint@1/blendpoint@2/cfendpoint@3/diiommu@ff940300rockchip,iommu/ k 2aclkifaceZ iokay`dsi@ff960000*rockchip,rk3288-mipi-dsisnps,dw-mipi-dsi/@ k~d 2refpclkZ 5 idisabledportsport@0/endpoint@0/e^endpoint@1/fcport@1/lvds@ff96c000rockchip,rk3288-lvds/@kg 2pclk_lvdslcdcgZ 5 idisabledportsport@0/endpoint@0/h_endpoint@1/idport@1/dp@ff970000rockchip,rk3288-dp/@ bkic2dppclkjdpZ 3o]dp5iokayportsport@0/endpoint@0/k]endpoint@1/lbport@1/endpoint@0/mhdmi@ff980000rockchip,rk3288-dw-hdmi/0 gkhmn2iahbisfrcecZ 5aiokaynportsport@0/endpoint@0/o\endpoint@1/paport@1/video-codec@ff9a0000rockchip,rk3288-vpu/   Yvepuvdpuk 2aclkhclkqZ iommu@ff9a0800rockchip,iommu/ k 2aclkifaceZ qiommu@ff9c0440rockchip,iommu /@@@ ok 2aclkiface idisabledgpu@ffa30000#rockchip,rk3288-maliarm,mali-t760/$ Yjobmmugpuk:rNZ iokay s2opp-table-1operating-points-v2ropp-100000000~opp-200000000 ~opp-300000000B@opp-400000000ׄopp-600000000#Fqos@ffaa0000rockchip,rk3288-qossyscon/ Uqos@ffaa0080rockchip,rk3288-qossyscon/ Vqos@ffad0000rockchip,rk3288-qossyscon/ Jqos@ffad0100rockchip,rk3288-qossyscon/ Kqos@ffad0180rockchip,rk3288-qossyscon/ Lqos@ffad0400rockchip,rk3288-qossyscon/ Mqos@ffad0480rockchip,rk3288-qossyscon/ Nqos@ffad0500rockchip,rk3288-qossyscon/ Iqos@ffad0800rockchip,rk3288-qossyscon/ Oqos@ffad0880rockchip,rk3288-qossyscon/ Pqos@ffad0900rockchip,rk3288-qossyscon/ Qqos@ffae0000rockchip,rk3288-qossyscon/ Tqos@ffaf0000rockchip,rk3288-qossyscon/ Rqos@ffaf0080rockchip,rk3288-qossyscon/ Sdma-controller@ffb20000arm,pl330arm,primecell/@=Hck 2apb_pclkWefuse@ffb40000rockchip,rk3288-efuse/ kq 2pclk_efusecpu-id@7/cpu_leakage@17/interrupt-controller@ffc01000 arm,gic-400+@/ @ `   pinctrlrockchip,rk3288-pinctrl5gpio@ff750000rockchip,gpio-bank/u Qk@<L+>gpio@ff780000rockchip,gpio-bank/x RkA<L+gpio@ff790000rockchip,gpio-bank/y SkB<L+gpio@ff7a0000rockchip,gpio-bank/z TkC<L+gpio@ff7b0000rockchip,gpio-bank/{ UkD<L+7gpio@ff7c0000rockchip,gpio-bank/| VkE<L+gpio@ff7d0000rockchip,gpio-bank/} WkF<L+gpio@ff7e0000rockchip,gpio-bank/~ XkG<L+|gpio@ff7f0000rockchip,gpio-bank/ YkH<L+hdmihdmi-cec-c0Xthdmi-cec-c7Xthdmi-ddc Xtthdmi-ddc-unwedge Xutpcfg-output-lowfupcfg-pull-upqvpcfg-pull-down~wpcfg-pull-nonetpcfg-pull-none-12ma zsuspendglobal-pwroffXt@ddrio-pwroffXtddr0-retentionXvddr1-retentionXvedpedp-hpdX wi2c0i2c0-xfer Xtt=i2c1i2c1-xfer Xtt%i2c2i2c2-xfer X t tDi2c3i2c3-xfer Xtt&i2c4i2c4-xfer Xtt'i2c5i2c5-xfer Xtt(i2s0i2s0-bus`XttttttYlcdclcdc-ctl@Xttttgsdmmcsdmmc-clkXx sdmmc-cmdXysdmmc-cdXvsdmmc-bus1Xvsdmmc-bus4@Xyyyysdmmc-pwrX tsdio0sdio0-bus1Xvsdio0-bus4@Xvvvvsdio0-cmdXvsdio0-clkXtsdio0-cdXvsdio0-wpXvsdio0-pwrXvsdio0-bkpwrXvsdio0-intXvsdio1sdio1-bus1Xvsdio1-bus4@Xvvvvsdio1-cdXvsdio1-wpXvsdio1-bkpwrXvsdio1-intXvsdio1-cmdXvsdio1-clkXtsdio1-pwrX vemmcemmc-clkXtemmc-cmdXvemmc-pwrX vemmc-bus1Xvemmc-bus4@Xvvvvemmc-bus8Xvvvvvvvvspi0spi0-clkX vspi0-cs0X vspi0-txXvspi0-rxXvspi0-cs1Xvspi1spi1-clkX vspi1-cs0X v spi1-rxXvspi1-txXvspi2spi2-cs1Xvspi2-clkXv!spi2-cs0Xv$spi2-rxXv#spi2-txX v"uart0uart0-xfer Xvt)uart0-ctsXvuart0-rtsXtuart1uart1-xfer Xv t*uart1-ctsX vuart1-rtsX tuart2uart2-xfer Xvt+uart3uart3-xfer Xvt,uart3-ctsX vuart3-rtsX tuart4uart4-xfer Xvt-uart4-ctsX vuart4-rtsX ttsadcotp-pinX t3otp-outX t4pwm0pwm0-pinXtEpwm1pwm1-pinXtFpwm2pwm2-pinXtGpwm3pwm3-pinXtHgmacrgmii-pinsXttttzzzzttt zztt9rmii-pinsXttttttttttspdifspdif-txX tXpcfg-pull-none-drv-8maxpcfg-pull-up-drv-8maqybacklightbl-enXt}buttonspwrbtnXvlcdlcd-csXtpmicpmic-intXv?usbhost-vbus-drvXteth_phyeth-phy-pwrXtmemory@0#memory/adc-keys adc-keys{buttonsw@button-up Volume Upsbutton-down Volume Downrbutton-menuMenu button-escEscB@button-homeHomef backlightpwm-backlight   !"#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[\]^_`abcdefghijklmnopqrstuvwxyz{|}~  6|default} C~B@external-gmac-clock fixed-clocksY@ ext_gmac8panellg,lp079qx1-sp0v H 6| Rportsportendpointmgpio-keys gpio-keys _defaultkey-power =>tGPIO Key Power j} {dvcc-host-regulatorregulator-fixed  >default uvcc_host3vcc-phy-regulatorregulator-fixed  >defaultuvcc_phyE2Z]2Z36vsys-regulatorregulator-fixeduvcc_sysELK@]LK@3Asdmmc-regulatorregulator-fixed | defaultuvcc_sdE2Z]2Z  B #address-cells#size-cellscompatibleinterrupt-parentmodelethernet0gpio0gpio1gpio2gpio3gpio4gpio5gpio6gpio7gpio8i2c0i2c1i2c2i2c3i2c4i2c5mshc0mshc1mshc2mshc3serial0serial1serial2serial3serial4spi0spi1spi2interruptsinterrupt-affinityenable-methodrockchip,pmudevice_typeregresetsoperating-points-v2#cooling-cellsclock-latencyclocksdynamic-power-coefficientcpu0-supplyphandleopp-sharedopp-hzopp-microvoltrangesclock-frequencyclock-output-names#clock-cellsarm,cpu-registers-not-fw-configuredarm,no-tick-in-suspendclock-namesportsmax-frequencyfifo-depthreset-namesstatusbus-widthcap-mmc-highspeedcap-sd-highspeedcard-detect-delaydisable-wppinctrl-namespinctrl-0vmmc-supplyvqmmc-supplynon-removable#io-channel-cellsvref-supplydmasdma-namesreg-shiftreg-io-width#dma-cellsarm,pl330-broken-no-flushparm,pl330-periph-burstpolling-delay-passivepolling-delaythermal-sensorstemperaturehysteresistripcooling-devicepinctrl-1pinctrl-2#thermal-sensor-cellsrockchip,grfrockchip,hw-tshut-temprockchip,hw-tshut-moderockchip,hw-tshut-polarityinterrupt-namesphy-supplyphy-modeclock_in_outsnps,reset-gpiosnps,reset-active-lowsnps,reset-delays-usassigned-clocksassigned-clock-parentstx_delayrx_delayphysphy-namesdr_modesnps,reset-phy-on-wakeg-np-tx-fifo-sizeg-rx-fifo-sizeg-tx-fifo-sizerockchip,system-power-controllerwakeup-sourcevcc1-supplyvcc2-supplyvcc3-supplyvcc4-supplyvcc6-supplyvcc7-supplyvcc8-supplyvcc9-supplyvcc10-supplyvcc11-supplyvcc12-supplyvddio-supplyregulator-always-onregulator-boot-onregulator-min-microvoltregulator-max-microvoltregulator-nameregulator-off-in-suspendregulator-on-in-suspendregulator-suspend-microvolt#pwm-cells#power-domain-cellspm_qosoffsetmode-normalmode-recoverymode-bootloadermode-loader#reset-cellsassigned-clock-rates#phy-cells#sound-dai-cellsrockchip,playback-channelsrockchip,capture-channels#iommu-cellsrockchip,disable-mmu-resetpower-domainsiommusremote-endpointforce-hpdddc-i2c-busmali-supplyinterrupt-controller#interrupt-cellsgpio-controller#gpio-cellsrockchip,pinsoutput-lowbias-pull-upbias-pull-downbias-disabledrive-strengthio-channelsio-channel-nameskeyup-threshold-microvoltlabellinux,codepress-threshold-microvoltbrightness-levelsdefault-brightness-levelenable-gpiospwmsbacklightpower-supplyautorepeatlinux,input-typedebounce-intervalenable-active-highstartup-delay-usvin-supply