^8( 'firefly,firefly-rk3288rockchip,rk3288&7Firefly-RK3288aliases=/ethernet@ff290000G/pinctrl/gpio@ff750000M/pinctrl/gpio@ff780000S/pinctrl/gpio@ff790000Y/pinctrl/gpio@ff7a0000_/pinctrl/gpio@ff7b0000e/pinctrl/gpio@ff7c0000k/pinctrl/gpio@ff7d0000q/pinctrl/gpio@ff7e0000w/pinctrl/gpio@ff7f0000}/i2c@ff650000/i2c@ff140000/i2c@ff660000/i2c@ff150000/i2c@ff160000/i2c@ff170000/mmc@ff0f0000/mmc@ff0c0000/mmc@ff0d0000/mmc@ff0e0000/serial@ff180000/serial@ff190000/serial@ff690000/serial@ff1b0000/serial@ff1c0000/spi@ff110000/spi@ff120000/spi@ff130000arm-pmuarm,cortex-a12-pmu0cpusrockchip,rk3066-smpcpu@500#cpuarm,cortex-a12/3:N]@krr cpu@501#cpuarm,cortex-a12/3:N]@krrcpu@502#cpuarm,cortex-a12/3:N]@krrcpu@503#cpuarm,cortex-a12/3:N]@krropp-table-0operating-points-v2opp-126000000 opp-216000000  opp-312000000 opp-408000000Q opp-600000000#F opp-696000000)|~opp-8160000000,B@opp-1008000000<opp-1200000000Gopp-1416000000TfrOopp-1512000000ZJ opp-1608000000_"preserved-memorydma-unusable@fe000000/oscillator fixed-clockn6xin24m timerarm,armv7-timer0   n6timer@ff810000rockchip,rk3288-timer/  H ka  2pclktimerdisplay-subsystemrockchip,display-subsystem> mmc@ff0c0000rockchip,rk3288-dw-mshcDр kDrv2biuciuciu-driveciu-sampleR / @3]resetiokaypzdefault mmc@ff0d0000rockchip,rk3288-dw-mshcDр kEsw2biuciuciu-driveciu-sampleR !/ @3]resetiokaypdefault mmc@ff0e0000rockchip,rk3288-dw-mshcDр kFtx2biuciuciu-driveciu-sampleR "/@3]reset idisabledmmc@ff0f0000rockchip,rk3288-dw-mshcDр kGuy2biuciuciu-driveciu-sampleR #/@3]resetiokaypzdefaultsaradc@ff100000rockchip,saradc/ $kI[2saradcapb_pclk3W ]saradc-apbiokay spi@ff110000(rockchip,rk3288-spirockchip,rk3066-spikAR2spiclkapb_pclk  txrx ,default !"#/iokayspi@ff120000(rockchip,rk3288-spirockchip,rk3066-spikBS2spiclkapb_pclk txrx -default$%&'/ idisabledspi@ff130000(rockchip,rk3288-spirockchip,rk3066-spikCT2spiclkapb_pclktxrx .default()*+/ idisabledi2c@ff140000rockchip,rk3288-i2c/ >2i2ckMdefault,iokayi2c@ff150000rockchip,rk3288-i2c/ ?2i2ckOdefault- idisabledi2c@ff160000rockchip,rk3288-i2c/ @2i2ckPdefault.iokayi2c@ff170000rockchip,rk3288-i2c/ A2i2ckQdefault/iokay{serial@ff180000&rockchip,rk3288-uartsnps,dw-apb-uart/ 7&0kMU2baudclkapb_pclktxrxdefault 012iokayserial@ff190000&rockchip,rk3288-uartsnps,dw-apb-uart/ 8&0kNV2baudclkapb_pclktxrxdefault3iokayserial@ff690000&rockchip,rk3288-uartsnps,dw-apb-uart/i 9&0kOW2baudclkapb_pclkdefault4iokayserial@ff1b0000&rockchip,rk3288-uartsnps,dw-apb-uart/ :&0kPX2baudclkapb_pclktxrxdefault5iokayserial@ff1c0000&rockchip,rk3288-uartsnps,dw-apb-uart/ ;&0kQY2baudclkapb_pclk  txrxdefault6 idisableddma-controller@ff250000arm,pl330arm,primecell/%@=Hck 2apb_pclkthermal-zonesreserve-thermalz7cpu-thermalzd7tripscpu_alert0p*passive8cpu_alert1$*passive9cpu_crit_ *criticalcooling-mapsmap080map190gpu-thermalzd7tripsgpu_alert0p*passive:gpu_crit_ *criticalcooling-mapsmap0: ;tsadc@ff280000rockchip,rk3288-tsadc/( %kHZ2tsadcapb_pclk3 ]tsadc-apbinitdefaultsleep<=<>siokay'>7ethernet@ff290000rockchip,rk3288-gmac/)Ymacirqeth_wake_irq>8kfgc]M2stmmacethmac_clk_rxmac_clk_txclk_mac_refclk_mac_refoutaclk_macpclk_mac3B ]stmmacethiokayiy?inputdefault@ABCDrgmii 'B@ E0usb@ff500000 generic-ehci/P kFusb idisabledusb@ff520000 generic-ohci/R )kFusb idisabledusb@ff5400002rockchip,rk3288-usbrockchip,rk3066-usbsnps,dwc2/T k2otg hostG usb2-phyiokaydefaultHusb@ff5800002rockchip,rk3288-usbrockchip,rk3066-usbsnps,dwc2/X k2otg otg,>M@@ I usb2-phyiokayusb@ff5c0000 generic-ehci/\ k idisableddma-controller@ff600000arm,pl330arm,primecell/`@=Hck 2apb_pclk idisabledi2c@ff650000rockchip,rk3288-i2c/e <2i2ckLdefaultJiokaysyr827@40silergy,syr827\/@yvdd_cpu Pp,@ syr828@41silergy,syr828\/Ayvdd_gpu Pprtc@51haoyu,hym8563/Qxin32k&KdefaultLact8846@5aactive-semi,act8846/ZdefaultMN2=HS^jvOregulatorsREG1yvcc_ddrOOREG2yvcc_io2Z2ZREG3yvdd_logREG4yvcc_20OREG5 yvccio_sd2Z2ZREG6 yvdd10_lcdB@B@REG7yvcca_18w@w@REG8yvcca_332Z2ZcREG9yvcc_lan2Z2ZDREG10yvdd_10B@B@REG11yvcc_18w@w@REG12 yvcc18_lcdw@w@i2c@ff660000rockchip,rk3288-i2c/f =2i2ckNdefaultPiokaypwm@ff680000rockchip,rk3288-pwm/hdefaultQk_ idisabledpwm@ff680010rockchip,rk3288-pwm/hdefaultRk_iokaypwm@ff680020rockchip,rk3288-pwm/h defaultSk_ idisabledpwm@ff680030rockchip,rk3288-pwm/h0defaultTk_ idisabledsram@ff700000 mmio-sram/ppsmp-sram@0rockchip,rk3066-smp-sram/sram@ff720000#rockchip,rk3288-pmu-srammmio-sram/rpower-management@ff730000&rockchip,rk3288-pmusysconsimple-mfd/spower-controller!rockchip,rk3288-power-controllerihy hpower-domain@9/ kchgfdehilkj$UVWXYZ[\]power-domain@11/ kop^_power-domain@12/ k`power-domain@13/ kabreboot-modesyscon-reboot-modeRBRBRB RBsyscon@ff740000rockchip,rk3288-sgrfsyscon/tclock-controller@ff760000rockchip,rk3288-cru/vk 2xin24m>Hijk$#gׄeрxhрxhsyscon@ff770000&rockchip,rk3288-grfsysconsimple-mfd/w>edp-phyrockchip,rk3288-dp-phykh224m idisabledxio-domains"rockchip,rk3288-io-voltage-domainiokayc)d4BDP^nzusbphyrockchip,rk3288-usb-phyiokayusb-phy@320/ k]2phyclk3 ]phy-resetIusb-phy@334/4k^2phyclk3 ]phy-resetFusb-phy@348/Hk_2phyclk3 ]phy-resetGwatchdog@ff800000 rockchip,rk3288-wdtsnps,dw-wdt/kp Oiokaysound@ff8b0000,rockchip,rk3288-spdifrockchip,rk3066-spdif/kT 2mclkhclketx 6defaultf> idisabledi2s@ff890000(rockchip,rk3288-i2srockchip,rk3066-i2s/ 5kR2i2s_clki2s_hclkeetxrxdefaultg idisabledcrypto@ff8a0000rockchip,rk3288-crypto/@ 0 k}2aclkhclksclkapb_pclk3 ]crypto-rstiommu@ff900800rockchip,iommu/@ k 2aclkiface idisablediommu@ff914000rockchip,iommu /@P k 2aclkiface idisabledrga@ff920000rockchip,rk3288-rga/ kj2aclkhclksclkh 3ilm ]coreaxiahbvop@ff930000rockchip,rk3288-vop / k2aclk_vopdclk_vophclk_voph 3def ]axiahbdclkiiokayport endpoint@0/j|endpoint@1/kyendpoint@2/lsendpoint@3/mviommu@ff930300rockchip,iommu/ k 2aclkifaceh iokayivop@ff940000rockchip,rk3288-vop / k2aclk_vopdclk_vophclk_voph 3 ]axiahbdclkniokayport endpoint@0/o}endpoint@1/pzendpoint@2/qtendpoint@3/rwiommu@ff940300rockchip,iommu/ k 2aclkifaceh iokayndsi@ff960000*rockchip,rk3288-mipi-dsisnps,dw-mipi-dsi/@ k~d 2refpclkh > idisabledportsport@0/endpoint@0/slendpoint@1/tqport@1/lvds@ff96c000rockchip,rk3288-lvds/@kg 2pclk_lvdslcdcuh > idisabledportsport@0/endpoint@0/vmendpoint@1/wrport@1/dp@ff970000rockchip,rk3288-dp/@ bkic2dppclkxdph 3o]dp> idisabledportsport@0/endpoint@0/ykendpoint@1/zpport@1/hdmi@ff980000rockchip,rk3288-dw-hdmi/0 gkhmn2iahbisfrcech >iokay'{portsport@0/endpoint@0/|jendpoint@1/}oport@1/video-codec@ff9a0000rockchip,rk3288-vpu/   Yvepuvdpuk 2aclkhclk~h iommu@ff9a0800rockchip,iommu/ k 2aclkifaceh ~iommu@ff9c0440rockchip,iommu /@@@ ok 2aclkiface idisabledgpu@ffa30000#rockchip,rk3288-maliarm,mali-t760/$ Yjobmmugpuk:Nh iokay3;opp-table-1operating-points-v2opp-100000000~opp-200000000 ~opp-300000000B@opp-400000000ׄopp-600000000#Fqos@ffaa0000rockchip,rk3288-qossyscon/ aqos@ffaa0080rockchip,rk3288-qossyscon/ bqos@ffad0000rockchip,rk3288-qossyscon/ Vqos@ffad0100rockchip,rk3288-qossyscon/ Wqos@ffad0180rockchip,rk3288-qossyscon/ Xqos@ffad0400rockchip,rk3288-qossyscon/ Yqos@ffad0480rockchip,rk3288-qossyscon/ Zqos@ffad0500rockchip,rk3288-qossyscon/ Uqos@ffad0800rockchip,rk3288-qossyscon/ [qos@ffad0880rockchip,rk3288-qossyscon/ \qos@ffad0900rockchip,rk3288-qossyscon/ ]qos@ffae0000rockchip,rk3288-qossyscon/ `qos@ffaf0000rockchip,rk3288-qossyscon/ ^qos@ffaf0080rockchip,rk3288-qossyscon/ _dma-controller@ffb20000arm,pl330arm,primecell/@=Hck 2apb_pclkeefuse@ffb40000rockchip,rk3288-efuse/ kq 2pclk_efusecpu-id@7/cpu_leakage@17/interrupt-controller@ffc01000 arm,gic-400?T@/ @ `   pinctrlrockchip,rk3288-pinctrl>gpio@ff750000rockchip,gpio-bank/u Qk@eu?Tgpio@ff780000rockchip,gpio-bank/x RkAeu?Tgpio@ff790000rockchip,gpio-bank/y SkBeu?Tgpio@ff7a0000rockchip,gpio-bank/z TkCeu?Tgpio@ff7b0000rockchip,gpio-bank/{ UkDeu?TEgpio@ff7c0000rockchip,gpio-bank/| VkEeu?Tgpio@ff7d0000rockchip,gpio-bank/} WkFeu?Tgpio@ff7e0000rockchip,gpio-bank/~ XkGeu?TKgpio@ff7f0000rockchip,gpio-bank/ YkHeu?Thdmihdmi-cec-c0hdmi-cec-c7hdmi-ddc hdmi-ddc-unwedge pcfg-output-lowpcfg-pull-uppcfg-pull-downpcfg-pull-nonepcfg-pull-none-12ma suspendglobal-pwroffddrio-pwroffddr0-retentionddr1-retentionedpedp-hpd i2c0i2c0-xfer Ji2c1i2c1-xfer ,i2c2i2c2-xfer   Pi2c3i2c3-xfer -i2c4i2c4-xfer .i2c5i2c5-xfer /i2s0i2s0-bus`glcdclcdc-ctl@usdmmcsdmmc-clk sdmmc-cmdsdmmc-cdsdmmc-bus1sdmmc-bus4@sdmmc-pwr sdio0sdio0-bus1sdio0-bus4@sdio0-cmdsdio0-clksdio0-cdsdio0-wpsdio0-pwrsdio0-bkpwrsdio0-intsdio1sdio1-bus1sdio1-bus4@sdio1-cdsdio1-wpsdio1-bkpwrsdio1-intsdio1-cmdsdio1-clksdio1-pwr emmcemmc-clkemmc-cmdemmc-pwr emmc-bus1emmc-bus4@emmc-bus8spi0spi0-clk spi0-cs0  spi0-tx!spi0-rx"spi0-cs1#spi1spi1-clk $spi1-cs0 'spi1-rx&spi1-tx%spi2spi2-cs1spi2-clk(spi2-cs0+spi2-rx*spi2-tx )uart0uart0-xfer 0uart0-cts1uart0-rts2uart1uart1-xfer  3uart1-cts uart1-rts uart2uart2-xfer 4uart3uart3-xfer 5uart3-cts uart3-rts uart4uart4-xfer 6uart4-cts uart4-rts tsadcotp-pin <otp-out =pwm0pwm0-pinQpwm1pwm1-pinRpwm2pwm2-pinSpwm3pwm3-pinTgmacrgmii-pins @rmii-pinsphy-int Cphy-pmebBphy-rstAspdifspdif-tx fpcfg-output-highpcfg-pull-up-drv-12ma act8846pwr-holdNpmic-vselMdvpdvp-pwr hym8563rtc-intLkeyspwr-keyledspower-led-pinwork-led-pinusb_hosthost-vbus-drvusbhub-rstHusb_otgotg-vbus-drv irir-intmemory@0#memory/adc-keys adc-keysbuttonsw@button-recovery Recovery h &dovdd-1v8-regulatorregulator-fixed ydovdd_1v8w@w@dexternal-gmac-clock fixed-clocksY@ ext_gmac?ir-receivergpio-ir-receiverdefault @Kgpio-keys gpio-keyskey-power F @ GPIO Power tdefaultleds gpio-ledsled-0 @ firefly:blue:user Trc-feedbackdefaultled-1 @ firefly:green:power Tdefault-ondefaultvsys-regulatorregulator-fixedyvcc_sysLK@LK@sdmmc-regulatorregulator-fixed K defaultyvcc_sd2Z2Z jflash-regulatorregulator-fixed yvcc_flashw@w@usb-regulatorregulator-fixedyvcc_5vLK@LK@usb-host-regulatorregulator-fixed { default yvcc_host_5vLK@LK@usb-otg-regulatorregulator-fixed {  default yvcc_otg_5vLK@LK@vcc28-dvp-regulatorregulator-fixed {  default yvcc28_dvp** #address-cells#size-cellscompatibleinterrupt-parentmodelethernet0gpio0gpio1gpio2gpio3gpio4gpio5gpio6gpio7gpio8i2c0i2c1i2c2i2c3i2c4i2c5mshc0mshc1mshc2mshc3serial0serial1serial2serial3serial4spi0spi1spi2interruptsinterrupt-affinityenable-methodrockchip,pmudevice_typeregresetsoperating-points-v2#cooling-cellsclock-latencyclocksdynamic-power-coefficientcpu0-supplyphandleopp-sharedopp-hzopp-microvoltrangesclock-frequencyclock-output-names#clock-cellsarm,cpu-registers-not-fw-configuredarm,no-tick-in-suspendclock-namesportsmax-frequencyfifo-depthreset-namesstatusbus-widthcap-mmc-highspeedcap-sd-highspeedcard-detect-delaydisable-wppinctrl-namespinctrl-0vmmc-supplyvqmmc-supplynon-removable#io-channel-cellsvref-supplydmasdma-namesreg-shiftreg-io-width#dma-cellsarm,pl330-broken-no-flushparm,pl330-periph-burstpolling-delay-passivepolling-delaythermal-sensorstemperaturehysteresistripcooling-devicepinctrl-1pinctrl-2#thermal-sensor-cellsrockchip,grfrockchip,hw-tshut-temprockchip,hw-tshut-moderockchip,hw-tshut-polarityinterrupt-namesassigned-clocksassigned-clock-parentsclock_in_outphy-supplyphy-modesnps,reset-active-lowsnps,reset-delays-ussnps,reset-gpiotx_delayrx_delayphysphy-namesdr_modesnps,reset-phy-on-wakeg-np-tx-fifo-sizeg-rx-fifo-sizeg-tx-fifo-sizefcs,suspend-voltage-selectorregulator-nameregulator-min-microvoltregulator-max-microvoltregulator-always-onregulator-boot-onregulator-enable-ramp-delayregulator-ramp-delayvin-supplysystem-power-controllervp1-supplyvp2-supplyvp3-supplyvp4-supplyinl1-supplyinl2-supplyinl3-supply#pwm-cells#power-domain-cellspm_qosoffsetmode-normalmode-recoverymode-bootloadermode-loader#reset-cellsassigned-clock-rates#phy-cellsaudio-supplybb-supplydvp-supplyflash0-supplyflash1-supplygpio30-supplygpio1830-supplylcdc-supplysdcard-supplywifi-supply#sound-dai-cellsrockchip,playback-channelsrockchip,capture-channels#iommu-cellsrockchip,disable-mmu-resetpower-domainsiommusremote-endpointddc-i2c-busmali-supplyinterrupt-controller#interrupt-cellsgpio-controller#gpio-cellsrockchip,pinsoutput-lowbias-pull-upbias-pull-downbias-disabledrive-strengthoutput-highio-channelsio-channel-nameskeyup-threshold-microvoltlabellinux,codepress-threshold-microvoltgpioswakeup-sourcelinux,default-triggerstartup-delay-usenable-active-high