8( +hisilicon,hi3660-hikey960hisilicon,hi3660 + 7HiKey960psci arm,psci-0.2=smccpus+cpu-mapcluster0core0Dcore1Dcore2Dcore3Dcluster1core0Dcore1Dcore2Dcore3D cpu@0arm,cortex-a53HcpuTXpscif w P ncpu@1arm,cortex-a53HcpuTXpscif w P cpu@2arm,cortex-a53HcpuTXpscif w P cpu@3arm,cortex-a53HcpuTXpscif w P cpu@100arm,cortex-a73HcpuTXpscifw &cpu@101arm,cortex-a73HcpuTXpscifw cpu@102arm,cortex-a73HcpuTXpscifw cpu@103arm,cortex-a73HcpuTXpscifw  idle-statespscicpu-sleep-0arm,idle-state,< cluster-sleep-0arm,idle-state,@<  cpu-sleep-1arm,idle-state,&<cluster-sleep-1arm,idle-state , T< l2-cache0cacheMY l2-cache1cacheMYopp-table-0operating-points-v2gopp00r@y `opp01r;y 5opp02rSҀy opp03reE@yB@opp04rm5yopp-table-1operating-points-v2gopp10r5үy `opp11rT@y 5opp12rk@y opp13r}yB@opp14rByinterrupt-controller@e82b0000 arm,gic-400@T++ +@ +`   a53-pmuarm,cortex-a53-pmu0a73-pmuarm,cortex-a73-pmu0 timerarm,armv8-timer 0   soc simple-bus+crg_ctrl@fff35000 hisilicon,hi3660-crgctrlsysconTPcrg_rst_controllerhisilicon,hi3660-resetpctrl@e8a09000hisilicon,hi3660-pctrlsysconT蠐 Mcrg_ctrl@fff34000 hisilicon,hi3660-pmuctrlsysconT@sctrl@fff0a000hisilicon,hi3660-sctrlsysconT9iomcu@ffd7e000hisilicon,hi3660-iomcusysconTresethisilicon,hi3660-resetmailbox@e896b000hisilicon,hi3660-mboxT薰 stub_clock@e896b500hisilicon,hi3660-stub-clkT薵  timer@fff14000arm,sp804arm,primecellT@01    timer1timer2apb_pclki2c@ffd71000snps,designware-i2cT v+, < CdefaultQ[okaybLS-I2C0i2c@ffd72000snps,designware-i2cT  w+, < CdefaultQ[okayrt1711h@4erichtek,rt1711hTN[okay CdefaultQconnectorusb-c-connectorbUSB-Chdualrdual}sink22Adports+port@1TendpointPport+endpoint@0TOadv7533@39[okay adi,adv7533T9ports+port@0Tport@1Ti2c@fdf0c000snps,designware-i2cT Q+,7 <xCdefaultQ ! [disabledi2c@fdf0b000snps,designware-i2cT :+,6 <`CdefaultQ"#[okaybLS-I2C1serial@fdf02000arm,pl011arm,primecellT  Jh uartclkapb_pclkCdefaultQ$% [disabledserial@fdf00000arm,pl011arm,primecellT Krxtx&&99 uartclkapb_pclkCdefaultQ'( [disabledserial@fdf03000arm,pl011arm,primecellT0 Lrxtx&&: uartclkapb_pclkCdefaultQ)* [disabledserial@ffd74000arm,pl011arm,primecellT@ r uartclkapb_pclkCdefaultQ+,[okay bLS-UART0serial@fdf01000arm,pl011arm,primecellT Mrxtx&&;; uartclkapb_pclkCdefaultQ-.[okaybluetooth ti,wl1837-st /-serial@fdf05000arm,pl011arm,primecellTP Nrxtx&& << uartclkapb_pclkCdefaultQ01 [disabledserial@fff32000arm,pl011arm,primecellT  O  uartclkapb_pclkCdefaultQ23[okay bLS-UART1dma@fdf30000hisilicon,k3-dma-1.0T  >. 9hi3660_dma&dma-controller@e804b000hisilicon,hisi-pcm-asp-dma-1.0T   Basp_dma_irqrtc@fff04000arm,pl031arm,primecellT@ .  apb_pclkgpio@e8a0b000arm,pl061arm,primecellT蠰 TRbn4  apb_pclkLzTP901[PMU0_SSI][PMU1_SSI][PMU2_SSI][PMU0_CLKOUT][JTAG_TCK][JTAG_TMS]gpio@e8a0c000arm,pl061arm,primecellT URbn4   apb_pclkCz[JTAG_TRST_N][JTAG_TDI][JTAG_TDO]NCNC[I2C3_SCL][I2C3_SDA]NCgpio@e8a0d000arm,pl061arm,primecellT VRbn4!  apb_pclkGzNCNCNCGPIO-JGPIO_020_HDMI_SELGPIO-LGPIO_022_UFSBUCK_INT_NGPIO-Ggpio@e8a0e000arm,pl061arm,primecellT WRbn4"  apb_pclkJz[CSI0_MCLK][CSI1_MCLK]NC[I2C2_SCL][I2C2_SDA][I2C3_SCL][I2C3_SDA]NCgpio@e8a0f000arm,pl061arm,primecellT XRbn4#  apb_pclkAzNCNCPWR_BTN_NGPIO_035_PMU2_ENGPIO_036_USB_HUB_RESETNCNCNCvgpio@e8a10000arm,pl061arm,primecellT YRbn4&$  apb_pclkQzGPIO-HGPIO_041_HDMI_PDTP904TP905NCNCGPIO_046_HUB_VDD33_ENGPIO_047_PMU1_ENgpio@e8a11000arm,pl061arm,primecellT ZRbn4.%  apb_pclkAzNCNCNCGPIO_051_WIFI_ENGPIO-I[SD_DAT1][SD_DAT2][UART1_RXD]xgpio@e8a12000arm,pl061arm,primecellT  [Rbn46&  apb_pclkyz[UART1_TXD][UART0_CTS][UART0_RTS][UART0_RXD][UART0_TXD][SOC_BT_UART4_CTS_N][SOC_BT_UART4_RTS_N][SOC_BT_UART4_RXD]gpio@e8a13000arm,pl061arm,primecellT0 \Rbn4>'  apb_pclk?z[SOC_BT_UART4_TXD]NC[PMU_HKADC_SSI]NCGPIO_068_SELNCNCNCgpio@e8a14000arm,pl061arm,primecellT@ ]Rbn4F(  apb_pclkzNCNCNCGPIO-KNCNCNCNCgpio@e8a15000arm,pl061arm,primecellTP ^Rbn4N)  apb_pclkzNCNCNCNCNCNCNCNCgpio@e8a16000arm,pl061arm,primecellT` _Rbn4V*  apb_pclk$zNC[PCIE_PERST_N]NCNCNCNCNCNC?gpio@e8a17000arm,pl061arm,primecellTp `Rb n4^4e+  apb_pclkzNCNCNCNCgpio@e8a18000arm,pl061arm,primecellT血 aRbn4f,  apb_pclkzNCNCNCNCNCNCNCNCgpio@e8a19000arm,pl061arm,primecellT衐 bRbn4n-  apb_pclkzNCNCNCNCNCNCNCNCgpio@e8a1a000arm,pl061arm,primecellT衠 cRbn4v.  apb_pclk'zNCNCNCNCNCNCGPIO_126_BT_ENTP902/gpio@e8a1b000arm,pl061arm,primecellT衰 dRb/  apb_pclkzgpio@e8a1c000arm,pl061arm,primecellT eRb0  apb_pclkzgpio@ff3b4000arm,pl061arm,primecellT;@ fRbn51  apb_pclkmz[UFS_REF_CLK][UFS_RST_N][SPI1_SCLK][SPI1_DIN][SPI1_DOUT][SPI1_CS]GPIO_150_USER_LED1GPIO_151_USER_LED2>gpio@ff3b5000arm,pl061arm,primecellT;P gRbn52  apb_pclkzNCNCNCNCgpio@e8a1f000arm,pl061arm,primecellT hRbn63  apb_pclk@z[SD_CLK][SD_CMD][SD_DATA0][SD_DATA1][SD_DATA2][SD_DATA3]gpio@e8a20000arm,pl061arm,primecellT iRbn74  apb_pclk^z[WL_SDIO_CLK][WL_SDIO_CMD][WL_SDIO_DATA0][WL_SDIO_DATA1][WL_SDIO_DATA2][WL_SDIO_DATA3]gpio@fff0b000arm,pl061arm,primecellT jRbn89  apb_pclkdz[GPIO_176_PMU_PWR_HOLD]NA[SYSCLK_EN]GPIO_179_WL_WAKEUP_APGPIO_180_HDMI_INTNAGPIO-F[I2C0_SCL]Jgpio@fff0c000arm,pl061arm,primecellT kRbn89  apb_pclk^z[I2C0_SDA][I2C1_SCL][I2C1_SDA][I2C1_SCL][I2C1_SDA]GPIO_189_USER_LED3GPIO_190_USER_LED4wgpio@fff0d000arm,pl061arm,primecellT lRbn8 9  apb_pclktz[PCM_DI][PCM_DO][PCM_CLK][PCM_FS][GPIO_196_I2S2_DI][GPIO_197_I2S2_DO][GPIO_198_I2S2_XCLK][GPIO_199_I2S2_XFS]gpio@fff0e000arm,pl061arm,primecellT mRb n889  apb_pclkzzNCNCGPIO_202_VBUS_TYPECGPIO_203_SD_DETGPIO_204_PMU12_IRQ_NGPIO_205_WIFI_ACTIVEGPIO_206_USBSW_SELGPIO_207_BT_ACTIVE@gpio@fff0f000arm,pl061arm,primecellT nRbn89  apb_pclkLzGPIO-AGPIO-BGPIO-CGPIO-DGPIO-E[PCIE_CLKREQ_N][PCIE_WAKE_N][SPI0_CLK]gpio@fff10000arm,pl061arm,primecellT oRbn8$9  apb_pclkBz[SPI0_DIN][SPI0_DOUT][SPI0_CS]GPIO_219_CC_INTNCNC[PMU_INT]gpio@fff1d000arm,pl061arm,primecellT Rb9  apb_pclkzspi@ffd68000arm,pl022arm,primecellTր+ t sspclkapb_pclkCdefaultQ:; [okaybLS-SPI0spi@ff3b3000arm,pl022arm,primecellT;0+ 855 sspclkapb_pclkCdefaultQ<= >[okaybHS-SPI1pcie@f4000000hisilicon,kirin960-pcie@T? dbiapbphyconfig+Hpci Bmsi(RSQP: pcie_phy_refpcie_auxpcie_apb_phypcie_apb_syspcie_aclk ?ufs@ff3b0000#hisilicon,hi3660-ufsjedec,ufs-1.1 T;;  fe ref_clkphy_clk < rstdwmmc1@ff37f000hisilicon,hi3660-dw-mshcT7+ K ciubiu,0 <reset9[okay-7HUbo} @Cdefault QABCDEdwmmc2@ff3ff000hisilicon,hi3660-dw-mshcT?+ L ciubiu <reset[okay-Cdefault QFGHIwlcore@2 ti,wl1837T Jwatchdog@e8a06000arm,sp805arm,primecellT` ,   wdog_clkapb_pclkwatchdog@e8a07000arm,sp805arm,primecellTp -   wdog_clkapb_pclktsensor@fff30000hisilicon,hi3660-tsensorT Kthermal-zonescls0-thermald!Ktripstrip-point01=Opassivetrip-point11$=OpassiveLcooling-mapsmap0HLM0Zmap1HLM0Z usb3_otg_bc@ff200000/hisilicon,hi3660-usb3-otg-bcsysconsimple-mfdT usb-phyhisilicon,hi3660-usb-phyitM$fNusb@ff100000 snps,dwc3TI refbus_earlyI C@0<N usb3-phyotg super-speed utmi4Kd}hostport+endpoint@0TOendpoint@1TPetm@ecc40000"arm,coresight-etm4xarm,primecellT  apb_pclkDout-portsportendpointQVetm@ecd40000"arm,coresight-etm4xarm,primecellT  apb_pclkDout-portsportendpointRWetm@ece40000"arm,coresight-etm4xarm,primecellT  apb_pclkDout-portsportendpointSXetm@ecf40000"arm,coresight-etm4xarm,primecellT  apb_pclkDout-portsportendpointTYfunnel@ec801000+arm,coresight-dynamic-funnelarm,primecellT  apb_pclkout-portsportendpointUZin-ports+port@0TendpointVQport@1TendpointWRport@2TendpointXSport@3TendpointYTetf@ec802000 arm,coresight-tmcarm,primecellT   apb_pclkin-portsportendpointZUout-portsportendpoint[hetm@ed440000"arm,coresight-etm4xarm,primecellTD  apb_pclkDout-portsportendpoint\aetm@ed540000"arm,coresight-etm4xarm,primecellTT  apb_pclkDout-portsportendpoint]betm@ed640000"arm,coresight-etm4xarm,primecellTd  apb_pclkDout-portsportendpoint^cetm@ed740000"arm,coresight-etm4xarm,primecellTt  apb_pclkD out-portsportendpoint_dfunnel@ed001000+arm,coresight-dynamic-funnelarm,primecellT  apb_pclkout-portsportendpoint`ein-ports+port@0Tendpointa\port@1Tendpointb]port@2Tendpointc^port@3Tendpointd_etf@ed002000 arm,coresight-tmcarm,primecellT   apb_pclkin-portsportendpointe`out-portsportendpointfifunnelarm,coresight-static-funnel  apb_pclkout-portsportendpointgkin-ports+port@0Tendpointh[port@1Tendpointiffunnel@ec031000+arm,coresight-dynamic-funnelarm,primecellT  apb_pclkout-portsportendpointjlin-ports+port@0Tendpointkgetf@ec036000 arm,coresight-tmcarm,primecellT`  apb_pclkin-portsportendpointljout-portsportendpointmnreplicator arm,coresight-static-replicator  apb_pclkin-portsportendpointnmout-ports+port@0Tendpointoqport@1Tendpointpretr@ec033000 arm,coresight-tmcarm,primecellT0  apb_pclkin-portsportendpointqotpiu@ec032000!arm,coresight-tpiuarm,primecellT   apb_pclkin-portsportendpointrpgpio-rangespinmux@e896c000pinctrl-singleT#2D b sst4pmu-pins  csi0-pwd-n-pinsDcsi1-pwd-n-pinsLisp0-pinsXdhisp1-pins\lppwr-key-pinsti2c3-pins,0 i2c4-pinspcie-perstn-pins\usbhub5734-pins uart0-pins$uart1-pins 'uart2-pins )uart3-pins +uart4-pins -uart5-pins 0uart6-pins 2cam0-rst-pinscam1-rst-pins$pinmux@ff37e000pinctrl-singleT72#D bs6sd-pins0 Apinmux@ff3b6000pinctrl-singleT;`0#2D bs 5ufs-pinsspi3-pins  <pinmux@ff3fd000pinctrl-singleT?#2D bs7sdio-pins0 Fpinmux@fff11000pinctrl-singleT#2D bs*8i2s2-pins DHLPslimbus-pins,0i2c0-pinsi2c1-pins i2c7-pins$("pcie-pinsspi2-pins :i2s0-pins 48<@pinmux@e896c800pinconf-singleT#D pmu-cfg-pins   i2c3-cfg-pins8<!csi0-pwd-n-cfg-pinsPcsi1-pwd-n-cfg-pinsXisp0-cfg-pinsdptisp1-cfg-pinshx|pwr-key-cfg-pinsuuart1-cfg-pins (uart2-cfg-pins *uart5-cfg-pins 1cam0-rst-cfg-pinsuart0-cfg-pins%uart6-cfg-pins 3uart3-cfg-pins ,uart4-cfg-pins .cam1-rst-cfg-pins0pinmux@ff3b6800pinconf-singleT;h#D ufs-cfg-pins0spi3-cfg-pins   =pinmux@ff3fd800pinconf-singleT?#D sdio-clk-cfg-pinsGsdio-cfg-pins( Hpinmux@ff37e800pinconf-singleT7#D sd-clk-cfg-pinsBsd-cfg-pins( Cpinmux@fff11800pinconf-singleT#D i2c0-cfg-pins i2c1-cfg-pins$(i2c7-cfg-pins,0#slimbus-cfg-pins48i2s0-cfg-pins @DHLi2s2-cfg-pins PTX\pcie-cfg-pinsspi2-cfg-pins  ;usb-cfg-pinsaliases/soc/dwmmc1@ff37f000 /soc/dwmmc2@ff3ff000/soc/serial@fdf02000/soc/serial@fdf00000/soc/serial@fdf03000'/soc/serial@ffd74000//soc/serial@fdf010007/soc/serial@fdf05000?/soc/serial@fff32000chosenGserial6:115200n8memory@0HmemoryTreserved-memory+ramoops@32000000ramoopsT2S_lreboot-mode-syscon@32100000sysconsimple-mfdT2reboot-modesyscon-reboot-modexwfUwfUwfUkeys gpio-keysCdefaultQtukey-power v bGPIO Powertleds gpio-ledsled-user-1 bgreen:user1 > heartbeatled-user-2 bgreen:user2 >noneled-user-3 bgreen:user3 wmmc0led-user-4 bgreen:user4 wnoneled-wlan byellow:wlan @phy0txoffled-btbblue:bt @ hci0-poweroffpmic@fff34000hisilicon,hi6421v530-pmicT@regulatorsLDO3 VOUT3_1V85 w@ ! 5xLDO9VOUT9_1V8_2V95  2Z 5ELDO11VOUT11_1V8_2V95  2Z 5LDO15 VOUT15_3V0  - Q c 5xLDO16 VOUT16_2V95  - 5hDwlan-en-1-8vregulator-fixedwlan-en-regulator w@ w@ wx |p Ifirmwareopteelinaro,optee-tz=smc compatibleinterrupt-parent#address-cells#size-cellsmodelmethodcpudevice_typeregenable-methodnext-level-cachecpu-idle-statescapacity-dmips-mhzclocksoperating-points-v2#cooling-cellsdynamic-power-coefficientphandleentry-methodlocal-timer-stoparm,psci-suspend-paramentry-latency-usexit-latency-usmin-residency-uscache-levelcache-unifiedopp-sharedopp-hzopp-microvoltclock-latency-ns#interrupt-cellsinterrupt-controllerinterruptsinterrupt-affinityranges#clock-cells#reset-cellshisi,rst-syscon#mbox-cellsmboxesclock-namesclock-frequencyresetspinctrl-namespinctrl-0statuslabeldata-rolepower-roletry-power-rolesource-pdossink-pdosop-sink-microwattremote-endpointadi,dsi-lanesdma-namesdmasenable-gpiosmax-speed#dma-cellsdma-channelsdma-requestsdma-channel-maskdma-no-ccidma-typeinterrupt-namesgpio-controller#gpio-cellsgpio-rangesgpio-line-namesnum-cscs-gpiosreg-namesbus-rangenum-lanesinterrupt-map-maskinterrupt-mapreset-gpiosfreq-table-hzreset-nameshisilicon,peripheral-sysconcard-detect-delaybus-widthcap-sd-highspeedsd-uhs-sdr12sd-uhs-sdr25sd-uhs-sdr50sd-uhs-sdr104disable-wpcd-gpiosvmmc-supplyvqmmc-supplynon-removablebroken-cdcap-power-off-card#thermal-sensor-cellspolling-delaypolling-delay-passivesustainable-powerthermal-sensorstemperaturehysteresistripcontributioncooling-device#phy-cellshisilicon,pericrg-sysconhisilicon,pctrl-sysconhisilicon,eye-diagram-paramassigned-clocksassigned-clock-ratesphysphy-namesdr_modemaximum-speedphy_typesnps,dis-del-phy-power-chg-quirksnps,lfps_filter_quirksnps,dis_u2_susphy_quirksnps,dis_u3_susphy_quirksnps,tx_de_emphasis_quirksnps,tx_de_emphasissnps,dis_enblslpm_quirksnps,gctl-reset-quirkusb-role-switchrole-switch-default-mode#pinctrl-single,gpio-range-cells#pinctrl-cells#gpio-range-cellspinctrl-single,register-widthpinctrl-single,function-maskpinctrl-single,gpio-rangepinctrl-single,pinspinctrl-single,bias-pulldownpinctrl-single,bias-pulluppinctrl-single,drive-strengthmshc1mshc2serial0serial1serial2serial3serial4serial5serial6stdout-pathrecord-sizeconsole-sizeftrace-sizeoffsetmode-normalmode-bootloadermode-recoverywakeup-sourcelinux,codelinux,default-triggerpanic-indicatordefault-stateregulator-nameregulator-min-microvoltregulator-max-microvoltregulator-enable-ramp-delayregulator-boot-onregulator-always-ongpiostartup-delay-usenable-active-high