c8]P(U]#geniatech,xpi-3128rockchip,rk3128 +7Geniatech XPI-3128aliases=/pinctrl/gpio@2007c000C/pinctrl/gpio@20080000I/pinctrl/gpio@20084000O/pinctrl/gpio@20088000U/i2c@20072000Z/i2c@20056000_/i2c@2005a000d/i2c@2005e000i/serial@20060000q/serial@20064000y/serial@20068000/ethernet@2008c000/mmc@1021c000/mmc@10214000arm-pmuarm,cortex-a7-pmu0LMNOcpus+rockchip,rk3036-smpcpu@f00cpuarm,cortex-a7@cpu@f01cpuarm,cortex-a7cpu@f02cpuarm,cortex-a7cpu@f03cpuarm,cortex-a7opp-table-0operating-points-v2#opp-216000000.  5~~7opp-408000000.Q 5~~7opp-600000000.#F 5~~7opp-696000000.)| 57opp-816000000.0, 5g8g87Copp-1008000000.< 5OO7opp-1200000000.G 5777opp-table-1operating-points-v2 opp-200000000.  5opp-300000000. 5opp-400000000.ׄ 500opp-480000000.8 5timerarm,armv7-timer0   Osn6oscillator fixed-clocksn6xin24m(sram@10080000 mmio-sram +  smp-sram@0rockchip,rk3066-smp-sramgpu@10090000"rockchip,rk3128-maliarm,mali-400 Hgpgpmmupp0ppmmu0pp1ppmmu1 buscore x okay syscon@100a0000&rockchip,rk3128-pmusysconsimple-mfd power-controller!rockchip,rk3128-power-controller+ power-domain@1Ez power-domain@2(power-domain@3qos@1012d000rockchip,rk3128-qossyscon qos@1012e000rockchip,rk3128-qossyscon qos@1012f000rockchip,rk3128-qossyscon qos@1012f080rockchip,rk3128-qossyscon  qos@1012f100rockchip,rk3128-qossyscon  qos@1012f180rockchip,rk3128-qossyscon qos@1012f200rockchip,rk3128-qossyscon interrupt-controller@10139000arm,cortex-a7-gic     usb@101800002rockchip,rk3128-usbrockchip,rk3066-usbsnps,dwc2 otg(otg0BQ@ ` eusb2-phyokayo}usb@101c0000 generic-ehci `eusbokayusb@101e0000 generic-ohci `eusb disabledmmc@102140000rockchip,rk3128-dw-mshcrockchip,rk3288-dw-mshc!@@  Drvbiuciuciu-driveciu-sample rx-txрQresetokaydefault mmc@102180000rockchip,rk3128-dw-mshcrockchip,rk3288-dw-mshc!@  Eswbiuciuciu-driveciu-sample rx-txрRreset disabledmmc@1021c0000rockchip,rk3128-dw-mshcrockchip,rk3288-dw-mshc!@  Guybiuciuciu-driveciu-sample rx-txрSresetokaydefault *7nand-controller@10500000(rockchip,rk3128-nfcrockchip,rk2928-nfcP@ Cahbnfcdefault  !"#$%&' disabledclock-controller@20000000rockchip,rk3128-cru (xin24m=)JWg#gsyscon@20008000&rockchip,rk3128-grfsysconsimple-mfd +)usb2phy@17crockchip,rk3128-usb2phy| phyclk usb480m_phyW|*okay*host-port 5 linestateokayotg-port$#34otg-bvalidotg-idlinestateokaytimer@20044000,rockchip,rk3128-timerrockchip,rk3288-timer @  aU pclktimertimer@20044020,rockchip,rk3128-timerrockchip,rk3288-timer @  aV pclktimertimer@20044040,rockchip,rk3128-timerrockchip,rk3288-timer @@  ;aW pclktimertimer@20044060,rockchip,rk3128-timerrockchip,rk3288-timer @`  <aX pclktimertimer@20044080,rockchip,rk3128-timerrockchip,rk3288-timer @  =aY pclktimertimer@200440a0,rockchip,rk3128-timerrockchip,rk3288-timer @  >aZ pclktimerwatchdog@2004c000 rockchip,rk3128-wdtsnps,dw-wdt  "? disabledpwm@20050000(rockchip,rk3128-pwmrockchip,rk3288-pwm ^default+ disabledpwm@20050010(rockchip,rk3128-pwmrockchip,rk3288-pwm ^default,okayPpwm@20050020(rockchip,rk3128-pwmrockchip,rk3288-pwm  ^default-okayQpwm@20050030(rockchip,rk3128-pwmrockchip,rk3288-pwm 0^default. disabledi2c@20056000(rockchip,rk3128-i2crockchip,rk3288-i2c ` i2cMdefault/+ disabledi2c@2005a000(rockchip,rk3128-i2crockchip,rk3288-i2c  i2cNdefault0+ disabledi2c@2005e000(rockchip,rk3128-i2crockchip,rk3288-i2c  i2cOdefault1+ disabledserial@20060000&rockchip,rk3128-uartsnps,dw-apb-uart  sn6MUbaudclkapb_pclktxrxdefault 234 disabledserial@20064000&rockchip,rk3128-uartsnps,dw-apb-uart @ sn6NVbaudclkapb_pclktxrxdefault5okayserial@20068000&rockchip,rk3128-uartsnps,dw-apb-uart  sn6OWbaudclkapb_pclktxrxdefault6 disabledsaradc@2006c000rockchip,saradc  [>saradcapb_pclkW saradc-apbokayDi2c@20072000(rockchip,rk3128-i2crockchip,rk3288-i2c   i2cLdefault7+ disabledspi@20074000(rockchip,rk3128-spirockchip,rk3066-spi @ ARspiclkapb_pclk txrxdefault89:;<+ disableddma-controller@20078000arm,pl330arm,primecell @ apb_pclkethernet@2008c000rockchip,rk3128-gmac @89macirqeth_wake_irq8~oMstmmacethmac_clk_rxmac_clk_txclk_mac_refclk_mac_refoutaclk_macpclk_mac8 stmmaceth=))okay7outputD=OrmiiX>W|gdefault?mdiosnps,dwmac-mdio+ethernet-phy@1ethernet-phy-ieee802.3-c22cdm } @defaultA>pinctrlrockchip,rk3128-pinctrl=)+gpio@2007c000rockchip,gpio-bank  $@HEADER_5HEADER_3HEADER_22HEADER_23HEADER_19HEADER_26HEADER_21HEADER_24HEADER_18HEADER_36HEADER_13Igpio@20080000rockchip,gpio-bank  %ApHEADER_7HEADER_35HEADER_33HEADER_37HEADER_40HEADER_38HEADER_11HEADER_29HEADER_31Mgpio@20084000rockchip,gpio-bank @ &B:HEADER_27HEADER_8HEADER_10@gpio@20088000rockchip,gpio-bank  'C;HEADER_32HEADER_12HEADER_15Epcfg-pull-defaultCpcfg-pull-noneBemmcemmc-clkBemmc-cmdCemmc-cmd1Cemmc-pwrCemmc-bus1Cemmc-bus4@CCCCemmc-bus8CCCCCCCCgmacrgmii-pinsC C C C CCCCCCCCCCCrmii-pinsC C CCCCCCCC?hdmihdmii2c-xfer BBhdmi-hpdBhdmi-cecBi2c0i2c0-xfer BB7i2c1i2c1-xfer BB/i2c2i2c2-xfer BB0i2c3i2c3-xfer BB1i2si2s-bus`B B B B BBi2s1-bus`BBBBBBlcdclcdc-dclkBlcdc-den Blcdc-hsync Blcdc-vsync Blcdc-rgb24 B BBBBBBBBBBBBBnfcflash-aleB flash-cleB"flash-wrnB'flash-rdnB%flash-rdyB&flash-cs0B#flash-dqsB$flash-bus8BBBBBBBB!pwm0pwm0-pinB+pwm1pwm1-pinB,pwm2pwm2-pinB-pwm3pwm3-pinB.sdiosdio-clkBsdio-cmdCsdio-pwrenCsdio-bus4@CCCCsdmmcsdmmc-clkBsdmmc-cmdCsdmmc-detCsdmmc-wpCsdmmc-pwrenCNsdmmc-bus4@CCCCspdifspdif-txBspi0spi0-clkC:spi0-cs0 C;spi0-tx C8spi0-rx C9spi0-cs1 C<spi1-clkCspi1-cs0Cspi1-txCspi1-rxCspi1-cs1Cspi2-clk Cspi2-cs0Cspi2-tx Cspi2-rx Cuart0uart0-xfer CB2uart0-ctsB3uart0-rtsB4uart1uart1-xfer  C C5uart1-ctsBuart1-rts Buart2uart2-xfer CB6uart2-ctsBuart2-rtsBdp83848cdp83848c-rstBAir-receiverir-intBHledspower-ledBJspd-led BKusb2host-drvBGmemory@60000000memory`@chosen/serial@20064000adc-keys adc-keysDbuttons!2Zbutton-recovery ;RecoveryAhLdc-5v-regulatorregulator-fixedfDC_5VuLK@LK@Fhost-pwr-5v-regulatorregulator-fixed E fHOST_PWR_5VuLK@LK@FdefaultGir-receivergpio-ir-receiver EdefaultHleds gpio-ledsled-power IpowerondefaultJled-spd E landefaultKmcu3v3-regulatorregulator-fixedfMCU3V3u2Z2Zvcc-ddr-regulatorregulator-fixedfVCC_DDRu``Lvcc-io-regulatorregulator-fixedfVCC_IOu2Z2ZLvcc-lan-regulatorregulator-fixedfVCC_LANu2Z2Z=vcc-sd-regulatorregulator-fixed MfVCC_SDu2Z2ZdefaultNvcc-sys-regulatorregulator-fixedfVCC_SYSuLK@LK@FLvcc33-hdmi-regulatorregulator-fixed fVCC33_HDMIu2Z2ZOvcca-33-regulatorregulator-fixedfVCCA_33u2Z2ZLOvdd-11-regulatorregulator-fixedfVDD_11uLvdd11-hdmi-regulatorregulator-fixed fVDD11_HDMIuvdd-arm-regulatorpwm-regulatorfVDD_ARMPa!Lu \vdd-log-regulatorpwm-regulatorfVDD_LOGQa,d!Lu\@  compatibleinterrupt-parent#address-cells#size-cellsmodelgpio0gpio1gpio2gpio3i2c0i2c1i2c2i2c3serial0serial1serial2ethernet0mmc0mmc1interruptsinterrupt-affinityenable-methoddevice_typeregclock-latencyclocksresetsoperating-points-v2#cooling-cellscpu-supplyphandleopp-sharedopp-hzopp-microvoltopp-suspendarm,cpu-registers-not-fw-configuredclock-frequencyclock-output-names#clock-cellsrangesinterrupt-namesclock-namespower-domainsstatusmali-supply#power-domain-cellspm_qosinterrupt-controller#interrupt-cellsdr_modeg-np-tx-fifo-sizeg-rx-fifo-sizeg-tx-fifo-sizephysphy-namesvusb_a-supplyvusb_d-supplydmasdma-namesfifo-depthmax-frequencyreset-namesbus-widthvmmc-supplypinctrl-namespinctrl-0disable-wpcap-sd-highspeedno-mmcno-sdiocap-mmc-highspeedmmc-ddr-3_3vno-sdrockchip,grf#reset-cellsassigned-clocksassigned-clock-ratesassigned-clock-parents#phy-cells#pwm-cellsreg-io-widthreg-shift#io-channel-cellsvref-supplyarm,pl330-broken-no-flushparm,pl330-periph-burst#dma-cellsrx-fifo-depthtx-fifo-depthclock_in_outphy-supplyphy-modephy-handlemax-speedreset-assert-usreset-deassert-usreset-gpiosgpio-controller#gpio-cellsgpio-line-namesbias-pull-pin-defaultbias-disablerockchip,pinsstdout-pathio-channelsio-channel-nameskeyup-threshold-microvoltlabellinux,codepress-threshold-microvoltregulator-nameregulator-min-microvoltregulator-max-microvoltregulator-always-onregulator-boot-ongpiostartup-delay-usvin-supplyenable-active-highfunctioncolordefault-statepwmspwm-supplypwm-dutycycle-rangeregulator-ramp-delay