98( I%amarula,vyasa-rk3288rockchip,rk3288&7Amarula Vyasa-RK3288aliases=/ethernet@ff290000G/pinctrl/gpio@ff750000M/pinctrl/gpio@ff780000S/pinctrl/gpio@ff790000Y/pinctrl/gpio@ff7a0000_/pinctrl/gpio@ff7b0000e/pinctrl/gpio@ff7c0000k/pinctrl/gpio@ff7d0000q/pinctrl/gpio@ff7e0000w/pinctrl/gpio@ff7f0000}/i2c@ff650000/i2c@ff140000/i2c@ff660000/i2c@ff150000/i2c@ff160000/i2c@ff170000/mmc@ff0f0000/mmc@ff0c0000/mmc@ff0d0000/mmc@ff0e0000/serial@ff180000/serial@ff190000/serial@ff690000/serial@ff1b0000/serial@ff1c0000/spi@ff110000/spi@ff120000/spi@ff130000arm-pmuarm,cortex-a12-pmu0cpusrockchip,rk3066-smpcpu@500#cpuarm,cortex-a12/3:N]@krr cpu@501#cpuarm,cortex-a12/3:N]@krr cpu@502#cpuarm,cortex-a12/3:N]@krr cpu@503#cpuarm,cortex-a12/3:N]@krr opp-table-0operating-points-v2opp-126000000 opp-216000000  opp-312000000 opp-408000000Q opp-600000000#F opp-696000000)|~opp-8160000000,B@opp-1008000000<opp-1200000000Gopp-1416000000TfrOopp-1512000000ZJ opp-1608000000_"preserved-memorydma-unusable@fe000000/oscillator fixed-clockn6xin24m timerarm,armv7-timer0   n6timer@ff810000rockchip,rk3288-timer/  H ka  1pclktimerdisplay-subsystemrockchip,display-subsystem= mmc@ff0c0000rockchip,rk3288-dw-mshcCр kDrv1biuciuciu-driveciu-sampleQ / @3\resethokayoydefault mmc@ff0d0000rockchip,rk3288-dw-mshcCр kEsw1biuciuciu-driveciu-sampleQ !/ @3\reset hdisabledmmc@ff0e0000rockchip,rk3288-dw-mshcCр kFtx1biuciuciu-driveciu-sampleQ "/@3\reset hdisabledmmc@ff0f0000rockchip,rk3288-dw-mshcCр kGuy1biuciuciu-driveciu-sampleQ #/@3\resethokayoydefaultsaradc@ff100000rockchip,saradc/ $kI[1saradcapb_pclk3W \saradc-apb hdisabledspi@ff110000(rockchip,rk3288-spirockchip,rk3066-spikAR1spiclkapb_pclk   txrx ,default/ hdisabledspi@ff120000(rockchip,rk3288-spirockchip,rk3066-spikBS1spiclkapb_pclk  txrx -default / hdisabledspi@ff130000(rockchip,rk3288-spirockchip,rk3066-spikCT1spiclkapb_pclk txrx .default!"#$/ hdisabledi2c@ff140000rockchip,rk3288-i2c/ >1i2ckMdefault% hdisabledi2c@ff150000rockchip,rk3288-i2c/ ?1i2ckOdefault& hdisabledi2c@ff160000rockchip,rk3288-i2c/ @1i2ckPdefault' hdisabledi2c@ff170000rockchip,rk3288-i2c/ A1i2ckQdefault(hokayqserial@ff180000&rockchip,rk3288-uartsnps,dw-apb-uart/ 7#kMU1baudclkapb_pclk txrxdefault) hdisabledserial@ff190000&rockchip,rk3288-uartsnps,dw-apb-uart/ 8#kNV1baudclkapb_pclk txrxdefault* hdisabledserial@ff690000&rockchip,rk3288-uartsnps,dw-apb-uart/i 9#kOW1baudclkapb_pclkdefault+hokayserial@ff1b0000&rockchip,rk3288-uartsnps,dw-apb-uart/ :#kPX1baudclkapb_pclk txrxdefault, hdisabledserial@ff1c0000&rockchip,rk3288-uartsnps,dw-apb-uart/ ;#kQY1baudclkapb_pclk   txrxdefault- hdisableddma-controller@ff250000arm,pl330arm,primecell/%@0;Vk 1apb_pclkthermal-zonesreserve-thermalm.cpu-thermalmd.tripscpu_alert0p*passive/cpu_alert1$*passive0cpu_crit_ *criticalcooling-mapsmap0/0map100gpu-thermalmd.tripsgpu_alert0p*passive1gpu_crit_ *criticalcooling-mapsmap01 2tsadc@ff280000rockchip,rk3288-tsadc/( %kHZ1tsadcapb_pclk3 \tsadc-apbinitdefaultsleep3435shokay1.ethernet@ff290000rockchip,rk3288-gmac/)Lmacirqeth_wake_irq58kfgc]M1stmmacethmac_clk_rxmac_clk_txclk_mac_refclk_mac_refoutaclk_macpclk_mac3B \stmmacethhokay\l6inputdefault789:;rgmii 'B@ <0usb@ff500000 generic-ehci/P k=usbhokayusb@ff520000 generic-ohci/R )k=usb hdisabledusb@ff5400002rockchip,rk3288-usbrockchip,rk3066-usbsnps,dwc2/T k1otghost> usb2-phyhokaydefault?usb@ff5800002rockchip,rk3288-usbrockchip,rk3066-usbsnps,dwc2/X k1otgotg1@@@ @ usb2-phyhokayOAusb@ff5c0000 generic-ehci/\ k hdisableddma-controller@ff600000arm,pl330arm,primecell/`@0;Vk 1apb_pclk hdisabledi2c@ff650000rockchip,rk3288-i2c/e <1i2ckLdefaultBhokaypmic@1brockchip,rk808/&Cxin32krk808-clkout2defaultDE[|FFFFFFFFFregulatorsDCDC_REG1vdd_arm q8pPd regulator-state-memvDCDC_REG2vdd_gpu P8Pdvregulator-state-memB@DCDC_REG3vcc_ddrPdregulator-state-memDCDC_REG4vcc_io 2Z82ZPdregulator-state-mem2ZLDO_REG1vcc_tp 2Z82ZPdregulator-state-mem2ZLDO_REG2 vcc_codec 2Z82ZPdregulator-state-memvLDO_REG3vdd_10 B@8B@Pdregulator-state-memB@LDO_REG4vcc_gps w@8w@Pdregulator-state-memw@LDO_REG5 vccio_sd w@82ZPdregulator-state-mem2ZLDO_REG6 vdd10_lcd B@8B@Pdregulator-state-memB@LDO_REG7vcc_18 w@8w@PdZregulator-state-memw@LDO_REG8 vcc18_lcd w@8w@Pdregulator-state-memw@SWITCH_REG1vcc_sd 2Z82ZPdregulator-state-memSWITCH_REG2vcc_lan 2Z82ZPd;regulator-state-memi2c@ff660000rockchip,rk3288-i2c/f =1i2ckNdefaultG hdisabledpwm@ff680000rockchip,rk3288-pwm/hdefaultHk_ hdisabledpwm@ff680010rockchip,rk3288-pwm/hdefaultIk_ hdisabledpwm@ff680020rockchip,rk3288-pwm/h defaultJk_ hdisabledpwm@ff680030rockchip,rk3288-pwm/h0defaultKk_ hdisabledsram@ff700000 mmio-sram/ppsmp-sram@0rockchip,rk3066-smp-sram/sram@ff720000#rockchip,rk3288-pmu-srammmio-sram/rpower-management@ff730000&rockchip,rk3288-pmusysconsimple-mfd/spower-controller!rockchip,rk3288-power-controller\hl ^power-domain@9/ kchgfdehilkj$LMNOPQRSTpower-domain@11/ kopUVpower-domain@12/ kWpower-domain@13/ kXYreboot-modesyscon-reboot-modeRBRB RB RBsyscon@ff740000rockchip,rk3288-sgrfsyscon/tclock-controller@ff760000rockchip,rk3288-cru/vk 1xin24m5&H\jk$3#gׄeрxhрxhsyscon@ff770000&rockchip,rk3288-grfsysconsimple-mfd/w5edp-phyrockchip,rk3288-dp-phykh124mH hdisablednio-domains"rockchip,rk3288-io-voltage-domainhokaySZ`juZ;Zusbphyrockchip,rk3288-usb-phyhokayusb-phy@320H/ k]1phyclk3 \phy-reset@usb-phy@334H/4k^1phyclk3 \phy-reset=usb-phy@348H/Hk_1phyclk3 \phy-reset>watchdog@ff800000 rockchip,rk3288-wdtsnps,dw-wdt/kp Ohokaysound@ff8b0000,rockchip,rk3288-spdifrockchip,rk3066-spdif/kT 1mclkhclk [tx 6default\5 hdisabledi2s@ff890000(rockchip,rk3288-i2srockchip,rk3066-i2s/ 5kR1i2s_clki2s_hclk [[txrxdefault] hdisabledcrypto@ff8a0000rockchip,rk3288-crypto/@ 0 k}1aclkhclksclkapb_pclk3 \crypto-rstiommu@ff900800rockchip,iommu/@ k 1aclkiface hdisablediommu@ff914000rockchip,iommu /@P k 1aclkiface( hdisabledrga@ff920000rockchip,rk3288-rga/ kj1aclkhclksclkC^ 3ilm \coreaxiahbvop@ff930000rockchip,rk3288-vop / k1aclk_vopdclk_vophclk_vopC^ 3def \axiahbdclkQ_hokayport endpoint@0/X`rendpoint@1/Xaoendpoint@2/Xbiendpoint@3/Xcliommu@ff930300rockchip,iommu/ k 1aclkifaceC^ hokay_vop@ff940000rockchip,rk3288-vop / k1aclk_vopdclk_vophclk_vopC^ 3 \axiahbdclkQdhokayport endpoint@0/Xesendpoint@1/Xfpendpoint@2/Xgjendpoint@3/Xhmiommu@ff940300rockchip,iommu/ k 1aclkifaceC^ hokayddsi@ff960000*rockchip,rk3288-mipi-dsisnps,dw-mipi-dsi/@ k~d 1refpclkC^ 5 hdisabledportsport@0/endpoint@0/Xibendpoint@1/Xjgport@1/lvds@ff96c000rockchip,rk3288-lvds/@kg 1pclk_lvdslcdckC^ 5 hdisabledportsport@0/endpoint@0/Xlcendpoint@1/Xmhport@1/dp@ff970000rockchip,rk3288-dp/@ bkic1dppclkndpC^ 3o\dp5 hdisabledportsport@0/endpoint@0/Xoaendpoint@1/Xpfport@1/hdmi@ff980000rockchip,rk3288-dw-hdmi/# gkhmn1iahbisfrcecC^ 5hokayhqportsport@0/endpoint@0/Xr`endpoint@1/Xseport@1/video-codec@ff9a0000rockchip,rk3288-vpu/   Lvepuvdpuk 1aclkhclkQtC^ iommu@ff9a0800rockchip,iommu/ k 1aclkifaceC^ tiommu@ff9c0440rockchip,iommu /@@@ ok 1aclkiface hdisabledgpu@ffa30000#rockchip,rk3288-maliarm,mali-t760/$ Ljobmmugpuk:uNC^ hokaytv2opp-table-1operating-points-v2uopp-100000000~opp-200000000 ~opp-300000000B@opp-400000000ׄopp-600000000#Fqos@ffaa0000rockchip,rk3288-qossyscon/ Xqos@ffaa0080rockchip,rk3288-qossyscon/ Yqos@ffad0000rockchip,rk3288-qossyscon/ Mqos@ffad0100rockchip,rk3288-qossyscon/ Nqos@ffad0180rockchip,rk3288-qossyscon/ Oqos@ffad0400rockchip,rk3288-qossyscon/ Pqos@ffad0480rockchip,rk3288-qossyscon/ Qqos@ffad0500rockchip,rk3288-qossyscon/ Lqos@ffad0800rockchip,rk3288-qossyscon/ Rqos@ffad0880rockchip,rk3288-qossyscon/ Sqos@ffad0900rockchip,rk3288-qossyscon/ Tqos@ffae0000rockchip,rk3288-qossyscon/ Wqos@ffaf0000rockchip,rk3288-qossyscon/ Uqos@ffaf0080rockchip,rk3288-qossyscon/ Vdma-controller@ffb20000arm,pl330arm,primecell/@0;Vk 1apb_pclk[efuse@ffb40000rockchip,rk3288-efuse/ kq 1pclk_efusecpu-id@7/cpu_leakage@17/interrupt-controller@ffc01000 arm,gic-400@/ @ `   pinctrlrockchip,rk3288-pinctrl5gpio@ff750000rockchip,gpio-bank/u Qk@Cgpio@ff780000rockchip,gpio-bank/x RkAgpio@ff790000rockchip,gpio-bank/y SkBgpio@ff7a0000rockchip,gpio-bank/z TkCgpio@ff7b0000rockchip,gpio-bank/{ UkD<gpio@ff7c0000rockchip,gpio-bank/| VkEgpio@ff7d0000rockchip,gpio-bank/} WkFgpio@ff7e0000rockchip,gpio-bank/~ XkG~gpio@ff7f0000rockchip,gpio-bank/ YkHhdmihdmi-cec-c0whdmi-cec-c7whdmi-ddc wwhdmi-ddc-unwedge xwvcc50-hdmi-en wpcfg-output-lowxpcfg-pull-upypcfg-pull-downzpcfg-pull-nonewpcfg-pull-none-12ma  {suspendglobal-pwroffwEddrio-pwroffwddr0-retentionyddr1-retentionyedpedp-hpd zi2c0i2c0-xfer wwBi2c1i2c1-xfer ww%i2c2i2c2-xfer  w wGi2c3i2c3-xfer ww&i2c4i2c4-xfer ww'i2c5i2c5-xfer ww(i2s0i2s0-bus`wwwwww]lcdclcdc-ctl@wwwwksdmmcsdmmc-clkw sdmmc-cmdysdmmc-cdysdmmc-bus1ysdmmc-bus4@yyyysdio0sdio0-bus1ysdio0-bus4@yyyysdio0-cmdysdio0-clkwsdio0-cdysdio0-wpysdio0-pwrysdio0-bkpwrysdio0-intysdio1sdio1-bus1ysdio1-bus4@yyyysdio1-cdysdio1-wpysdio1-bkpwrysdio1-intysdio1-cmdysdio1-clkwsdio1-pwr yemmcemmc-clkwemmc-cmdyemmc-pwr yemmc-bus1yemmc-bus4@yyyyemmc-bus8yyyyyyyyspi0spi0-clk yspi0-cs0 yspi0-txyspi0-rxyspi0-cs1yspi1spi1-clk yspi1-cs0 y spi1-rxyspi1-txyspi2spi2-cs1yspi2-clky!spi2-cs0y$spi2-rxy#spi2-tx y"uart0uart0-xfer yw)uart0-ctsyuart0-rtswuart1uart1-xfer y w*uart1-cts yuart1-rts wuart2uart2-xfer yw+uart3uart3-xfer yw,uart3-cts yuart3-rts wuart4uart4-xfer yw-uart4-cts yuart4-rts wtsadcotp-pin w3otp-out w4pwm0pwm0-pinwHpwm1pwm1-pinwIpwm2pwm2-pinwJpwm3pwm3-pinwKgmacrgmii-pinswwww{{{{www {{ww7rmii-pinswwwwwwwwwwphy-int y:phy-pmeby9phy-rst|8spdifspdif-tx w\pcfg-output-high |pmicpmic-intyDusb_hostphy-pwr-en |?usb2-pwr-en wusb_otgotg-vbus-drv wchosen /serial@ff690000memory/#memorydc12-vbatregulator-fixed dc12_vbat 8Pd}vboot-3v3regulator-fixed vboot_3v3 2Z82ZPd +}vsys-regulatorregulator-fixedvcc_sys 8u 88u Pd +}Fvboot-5vregulator-fixed vboot_sv LK@8LK@Pd +}v3g-3v3regulator-fixedv3g_3v3 2Z82ZPd +}vsus-5vregulator-fixedvsus_5v LK@8LK@Pd +vcc50-hdmiregulator-fixed vcc50_hdmi 6 ~ defaultPd +vusb1-5vregulator-fixed vusb1_5v 6 C default LK@8LK@ +Avusb2-5vregulator-fixed vusb2_5v 6  default LK@8LK@Pd +external-gmac-clock fixed-clocksY@ ext_gmac6 #address-cells#size-cellscompatibleinterrupt-parentmodelethernet0gpio0gpio1gpio2gpio3gpio4gpio5gpio6gpio7gpio8i2c0i2c1i2c2i2c3i2c4i2c5mshc0mshc1mshc2mshc3serial0serial1serial2serial3serial4spi0spi1spi2interruptsinterrupt-affinityenable-methodrockchip,pmudevice_typeregresetsoperating-points-v2#cooling-cellsclock-latencyclocksdynamic-power-coefficientcpu-supplyphandleopp-sharedopp-hzopp-microvoltrangesclock-frequencyclock-output-names#clock-cellsarm,cpu-registers-not-fw-configuredarm,no-tick-in-suspendclock-namesportsmax-frequencyfifo-depthreset-namesstatusbus-widthcap-mmc-highspeedcap-sd-highspeedcard-detect-delaydisable-wppinctrl-namespinctrl-0vmmc-supplyvqmmc-supplynon-removable#io-channel-cellsdmasdma-namesreg-shiftreg-io-width#dma-cellsarm,pl330-broken-no-flushparm,pl330-periph-burstpolling-delay-passivepolling-delaythermal-sensorstemperaturehysteresistripcooling-devicepinctrl-1pinctrl-2#thermal-sensor-cellsrockchip,grfrockchip,hw-tshut-temprockchip,hw-tshut-moderockchip,hw-tshut-polarityinterrupt-namesassigned-clocksassigned-clock-parentsclock_in_outphy-supplyphy-modesnps,reset-active-lowsnps,reset-delays-ussnps,reset-gpiotx_delayrx_delayphysphy-namesdr_modesnps,reset-phy-on-wakeg-np-tx-fifo-sizeg-rx-fifo-sizeg-tx-fifo-sizevbus-supplyrockchip,system-power-controllerwakeup-sourcevcc1-supplyvcc2-supplyvcc3-supplyvcc4-supplyvcc6-supplyvcc7-supplyvcc8-supplyvcc9-supplyvcc10-supplyvcc11-supplyvcc12-supplyregulator-nameregulator-min-microvoltregulator-max-microvoltregulator-always-onregulator-boot-onregulator-off-in-suspendregulator-on-in-suspendregulator-suspend-microvolt#pwm-cells#power-domain-cellspm_qosoffsetmode-normalmode-recoverymode-bootloadermode-loader#reset-cellsassigned-clock-rates#phy-cellsaudio-supplybb-supplydvp-supplyflash0-supplyflash1-supplygpio30-supplygpio1830-supplylcdc-supplysdcard-supplywifi-supply#sound-dai-cellsrockchip,playback-channelsrockchip,capture-channels#iommu-cellsrockchip,disable-mmu-resetpower-domainsiommusremote-endpointddc-i2c-busmali-supplyinterrupt-controller#interrupt-cellsgpio-controller#gpio-cellsrockchip,pinsoutput-lowbias-pull-upbias-pull-downbias-disabledrive-strengthoutput-highstdout-pathvin-supplyenable-active-high