u8q0(hp ,Freescale i.MX8QM MEK2fsl,imx8qm-mekfsl,imx8qmaliases=/bus@5b000000/mmc@5b010000B/bus@5b000000/mmc@5b020000G/bus@5b000000/mmc@5b030000L/bus@5a000000/serial@5a060000T/bus@5a000000/serial@5a070000\/bus@5a000000/serial@5a080000d/bus@5a000000/serial@5a090000 l/vpu@2c000000/vpu-core@2d080000 v/vpu@2c000000/vpu-core@2d090000 /vpu@2c000000/vpu-core@2d0a0000cpus cpu@0cpu2arm,cortex-a53psci@@cpu@1cpu2arm,cortex-a53psci@@cpu@2cpu2arm,cortex-a53psci@@cpu@3cpu2arm,cortex-a53psci@@l2-cache02cache@+l2-cache12cache@interrupt-controller@51a00000 2arm,gic-v3PQQ R RR3D Y +pmu2arm,armv8-pmuv3 Ypsci 2arm,psci-1.0smctimer2arm,armv8-timer0Y   system-controller 2fsl,imx-scu dtx0rx0gip3$opower-controller2fsl,imx8qm-scu-pdfsl,scu-pdv+clock-controller2fsl,imx8qm-clkfsl,scu-clk+ pinctrl2fsl,imx8qm-iomuxc+6fec1grp              +*lpuart0grp  +usdhc1grpA!!!!!!!!!A+#usdhc2grpTA!!!!!!+%rtc2fsl,imx8qxp-sc-rtcvpu@2c000000 ,,, disabledmailbox@2d0000002fsl,imx6sx-mu- Y disabled+mailbox@2d0200002fsl,imx6sx-mu- Y disabled+mailbox@2d0400002fsl,imx6sx-mu- Y disabled+vpu-core@2d080000-2nxp,imx8q-vpu-decoder dtx0tx1rx$o disabledvpu-core@2d090000- 2nxp,imx8q-vpu-encoder dtx0tx1rx$o disabledvpu-core@2d0a0000- 2nxp,imx8q-vpu-encoder dtx0tx1rx$o disabledbus@58000000 2simple-bus XXclock-img-ipg 2fixed-clock  img_ipg_clk+ jpegdec@58400000X@0Y5678peripg (%2nxp,imx8qm-jpgdecnxp,imx8qxp-jpgdecjpegenc@58450000XE0Y1234 peripg  (%2nxp,imx8qm-jpgencnxp,imx8qxp-jpgencclock-controller@585d00002fsl,imx8qxp-lpcgX] #0img_jpeg_dec_lpcg_clkimg_jpeg_dec_lpcg_ipg_clk+clock-controller@585f00002fsl,imx8qxp-lpcgX_ #0img_jpeg_enc_lpcg_clkimg_jpeg_enc_lpcg_ipg_clk+ bus@5a000000 2simple-bus ZZclock-dma-ipg 2fixed-clock' dma_ipg_clk+spi@5a0000002fsl,imx7ulp-spiZ  YP peripg  55 disabledspi@5a0100002fsl,imx7ulp-spiZ  YQ peripg  66 disabledspi@5a0200002fsl,imx7ulp-spiZ  YRperipg  77 disabledspi@5a0300002fsl,imx7ulp-spiZ  YSperipg  88 disabledserial@5a060000Z Y ipgbaud  9Ĵ9okay%2fsl,imx8qm-lpuartfsl,imx8qxp-lpuart1default?serial@5a070000Z Y ipgbaud  :Ĵ: disabled%2fsl,imx8qm-lpuartfsl,imx8qxp-lpuartserial@5a080000Z Y ipgbaud  ;Ĵ; disabled%2fsl,imx8qm-lpuartfsl,imx8qxp-lpuartserial@5a090000Z  Y ipgbaud  <Ĵ< disabled%2fsl,imx8qm-lpuartfsl,imx8qxp-lpuartclock-controller@5a4000002fsl,imx8qxp-lpcgZ@ 5# spi0_lpcg_clkspi0_lpcg_ipg_clk5+ clock-controller@5a4100002fsl,imx8qxp-lpcgZA 6# spi1_lpcg_clkspi1_lpcg_ipg_clk6+ clock-controller@5a4200002fsl,imx8qxp-lpcgZB 7# spi2_lpcg_clkspi2_lpcg_ipg_clk7+clock-controller@5a4300002fsl,imx8qxp-lpcgZC 8# spi3_lpcg_clkspi3_lpcg_ipg_clk8+clock-controller@5a4600002fsl,imx8qxp-lpcgZF 9#'uart0_lpcg_baud_clkuart0_lpcg_ipg_clk9+clock-controller@5a4700002fsl,imx8qxp-lpcgZG :#'uart1_lpcg_baud_clkuart1_lpcg_ipg_clk:+clock-controller@5a4800002fsl,imx8qxp-lpcgZH ;#'uart2_lpcg_baud_clkuart2_lpcg_ipg_clk;+clock-controller@5a4900002fsl,imx8qxp-lpcgZI <#'uart3_lpcg_baud_clkuart3_lpcg_ipg_clk<+i2c@5a800000Z@ Yperipg  `n6` disabled#2fsl,imx8qm-lpi2cfsl,imx7ulp-lpi2ci2c@5a810000Z@ Yperipg  an6a disabled#2fsl,imx8qm-lpi2cfsl,imx7ulp-lpi2ci2c@5a820000Z@ Yperipg  bn6b disabled#2fsl,imx8qm-lpi2cfsl,imx7ulp-lpi2ci2c@5a830000Z@ Yperipg  cn6c disabled#2fsl,imx8qm-lpi2cfsl,imx7ulp-lpi2cadc@5a8800002nxp,imx8qxp-adcIZ Yperipg  en6e disabledadc@5a8900002nxp,imx8qxp-adcIZ Yperipg  fn6f disabledcan@5a8d00002fsl,imx8qm-flexcanZ Yipgper  ibZi[j disabledcan@5a8e00002fsl,imx8qm-flexcanZ Yipgper  jbZj[j disabledcan@5a8f00002fsl,imx8qm-flexcanZ Yipgper  kbZk[j disabledclock-controller@5ac000002fsl,imx8qxp-lpcgZ `# i2c0_lpcg_clki2c0_lpcg_ipg_clk`+clock-controller@5ac100002fsl,imx8qxp-lpcgZ a# i2c1_lpcg_clki2c1_lpcg_ipg_clka+clock-controller@5ac200002fsl,imx8qxp-lpcgZ b# i2c2_lpcg_clki2c2_lpcg_ipg_clkb+clock-controller@5ac300002fsl,imx8qxp-lpcgZ c# i2c3_lpcg_clki2c3_lpcg_ipg_clkc+clock-controller@5ac800002fsl,imx8qxp-lpcgZ e# adc0_lpcg_clkadc0_lpcg_ipg_clke+clock-controller@5ac900002fsl,imx8qxp-lpcgZ f# adc1_lpcg_clkadc1_lpcg_ipg_clkf+clock-controller@5acd00002fsl,imx8qxp-lpcgZ i #5can0_lpcg_pe_clkcan0_lpcg_ipg_clkcan0_lpcg_chi_clki+clock-controller@5a4a00002fsl,imx8qxp-lpcgZJ =#'uart4_lpcg_baud_clkuart4_lpcg_ipg_clk=clock-controller@5ace00002fsl,imx8qxp-lpcgZ j #5can1_lpcg_pe_clkcan1_lpcg_ipg_clkcan1_lpcg_chi_clkj+clock-controller@5acf00002fsl,imx8qxp-lpcgZ k #5can2_lpcg_pe_clkcan2_lpcg_ipg_clkcan2_lpcg_chi_clkk+bus@5b000000 2simple-bus [[clock-conn-axi 2fixed-clockCU conn_axi_clk+0clock-conn-ahb 2fixed-clock ! conn_ahb_clk+1clock-conn-ipg 2fixed-clock conn_ipg_clk+/usb@5b0d0000-2fsl,imx7ulp-usbfsl,imx6ul-usbfsl,imx27-usb[  Y x ! disabledusbmisc@5b0d020082fsl,imx7ulp-usbmiscfsl,imx7d-usbmiscfsl,imx6q-usbmisc[ + usbphy@5b1000002fsl,imx7ulp-usbphy[! disabled+mmc@5b010000 Y[""" ipgahbperokay32fsl,imx8qm-usdhcfsl,imx8qxp-usdhcfsl,imx7d-usdhc1default?#mmc@5b020000 Y[$$$ ipgahbperokay32fsl,imx8qm-usdhcfsl,imx8qxp-usdhcfsl,imx7d-usdhc1default?% & ,' 5'mmc@5b030000 Y[((( ipgahbper disabled32fsl,imx8qm-usdhcfsl,imx8qxp-usdhcfsl,imx7d-usdhcethernet@5b040000[0Y ))) )ipgahbenet_clk_refptp  沀sY@>Pokay2fsl,imx8qm-fecfsl,imx6sx-fec1default?* brgmii-idk+vmdio ethernet-phy@02ethernet-phy-ieee802.3-c22++ethernet-phy@12ethernet-phy-ieee802.3-c22ethernet@5b050000[0Y ,,, ,ipgahbenet_clk_refptp  沀sY@>P disabled2fsl,imx8qm-fecfsl,imx6sx-fecusb@5b1100002fsl,imx8qm-usb3[ (-----lpmbusaclkipgcore  沀 disabledusb@5b120000 2cdns,usb3[[[ xhcidevotg 0Yhostperipheralotgwakeup.cdns3,usb3-phy disabledusb-phy@5b1600002nxp,salvo-phy[-salvo_phy_clk disabled+.clock-controller@5b2000002fsl,imx8qxp-lpcg[  /0 #9sdhc0_lpcg_per_clksdhc0_lpcg_ipg_clksdhc0_lpcg_ahb_clk+"clock-controller@5b2100002fsl,imx8qxp-lpcg[! /0 #9sdhc1_lpcg_per_clksdhc1_lpcg_ipg_clksdhc1_lpcg_ahb_clk+$clock-controller@5b2200002fsl,imx8qxp-lpcg[" /0 #9sdhc2_lpcg_per_clksdhc2_lpcg_ipg_clksdhc2_lpcg_ahb_clk+(clock-controller@5b2300002fsl,imx8qxp-lpcg[#0  0 //# enet0_lpcg_timer_clkenet0_lpcg_txc_sampling_clkenet0_lpcg_ahb_clkenet0_lpcg_rgmii_txc_clkenet0_lpcg_ipg_clkenet0_lpcg_ipg_s_clk+)clock-controller@5b2400002fsl,imx8qxp-lpcg[$0  0 //# enet1_lpcg_timer_clkenet1_lpcg_txc_sampling_clkenet1_lpcg_ahb_clkenet1_lpcg_rgmii_txc_clkenet1_lpcg_ipg_clkenet1_lpcg_ipg_s_clk+,clock-controller@5b2700002fsl,imx8qxp-lpcg['1/#"usboh3_ahb_clkusboh3_phy_ipg_clk+!clock-controller@5b2800002fsl,imx8qxp-lpcg[(#0  /// Musb3_app_clkusb3_lpm_clkusb3_ipg_clkusb3_core_pclkusb3_phy_clkusb3_aclk+-bus@5d000000 2simple-bus  ]]clock-lsio-mem 2fixed-clock  lsio_mem_clkclock-lsio-bus 2fixed-clock lsio_bus_clk+7pwm@5d0000002fsl,imx27-pwm]ipgper22  n6 disabledpwm@5d0100002fsl,imx27-pwm]ipgper33  n6 disabledpwm@5d0200002fsl,imx27-pwm]ipgper44  n6 disabledpwm@5d0300002fsl,imx27-pwm]ipgper55  n6 disabledgpio@5d080000] YD32fsl,imx8qm-gpiofsl,imx35-gpio0666$gpio@5d090000]  YD32fsl,imx8qm-gpiofsl,imx35-gpio@6(62 6?6Hgpio@5d0a0000]  YD32fsl,imx8qm-gpiofsl,imx35-gpio06P6U6h gpio@5d0b0000]  YD32fsl,imx8qm-gpiofsl,imx35-gpio6r6u6666666666gpio@5d0c0000]  YD32fsl,imx8qm-gpiofsl,imx35-gpio`6666 66+8gpio@5d0d0000]  YD32fsl,imx8qm-gpiofsl,imx35-gpio666 66666+'gpio@5d0e0000] YD32fsl,imx8qm-gpiofsl,imx35-gpio 6 6  gpio@5d0f0000] YD32fsl,imx8qm-gpiofsl,imx35-gpiospi@5d120000 2nxp,imx8qxp-fspi]fspi_basefspi_mmap Y\   fspi_enfspi disabledmailbox@5d1b0000] Y disabled,2fsl,imx8-mu-scufsl,imx8qm-mufsl,imx6sx-mumailbox@5d1c0000] Y,2fsl,imx8-mu-scufsl,imx8qm-mufsl,imx6sx-mu+mailbox@5d1d0000] Y disabled,2fsl,imx8-mu-scufsl,imx8qm-mufsl,imx6sx-mumailbox@5d1e0000] Y disabled,2fsl,imx8-mu-scufsl,imx8qm-mufsl,imx6sx-mumailbox@5d1f0000] Y disabled,2fsl,imx8-mu-scufsl,imx8qm-mufsl,imx6sx-mumailbox@5d200000]  Y disabled2fsl,imx8qm-mufsl,imx6sx-mumailbox@5d210000]! Y disabled2fsl,imx8qm-mufsl,imx6sx-mumailbox@5d280000]( Y2fsl,imx8qm-mufsl,imx6sx-muclock-controller@5d4000002fsl,imx8qxp-lpcg]@4   7 #hpwm0_lpcg_ipg_clkpwm0_lpcg_ipg_hf_clkpwm0_lpcg_ipg_s_clkpwm0_lpcg_ipg_slv_clkpwm0_lpcg_ipg_mstr_clk+2clock-controller@5d4100002fsl,imx8qxp-lpcg]A4   7 #hpwm1_lpcg_ipg_clkpwm1_lpcg_ipg_hf_clkpwm1_lpcg_ipg_s_clkpwm1_lpcg_ipg_slv_clkpwm1_lpcg_ipg_mstr_clk+3clock-controller@5d4200002fsl,imx8qxp-lpcg]B4   7 #hpwm2_lpcg_ipg_clkpwm2_lpcg_ipg_hf_clkpwm2_lpcg_ipg_s_clkpwm2_lpcg_ipg_slv_clkpwm2_lpcg_ipg_mstr_clk+4clock-controller@5d4300002fsl,imx8qxp-lpcg]C4   7 #hpwm3_lpcg_ipg_clkpwm3_lpcg_ipg_hf_clkpwm3_lpcg_ipg_s_clkpwm3_lpcg_ipg_slv_clkpwm3_lpcg_ipg_mstr_clk+5clock-controller@5d4400002fsl,imx8qxp-lpcg]D4   7 #hpwm4_lpcg_ipg_clkpwm4_lpcg_ipg_hf_clkpwm4_lpcg_ipg_s_clkpwm4_lpcg_ipg_slv_clkpwm4_lpcg_ipg_mstr_clkclock-controller@5d4500002fsl,imx8qxp-lpcg]E4   7 #hpwm5_lpcg_ipg_clkpwm5_lpcg_ipg_hf_clkpwm5_lpcg_ipg_s_clkpwm5_lpcg_ipg_slv_clkpwm5_lpcg_ipg_mstr_clkclock-controller@5d4600002fsl,imx8qxp-lpcg]F4   7 #hpwm6_lpcg_ipg_clkpwm6_lpcg_ipg_hf_clkpwm6_lpcg_ipg_s_clkpwm6_lpcg_ipg_slv_clkpwm6_lpcg_ipg_mstr_clkclock-controller@5d4700002fsl,imx8qxp-lpcg]G4   7 #hpwm7_lpcg_ipg_clkpwm7_lpcg_ipg_hf_clkpwm7_lpcg_ipg_s_clkpwm7_lpcg_ipg_slv_clkpwm7_lpcg_ipg_mstr_clkchosen/bus@5a000000/serial@5a060000memory@80000000memory@usdhc2-vmmc2regulator-fixed SD1_SPWR -8- P8U+& interrupt-parent#address-cells#size-cellsmodelcompatiblemmc0mmc1mmc2serial0serial1serial2serial3vpu_core0vpu_core1vpu_core2device_typeregenable-methodi-cache-sizei-cache-line-sizei-cache-setsd-cache-sized-cache-line-sized-cache-setsnext-level-cachecache-levelcache-unifiedphandle#interrupt-cellsinterrupt-controllerinterruptsmbox-namesmboxes#power-domain-cells#clock-cellsfsl,pinsrangespower-domainsstatus#mbox-cellsclock-frequencyclock-output-namesclocksclock-namesassigned-clocksassigned-clock-ratesclock-indicespinctrl-namespinctrl-0#io-channel-cellsfsl,clk-sourcefsl,scu-indexfsl,usbphyfsl,usbmiscahb-burst-configtx-burst-size-dwordrx-burst-size-dword#index-cellsbus-widthno-sdno-sdionon-removablefsl,tuning-start-tapfsl,tuning-stepvmmc-supplycd-gpioswp-gpiosfsl,num-tx-queuesfsl,num-rx-queuesphy-modephy-handlefsl,magic-packetreg-namesinterrupt-namesphysphy-namescdns,on-chip-buff-size#phy-cells#pwm-cellsgpio-controller#gpio-cellsgpio-rangesstdout-pathregulator-nameregulator-min-microvoltregulator-max-microvoltgpioenable-active-high