Ð þí J8t(Ö< +,Qualcomm Technologies, Inc. IPQ5332 MI01.6$2qcom,ipq5332-ap-mi01.6qcom,ipq5332clockssleep-clk 2fixed-clock=J}Z xo-board-clk 2fixed-clock=Jn6Z cpus cpu@0bcpu2arm,cortex-a53nrpsci€‘˜cpu@1bcpu2arm,cortex-a53nrpsci€‘˜cpu@2bcpu2arm,cortex-a53nrpsci€‘˜cpu@3bcpu2arm,cortex-a53nrpsci€‘˜l2-cache2cache¬¸Zfirmwarescm2qcom,scm-ipq5332qcom,scmÆamemory@40000000bmemoryn@opp-table-cpu2operating-points-v2ÖZopp-1488000000áX±è @pmu2arm,cortex-a53-pmu ùpsci 2arm,psci-1.0ysmcreserved-memory bootloader@4a100000nJ@ sbl@4a500000nJP tz@4a600000nJ`  smem@4a800000 2qcom,smemnJ€ soc@0 2simple-bus ÿÿÿÿefuse@a4000 2qcom,ipq5332-qfpromqcom,qfpromn @! rng@e3000 2qcom,prng-een0‘Ycorepinctrl@10000002qcom,ipq5332-tlmmn0 ùù&6B5NcZserial0-statetgpio18gpio19 yblsp0_uart0‚‘Z sdc-default-stateZ clk-pinstgpio13ysdc_clk‚žcmd-pinstgpio12ysdc_cmd‚‘data-pinstgpio8gpio9gpio10gpio11 ysdc_data‚‘spi-0-data-clk-statetgpio14gpio15gpio16 yblsp0_spi‚«Zspi-0-cs-statetgpio17 yblsp0_spi‚‘Zclock-controller@18000002qcom,ipq5332-gccn€=ºÇ‘ Zhwlock@19050002qcom,tcsr-mutexnPÛZsyscon@19370002qcom,tcsr-ipq5332sysconn“pZmmc@7804000%2qcom,ipq5332-sdhciqcom,sdhci-msm-v5n€@€Pù9<éhc_irqpwr_irq‘qr ifacecorexoùokay q°%4B Ldefaultdma-controller@78840002qcom,bam-v1.7.0nˆ@Ð ù!‘ bam_clkZeZ serial@78af000%2qcom,msm-uartdm-v1.4qcom,msm-uartdmnŠð ù"‘  coreifaceùokayB Ldefaultserial@78b0000%2qcom,msm-uartdm-v1.4qcom,msm-uartdmn‹ ù#‘  coreifacem  rtxrx ùdisabledspi@78b50002qcom,spi-qup-v2.2.1n‹P  ù$‘   coreifacem  rtxrxùokayBLdefaultflash@0 2micron,n25q128a11jedec,spi-norn |úð€i2c@78b60002qcom,i2c-qup-v2.2.1n‹`  ù%‘  coreifacem  rtxrx ùdisabledspi@78b70002qcom,spi-qup-v2.2.1n‹p  ù&‘  coreifacem  rtxrx ùdisabledinterrupt-controller@b0000002qcom,msm-qgic2 n    @ ù Nc   À0Zv2m@02arm,gic-v2m-framenýŽv2m@10002arm,gic-v2m-framenýŽv2m@20002arm,gic-v2m-framen ýŽwatchdog@b017000$2qcom,apss-wdt-ipq5332qcom,kpss-wdtn p ù‘ mailbox@b111000<2qcom,ipq5332-apcs-apps-globalqcom,ipq6018-apcs-apps-globaln =‘ pllxo©Zclock@b1160002qcom,ipq5332-a53plln `@=‘ xoZtimer@b1200002arm,armv7-timer-memn  frame@b120000n   ùµframe@b123000n 0 ù µ ùdisabledframe@b124000n @ ù µ ùdisabledframe@b125000n P ù µ ùdisabledframe@b126000n ` ù µ ùdisabledframe@b127000n p ù µ ùdisabledframe@b128000n € ùµ ùdisabledtimer2arm,armv8-timer0ùaliasesÂ/soc@0/serial@78af000chosenÊserial0 interrupt-parent#address-cells#size-cellsmodelcompatible#clock-cellsclock-frequencyphandledevice_typeregenable-methodnext-level-cacheclocksoperating-points-v2cache-levelcache-unifiedqcom,dload-modeopp-sharedopp-hzclock-latency-nsinterruptsrangesno-maphwlocksclock-namesgpio-controller#gpio-cellsgpio-rangesinterrupt-controller#interrupt-cellspinsfunctiondrive-strengthbias-pull-upbias-disablebias-pull-down#reset-cells#power-domain-cells#hwlock-cellsinterrupt-namesstatusbus-widthmax-frequencymmc-ddr-1_8vmmc-hs200-1_8vnon-removablepinctrl-0pinctrl-names#dma-cellsqcom,eedmasdma-namesspi-max-frequencymsi-controllertimeout-sec#mbox-cellsframe-numberserial0stdout-path