8( ,OnePlus Nord N1002oneplus,billie2qcom,sm4250=I chosen W ^framebuffer0framebuffer@9d4000002simple-framebufferj\FPnt@{ @ a8r8g8b8clocksxo-board 2fixed-clock$ sleep-clk 2fixed-clock$cpus cpu@0cpu 2qcom,kryo240jdpsci ,psci l2-cache2cache?Kcpu@1cpu 2qcom,kryo240jdpsci ,pscicpu@2cpu 2qcom,kryo240jdpsci ,pscicpu@3cpu 2qcom,kryo240jdpsci ,pscicpu@100cpu 2qcom,kryo240jpscif  ,pscil2-cache2cache?Kcpu@101cpu 2qcom,kryo240jfpsci  ,pscicpu@102cpu 2qcom,kryo240jfpsci  ,pscicpu@103cpu 2qcom,kryo240jfpsci  ,pscicpu-mapcluster0core0Y core1Ycore2Ycore3Ycluster1core0Ycore1Ycore2Ycore3Yidle-states]pscicpu-sleep-0-02arm,idle-statejsilver-rail-power-collapsez@"xcpu-sleep-1-02arm,idle-statejgold-rail-power-collapsez@)DVdomain-idle-statescluster-sleep-0-02domain-idle-statez@"hcluster-sleep-0-12domain-idle-statezAD Fcluster-sleep-1-02domain-idle-statez@B:Ycluster-sleep-1-12domain-idle-statezADvfirmwarescm2qcom,scm-sm6115qcom,scmmemory@80000000memoryjpmu2arm,armv8-pmuv3 psci 2arm,psci-1.0smcpower-domain-cpu0power-domain-cpu1power-domain-cpu2power-domain-cpu3power-domain-cpu4 power-domain-cpu5 power-domain-cpu6 power-domain-cpu7 power-domain-cpu-cluster0power-domain-cpu-cluster1reserved-memory Wmemory@45700000jEp`memory@45e00000jEmemory@45fff000jEmemory@46000000 2qcom,smemjF "memory@46200000jF memory@4ab00000jJTmemory@51400000jQ@Pmemory@51900000jQ|memory@51a00000jQzmemory@53800000jSwmemory@56100000jVmemory@56110000jVPmemory@56115000jVP memory@5c000000j\memory@5cf00000j\memory@60000000j`memory@89b010002qcom,rmtfs-memj 3B+memory@5fff7000j_pramoops@cbe000002ramoopsj@LX bomemory@cc200000j memory@cc300000j0rpm-glink2qcom,glink-rpm "{rpm-requests2qcom,rpm-sm6115 rpm_requestsclock-controller2qcom,rpmcc-sm6115qcom,rpmcc xo#power-controller2qcom,sm6115-rpmpd!,opp-table2operating-points-v2!opp10Mopp2@3opp3Nopp4Oopp54opp6@opp7opp8regulators-02qcom,rpm-pm6125-regulatorss67s7 s8<@l1l4r@B@'l5%./l6 l7Ol8 l9w@l10@ l11@7l12F(l13l14@ l15,@1Q)l16@ l17l18؀9l192j@l202j@l21$6l22- @2j@.l232K2j@l24)B66smp2p-adsp 2qcom,smp2p {  master-kernelmaster-kernel)xslave-kernel slave-kernel@Uvsmp2p-cdsp 2qcom,smp2p^ { master-kernelmaster-kernel){slave-kernel slave-kernel@Uysmp2p-mpss 2qcom,smp2p F{ master-kernelmaster-kernel)Uslave-kernel slave-kernel@USsoc@0 2simple-bus Wfhwlock@3400002qcom,tcsr-mutexj4qpinctrl@5000002qcom,sm6115-tlmm0jP@@@westsoutheast "r@U"qup-i2c0-default-state gpio0gpio1qup0:qup-i2c1-default-state gpio4gpio5qup1=qup-i2c2-default-state gpio6gpio7qup2?qup-i2c3-default-state gpio8gpio9qup3Aqup-i2c4-default-stategpio12gpio13qup4Cqup-i2c5-default-stategpio14gpio15qup5Equp-spi0-default-stategpio0gpio1gpio2gpio3qup0<qup-spi1-default-stategpio4gpio5gpio69gpio70qup1>qup-spi2-default-stategpio6gpio7gpio71gpio80qup2@qup-spi3-default-stategpio8gpio9gpio10gpio11qup3Bqup-spi4-default-stategpio12gpio13gpio96gpio97qup4Dqup-spi5-default-stategpio14gpio15gpio16gpio17qup5Fsdc1-on-stateclk-pins sdc1_clkcmd-pins sdc1_cmd data-pins sdc1_data rclk-pins sdc1_rclksdc1-off-stateclk-pins sdc1_clkcmd-pins sdc1_cmddata-pins sdc1_datarclk-pins sdc1_rclksdc2-on-state0clk-pins sdc2_clkcmd-pins sdc2_cmd data-pins sdc2_data sdc2-off-state2clk-pins sdc2_clkcmd-pins sdc2_cmddata-pins sdc2_datasd-card-det-n-stategpio88gpio1clock-controller@14000002qcom,gcc-sm6115j@ #$bi_tcxosleep_clk%phy@16130002qcom,sm6115-qusb2-phyja0 %# cfg_ahbref%&*okay1'<(L)Gdma-controller@1b04000 2qcom,bam-v1.7.4qcom,bam-v1.7.0j@@ #Fbam_clkalt<*****+crypto@1b3a000*2qcom,sm6115-qceqcom,ipq4019-qceqcom,qcej`#Fcore++rxtx<*****phy@16150002qcom,sm6115-qmp-usb3-phyjaP %%%%cfg_ahbrefcom_auxpipe% %  phyphy_phyusb3_phy_pipe_clk_src  *disabledqfprom@1b400002qcom,sm6115-qfpromqcom,qfpromjp hstx-trim@25bj[&rng@1b53000 2qcom,prng-eej0%Tcorespmi@1c400002qcom,spmi-pmic-arbPj `corechnlsobsrvrintrcnfg periph_irq l @Uthermal-sensor@4411000 2qcom,sm6115-tsensqcom,tsens-v2 jAAuplowcritical}sram@45f00002qcom,rpm-msg-ramj_psram@46900002qcom,rpm-statsjimmc@4744000$2qcom,sm6115-sdhciqcom,sdhci-msm-v50jt@tPt hccqhciice\`hc_irqpwr_irq %j%k#%mifacecorexoice *disabledmmc@4784000$2qcom,sm6115-sdhciqcom,sdhci-msm-v5jx@hc^ahc_irqpwr_irq%o%p#ifacecorexo,- *% d,"h*okay2.>/ K"XTdefaultsleepb01l21opp-table2operating-points-v2-opp-100000000v}3opp-202000000v F}4ufs@4804000+2qcom,sm6115-ufshcqcom,ufshcjedec,ufs-2.0 j@0stdice d5ufsphy%rst% *@%v%s%u%~#%}%|%xicore_clkbus_aggr_clkiface_clkcore_clk_uniproref_clktx_lane0_sync_clkrx_lane0_sync_clkice_core_clk@ <4`рxh*okay6 '7 '8phy@48070002qcom,sm6115-qmp-ufs-phyjp W%%z refref_aux8ufsphy*okay'<(9phy@48074000jtv0|l 5dma-controller@4a00000(2qcom,sm6115-gpi-dmaqcom,sm6350-gpi-dmajxOPQRSTUVWX ) *a *disabled;geniqup@4ac00002qcom,geni-se-qupj  m-ahbs-ahb%h%i  *W *disabledi2c@4a800002qcom,geni-i2cj@se%\Tdefaultb: G ;;txrx  *disabledspi@4a800002qcom,geni-spij@se%\Tdefaultb< G ;;txrx  *disabledi2c@4a840002qcom,geni-i2cj@@se%^Tdefaultb= H ;;txrx  *disabledspi@4a840002qcom,geni-spij@@se%^Tdefaultb> H ;;txrx  *disabledi2c@4a880002qcom,geni-i2cj@se%`Tdefaultb? I ;;txrx  *disabledspi@4a880002qcom,geni-spij@se%`Tdefaultb@ I ;;txrx  *disabledi2c@4a8c0002qcom,geni-i2cj@se%bTdefaultbA J ;;txrx  *disabledspi@4a8c0002qcom,geni-spij@se%bTdefaultbB J ;;txrx  *disabledi2c@4a900002qcom,geni-i2cj@se%dTdefaultbC K ;;txrx  *disabledspi@4a900002qcom,geni-spij@se%dTdefaultbD K ;;txrx  *disabledserial@4a900002qcom,geni-debug-uartj@se%d K *disabledi2c@4a940002qcom,geni-i2cj@@se%fTdefaultbE L ;;txrx  *disabledspi@4a940002qcom,geni-spij@@se%fTdefaultbF L ;;txrx  *disabledusb@4ef88002qcom,sm6115-dwc3qcom,dwc3j W0%8%%t%%%&cfg_noccoreifacesleepmock_utmixo:%%J$@hs_phy_irqss_phy_irq%%_*okayusb@4e00000 2snps,dwc3j G usb2-phy * | high-speed peripheralclock-controller@59900002qcom,sm6115-gpuccj#%I%JHiommu@59a0000@2qcom,sm6115-smmu-500qcom,adreno-smmuqcom,smmu-500arm,mmu-500jl%LH%MmemhlosifaceHdisplay-subsystem@5e000002qcom,sm6115-mdssjmdssI%=%?I  @U* *! W *disabledKdisplay-controller@5e010002qcom,sm6115-dpu j  mdpvbif0%?II I IIbusifacecorelutrotvsyncJ,Kports port@0jendpoint"LRopp-table2operating-points-v2Jopp-19200000v$}Mopp-192000000v q}3opp-256000000vB@}Nopp-307200000vO}Oopp-384000000v`}4dsi@5e94000(2qcom,sm6115-dsi-ctrlqcom,mdss-dsi-ctrlj@ dsi_ctrlK0IIIII%?$bytebyte_intfpixelcoreifacebus:II2PPQ,P  *disabledports port@0jendpoint"RLport@1jendpointopp-table2operating-points-v2Qopp-19200000v$}Mopp-164000000v q}3opp-187500000v -}Nphy@5e944002qcom,dsi-phy-14nm-22900jDEHdsi_phydsi_phy_lanedsi_pll I# ifaceref *disabledPclock-controller@5f000002qcom,sm6115-dispccj$#$PP%>Iremoteproc@60800002qcom,sm6115-mpss-pasjLI3SSSSS0wdogfatalreadyhandoverstop-ackshutdown-ack#xo,]TkU|stop *disabledglink-edge Dmpss { stm@8002000 2arm,coresight-stmarm,primecell j (stm-basestm-stimulus-base# apb_pclk *disabledout-portsportendpoint"V]cti@8010000 2arm,coresight-ctiarm,primecellj# apb_pclk *disabledcti@8011000 2arm,coresight-ctiarm,primecellj# apb_pclk *disabledcti@8012000 2arm,coresight-ctiarm,primecellj # apb_pclk *disabledcti@8013000 2arm,coresight-ctiarm,primecellj0# apb_pclk *disabledcti@8014000 2arm,coresight-ctiarm,primecellj@# apb_pclk *disabledcti@8015000 2arm,coresight-ctiarm,primecelljP# apb_pclk *disabledcti@8016000 2arm,coresight-ctiarm,primecellj`# apb_pclk *disabledcti@8017000 2arm,coresight-ctiarm,primecelljp# apb_pclk *disabledcti@8018000 2arm,coresight-ctiarm,primecellj# apb_pclk *disabledcti@8019000 2arm,coresight-ctiarm,primecellj# apb_pclk *disabledcti@801a000 2arm,coresight-ctiarm,primecellj# apb_pclk *disabledcti@801b000 2arm,coresight-ctiarm,primecellj# apb_pclk *disabledcti@801c000 2arm,coresight-ctiarm,primecellj# apb_pclk *disabledcti@801d000 2arm,coresight-ctiarm,primecellj# apb_pclk *disabledcti@801e000 2arm,coresight-ctiarm,primecellj# apb_pclk *disabledcti@801f000 2arm,coresight-ctiarm,primecellj# apb_pclk *disabledreplicator@8046000/2arm,coresight-dynamic-replicatorarm,primecellj`# apb_pclk *disabledout-portsportendpoint"W[in-portsportendpoint"XZetf@8047000 2arm,coresight-tmcarm,primecelljp# apb_pclk *disabledin-portsportendpoint"Y`out-portsportendpoint"ZXetr@8048000 2arm,coresight-tmcarm,primecellj# apb_pclk *disabledin-portsportendpoint"[Wfunnel@8041000+2arm,coresight-dynamic-funnelarm,primecellj# apb_pclk *disabledout-portsportendpoint"\ain-portsportendpoint"]Vfunnel@8042000+2arm,coresight-dynamic-funnelarm,primecellj # apb_pclk *disabledout-portsportendpoint"^bin-portsportendpoint"_tfunnel@8045000+2arm,coresight-dynamic-funnelarm,primecelljP# apb_pclk *disabledout-portsportendpoint"`Yin-ports port@0jendpoint"a\port@1jendpoint"b^etm@9040000"2arm,coresight-etm4xarm,primecellj # apb_pclkY  *disabledout-portsportendpoint"cletm@9140000"2arm,coresight-etm4xarm,primecellj # apb_pclkY *disabledout-portsportendpoint"dmetm@9240000"2arm,coresight-etm4xarm,primecellj $# apb_pclkY *disabledout-portsportendpoint"enetm@9340000"2arm,coresight-etm4xarm,primecellj 4# apb_pclkY *disabledout-portsportendpoint"foetm@9440000"2arm,coresight-etm4xarm,primecellj D# apb_pclkY *disabledout-portsportendpoint"gpetm@9540000"2arm,coresight-etm4xarm,primecellj T# apb_pclkY *disabledout-portsportendpoint"hqetm@9640000"2arm,coresight-etm4xarm,primecellj d# apb_pclkY *disabledout-portsportendpoint"iretm@9740000"2arm,coresight-etm4xarm,primecellj t# apb_pclkY *disabledout-portsportendpoint"jsfunnel@9800000+2arm,coresight-dynamic-funnelarm,primecellj # apb_pclk *disabledout-portsportendpoint"kuin-ports port@0jendpoint"lcport@1jendpoint"mdport@2jendpoint"neport@3jendpoint"ofport@4jendpoint"pgport@5jendpoint"qhport@6jendpoint"riport@7jendpoint"sjfunnel@9810000+2arm,coresight-dynamic-funnelarm,primecellj # apb_pclk *disabledout-portsportendpoint"t_in-portsportendpoint"ukremoteproc@ab000002qcom,sm6115-adsp-pasj @Ivvvv#wdogfatalreadyhandoverstop-ack#xo,,]wkx|stop *disabledglink-edge lpass {fastrpc 2qcom,fastrpcfastrpcglink-apps-dspadsp compute-cb@32qcom,fastrpc-compute-cbj *compute-cb@42qcom,fastrpc-compute-cbj *compute-cb@52qcom,fastrpc-compute-cbj *compute-cb@62qcom,fastrpc-compute-cbj *compute-cb@72qcom,fastrpc-compute-cbj *remoteproc@b3000002qcom,sm6115-cdsp-pasj 0@I yyyy#wdogfatalreadyhandoverstop-ack#xo,]zk{|stop *disabledglink-edge cdsp {fastrpc 2qcom,fastrpcfastrpcglink-apps-dspcdsp compute-cb@12qcom,fastrpc-compute-cbj * compute-cb@22qcom,fastrpc-compute-cbj * compute-cb@32qcom,fastrpc-compute-cbj * compute-cb@42qcom,fastrpc-compute-cbj * compute-cb@52qcom,fastrpc-compute-cbj * compute-cb@62qcom,fastrpc-compute-cbj * iommu@c600000/2qcom,sm6115-smmu-500qcom,smmu-500arm,mmu-500j ` QXYZ[\]^_`abcdefghijklmnopqrstuvwxyz{|}~*wifi@c8000002qcom,wcn3990-wifij membase]|fghijklmnopq * *disabledwatchdog@f017000#2qcom,apss-wdt-sm6115qcom,kpss-wdtjp$ mailbox@f111000;2qcom,sm6115-apcs-hmss-globalqcom,msm8994-apcs-kpss-globaljtimer@f1200002arm,armv7-timer-memj W$frame@f121000 j frame@f123000j0   *disabledframe@f124000j@   *disabledframe@f125000jP   *disabledframe@f126000j`   *disabledframe@f127000jp   *disabledframe@f128000j  *disabledinterrupt-controller@f200000 2arm,gic-v3 j 0U@  cpufreq@f521000'2qcom,sm6115-cpufreq-hwqcom,cpufreq-hw jRR0freq-domain0freq-domain1#% xoalternate-thermal-zonesmapss-thermal@Vd}tripstrip-point0t8passivetrip-point1tHpassivecdsp-hvx-thermal@Vd}tripstrip-point0t8passivetrip-point1tHpassivewlan-thermal@Vd}tripstrip-point0t8passivetrip-point1tHpassivecamera-thermal@Vd}tripstrip-point0t8passivetrip-point1tHpassivevideo-thermal@Vd}tripstrip-point0t8passivetrip-point1tHpassivemodem1-thermal@Vd}tripstrip-point0t8passivetrip-point1tHpassivecpu4-thermal@Vd}tripstrip-point0t_passivetrip-point1tspassivecpu_critt criticalcpu5-thermal@Vd}tripstrip-point0t_passivetrip-point1tspassivecpu_critt criticalcpu6-thermal@Vd}tripstrip-point0t_passivetrip-point1tspassivecpu_critt criticalcpu7-thermal@Vd} tripstrip-point0t_passivetrip-point1tspassivecpu_critt criticalcpu45-thermal@Vd} tripstrip-point0t_passivetrip-point1tspassivecpu_critt criticalcpu67-thermal@Vd} tripstrip-point0t_passivetrip-point1tspassivecpu_critt criticalcpu0123-thermal@Vd} tripstrip-point0t_passivetrip-point1tspassivecpu_critt criticalmodem0-thermal@Vd} tripstrip-point0t8passivetrip-point1tHpassivedisplay-thermal@Vd}tripstrip-point0t8passivetrip-point1tHpassivegpu-thermal@Vd}tripstrip-point0t8passivetrip-point1tHpassivetimer2arm,armv8-timer0aliases interrupt-parent#address-cells#size-cellsmodelcompatibleqcom,msm-idqcom,board-idrangesstdout-pathregwidthheightstrideformat#clock-cellsclock-frequencyphandledevice_typeclockscapacity-dmips-mhzdynamic-power-coefficientenable-methodnext-level-cacheqcom,freq-domainpower-domainspower-domain-namescache-levelcache-unifiedcpuentry-methodidle-state-namearm,psci-suspend-paramentry-latency-usexit-latency-usmin-residency-uslocal-timer-stop#reset-cellsinterrupts#power-domain-cellsdomain-idle-statesno-maphwlocksqcom,rpm-msg-ramqcom,client-idqcom,vmidrecord-sizepmsg-sizeconsole-sizeftrace-sizemboxesqcom,glink-channelsclock-namesoperating-points-v2opp-levelregulator-min-microvoltregulator-max-microvoltqcom,smemqcom,local-pidqcom,remote-pidqcom,entry-name#qcom,smem-state-cellsinterrupt-controller#interrupt-cellsdma-ranges#hwlock-cellsreg-namesgpio-controllergpio-ranges#gpio-cellsgpio-reserved-rangespinsfunctiondrive-strengthbias-pull-upbias-disablebias-pull-down#phy-cellsresetsnvmem-cellsstatusvdd-supplyvdda-pll-supplyvdda-phy-dpdm-supply#dma-cellsqcom,eeqcom,controlled-remotelyiommusdmasdma-namesreset-namesclock-output-namesbitsinterrupt-namesqcom,channel#qcom,sensors#thermal-sensor-cellsbus-widthqcom,dll-configqcom,ddr-configvmmc-supplyvqmmc-supplycd-gpiospinctrl-namespinctrl-0pinctrl-1opp-hzrequired-oppsphysphy-nameslanes-per-directionfreq-table-hzvcc-supplyvcc-max-microampvccq2-supplyvccq2-max-microampvdda-phy-supplyvddp-ref-clk-supplydma-channelsdma-channel-maskassigned-clocksassigned-clock-ratesqcom,select-utmi-as-pipe-clksnps,dis_u2_susphy_quirksnps,dis_enblslpm_quirksnps,has-lpm-erratumsnps,hird-thresholdsnps,usb3_lpm_capablemaximum-speeddr_mode#global-interrupts#iommu-cellsremote-endpointassigned-clock-parentsinterrupts-extendedmemory-regionqcom,smem-statesqcom,smem-state-nameslabelarm,coresight-loses-context-with-cpuqcom,non-secure-domainqcom,msa-fixed-perm#mbox-cellsframe-number#redistributor-regionsredistributor-stride#freq-domain-cellspolling-delay-passivepolling-delaythermal-sensorstemperaturehysteresis