8ߐ('X)rockchip,rk3588-evb1-v10rockchip,rk3588 +7Rockchip RK3588 EVB1 V10 Boardcpus+cpu-mapcluster0core0=core1=core2=core3=cluster1core0=core1=cluster2core0=core1= cpu@0Acpuarm,cortex-a55MQpsci_r y 0, @@ 1@ Kcpu@100Acpuarm,cortex-a55MQpsci_r  @@1@ Kcpu@200Acpuarm,cortex-a55MQpsci_r  @@1@ Kcpu@300Acpuarm,cortex-a55MQpsci_r  @@1@ Kcpu@400Acpuarm,cortex-a76MQpsci_r y 0, @@1@Kcpu@500Acpuarm,cortex-a76MQpsci_r  @@1@Kcpu@600Acpuarm,cortex-a76MQpsci_r y 0, @@1@Kcpu@700Acpuarm,cortex-a76MQpsci_r  @@1@K idle-statesSpscicpu-sleeparm,idle-state`qdxK l2-cache-l0cache@K l2-cache-l1cache@Kl2-cache-l2cache@Kl2-cache-l3cache@Kl2-cache-b0cache@Kl2-cache-b1cache@Kl2-cache-b2cache@Kl2-cache-b3cache@Kl3-cachecache0@Kfirmwareopteelinaro,optee-tzXsmcscmi arm,scmi-smcԂ+protocol@14MK protocol@16Mpmu-a55arm,cortex-a55-pmupmu-a76arm,cortex-a76-pmupsci arm,psci-1.0Xsmcclock-0 fixed-clock )׫splltimerarm,armv8-timerP    %-sec-physphysvirthyp-physhyp-virtclock-1 fixed-clock n6xin24mclock-2 fixed-clock xin32ksram@10f000 mmio-sramM=+sram@0arm,scmi-shmemMKsyscon@fd58c000rockchip,rk3588-sys-grfsysconMXKUsyscon@fd5b0000rockchip,rk3588-php-grfsysconM[Ksyscon@fd5f0000rockchip,rk3588-iocsysconM_Ksram@fd600000 mmio-sramM`=`+clock-controller@fd7c0000rockchip,rk3588-cruM|y]q@A.2Fq)׫ׄe/ׄ eZ р DKi2c@fd880000(rockchip,rk3588-i2crockchip,rk3399-i2cM=rts Qi2cpclk]gdefault+ udisabledserial@fd890000&rockchip,rk3588-uartsnps,dw-apb-uartMKrQbaudclkapb_pclk|txrx]gdefault udisabledpwm@fd8b0000(rockchip,rk3588-pwmrockchip,rk3328-pwmMr Qpwmpclk] gdefault udisabledpwm@fd8b0010(rockchip,rk3588-pwmrockchip,rk3328-pwmMr Qpwmpclk]!gdefault udisabledpwm@fd8b0020(rockchip,rk3588-pwmrockchip,rk3328-pwmM r Qpwmpclk]"gdefaultuokayKpwm@fd8b0030(rockchip,rk3588-pwmrockchip,rk3328-pwmM0r Qpwmpclk]#gdefault udisabledpower-management@fd8d8000&rockchip,rk3588-pmusysconsimple-mfdMpower-controller!rockchip,rk3588-power-controller+uokayKTpower-domain@8M+power-domain@9M  r!#" $%&+power-domain@10M r!#"'power-domain@11M r!#"(power-domain@12M r)*+,power-domain@13M +power-domain@14M(r-power-domain@15M r.power-domain@16Mr /01+power-domain@17M r 234power-domain@21Mr 56789:;<+power-domain@23MrCA=power-domain@14M r-power-domain@15Mr.power-domain@22Mr>power-domain@24Mr[Z]?@+power-domain@25M8rZApower-domain@26M8rQBCpower-domain@27M0rDEFG+power-domain@28M rHIpower-domain@29M(rJKpower-domain@30Mrz{Lpower-domain@31M8rWMNOPpower-domain@33M!rWZ[power-domain@34M"rWZ[power-domain@37M%r2Qpower-domain@38M&r45power-domain@40M(Ri2s@fddc0000rockchip,rk3588-i2s-tdmMrQmclk_txmclk_rxhclky|StxTtx-m udisabledi2s@fddf0000rockchip,rk3588-i2s-tdmMr445Qmclk_txmclk_rxhclky1|StxTtx-m udisabledi2s@fddfc000rockchip,rk3588-i2s-tdmMr00,Qmclk_txmclk_rxhclky-|SrxTrx-m udisabledqos@fdf35000rockchip,rk3588-qossysconMP K)qos@fdf35200rockchip,rk3588-qossysconMR K*qos@fdf35400rockchip,rk3588-qossysconMT K+qos@fdf35600rockchip,rk3588-qossysconMV K,qos@fdf36000rockchip,rk3588-qossysconM` KLqos@fdf39000rockchip,rk3588-qossysconM KQqos@fdf3d800rockchip,rk3588-qossysconM KRqos@fdf3e000rockchip,rk3588-qossysconM KNqos@fdf3e200rockchip,rk3588-qossysconM KMqos@fdf3e400rockchip,rk3588-qossysconM KOqos@fdf3e600rockchip,rk3588-qossysconM KPqos@fdf40000rockchip,rk3588-qossysconM KJqos@fdf40200rockchip,rk3588-qossysconM KKqos@fdf40400rockchip,rk3588-qossysconM KDqos@fdf40500rockchip,rk3588-qossysconM KEqos@fdf40600rockchip,rk3588-qossysconM KFqos@fdf40800rockchip,rk3588-qossysconM KGqos@fdf41000rockchip,rk3588-qossysconM KHqos@fdf41100rockchip,rk3588-qossysconM KIqos@fdf60000rockchip,rk3588-qossysconM K/qos@fdf60200rockchip,rk3588-qossysconM K0qos@fdf60400rockchip,rk3588-qossysconM K1qos@fdf61000rockchip,rk3588-qossysconM K2qos@fdf61200rockchip,rk3588-qossysconM K3qos@fdf61400rockchip,rk3588-qossysconM K4qos@fdf62000rockchip,rk3588-qossysconM K-qos@fdf63000rockchip,rk3588-qossysconM0 K.qos@fdf64000rockchip,rk3588-qossysconM@ K=qos@fdf66000rockchip,rk3588-qossysconM` K5qos@fdf66200rockchip,rk3588-qossysconMb K6qos@fdf66400rockchip,rk3588-qossysconMd K7qos@fdf66600rockchip,rk3588-qossysconMf K8qos@fdf66800rockchip,rk3588-qossysconMh K9qos@fdf66a00rockchip,rk3588-qossysconMj K:qos@fdf66c00rockchip,rk3588-qossysconMl K;qos@fdf66e00rockchip,rk3588-qossysconMn K<qos@fdf67000rockchip,rk3588-qossysconMp K>qos@fdf67200rockchip,rk3588-qossysconMr qos@fdf70000rockchip,rk3588-qossysconM K'qos@fdf71000rockchip,rk3588-qossysconM K(qos@fdf72000rockchip,rk3588-qossysconM K$qos@fdf72200rockchip,rk3588-qossysconM" K%qos@fdf72400rockchip,rk3588-qossysconM$ K&qos@fdf80000rockchip,rk3588-qossysconM KAqos@fdf81000rockchip,rk3588-qossysconM KBqos@fdf81200rockchip,rk3588-qossysconM KCqos@fdf82000rockchip,rk3588-qossysconM K?qos@fdf82200rockchip,rk3588-qossysconM" K@ethernet@fe1c0000&rockchip,rk3588-gmacsnps,dwmac-4.20aM -macirqeth_wake_irq(r67Y^50Qstmmacethclk_mac_refpclk_macaclk_macptp_refT!$ stmmacethDU"V2CWVXi udisabledmdiosnps,dwmac-mdio+stmmac-axi-configr|KVrx-queues-configKWqueue0queue1tx-queues-configKXqueue0queue1mmc@fe2c00000rockchip,rk3588-dw-mshcrockchip,rk3288-dw-mshcM,@ r  Qbiuciuciu-driveciu-sample gdefault]YZ[\T( udisabledmmc@fe2d00000rockchip,rk3588-dw-mshcrockchip,rk3288-dw-mshcM-@ rQbiuciuciu-driveciu-sample gdefault]]T% udisabledmmc@fe2e0000rockchip,rk3588-dwcmshcM.y-., n6 (r,*+-.Qcorebusaxiblocktimer ]^_`abgdefault(corebusaxiblocktimeruokayi2s@fe470000rockchip,rk3588-i2s-tdmMGr+/(Qmclk_txmclk_rxhclky)-|txrxT&*+ tx-mrx-m0gdefault(]cdefghijkl udisabledi2s@fe480000rockchip,rk3588-i2s-tdmMHry}uQmclk_txmclk_rxhclk|txrx^_ tx-mrx-m0gdefault(]mnopqrstuv udisabledi2s@fe490000(rockchip,rk3588-i2srockchip,rk3066-i2sMIrQi2s_clki2s_hclky|wwtxrxT&0gdefault]xyz{ udisabledi2s@fe4a0000(rockchip,rk3588-i2srockchip,rk3066-i2sMJr%Qi2s_clki2s_hclky"|wwtxrxT&0gdefault]|}~ udisabledinterrupt-controller@fe600000 arm,gic-v3 M`h K`aj8u=+Kmsi-controller@fe640000arm,gic-v3-itsMdumsi-controller@fe660000arm,gic-v3-itsMfuppi-partitionsinterrupt-partition-0Kinterrupt-partition-1 Kdma-controller@fea10000arm,pl330arm,primecellM@ VWrn Qapb_pclkKdma-controller@fea30000arm,pl330arm,primecellM@ XYro Qapb_pclkKwi2c@fea90000(rockchip,rk3588-i2crockchip,rk3399-i2cMr{ Qi2cpclk>]gdefault+ udisabledi2c@feaa0000(rockchip,rk3588-i2crockchip,rk3399-i2cMr| Qi2cpclk?]gdefault+uokayrtc@51haoyu,hym8563MQhym8563gdefault] i2c@feab0000(rockchip,rk3588-i2crockchip,rk3399-i2cMr} Qi2cpclk@]gdefault+ udisabledi2c@feac0000(rockchip,rk3588-i2crockchip,rk3399-i2cMr~ Qi2cpclkA]gdefault+ udisabledi2c@fead0000(rockchip,rk3588-i2crockchip,rk3399-i2cMr Qi2cpclkB]gdefault+ udisabledtimer@feae0000,rockchip,rk3588-timerrockchip,rk3288-timerM !rTW Qpclktimerwatchdog@feaf0000 rockchip,rk3588-wdtsnps,dw-wdtMrdc Qtclkpclk;spi@feb00000(rockchip,rk3588-spirockchip,rk3066-spiMFrQspiclkapb_pclk|txrx ]gdefault+ udisabledspi@feb10000(rockchip,rk3588-spirockchip,rk3066-spiMGrQspiclkapb_pclk|txrx ]gdefault+ udisabledspi@feb20000(rockchip,rk3588-spirockchip,rk3066-spiMHrQspiclkapb_pclk|wwtxrx ]gdefault+uokayy pmic@0rockchip,rk806M ]gdefaultB@&2>JVbnzdvs1-null-pinsgpio_pwrctrl1 pin_fun0Kdvs2-null-pinsgpio_pwrctrl2 pin_fun0Kdvs3-null-pinsgpio_pwrctrl3 pin_fun0Kregulatorsdcdc-reg1dp~0 ,vdd_gpu_s0;regulator-state-memWdcdc-reg2pdp~0 ,vdd_npu_s0regulator-state-memWdcdc-reg3p L q0 ,vdd_log_s0regulator-state-memW qdcdc-reg4pdp~0 ,vdd_vdenc_s0regulator-state-memWdcdc-reg5 L~0;,vdd_gpu_mem_s0regulator-state-memWdcdc-reg6p L~0,vdd_npu_mem_s0regulator-state-memWdcdc-reg7p0,vdd_2v0_pldo_s3Kregulator-state-memdcdc-reg8p L~0,vdd_vdenc_mem_s0regulator-state-memWdcdc-reg9p ,vdd2_ddr_s3regulator-state-memdcdc-reg10p0,vcc_1v1_nldo_s3Kregulator-state-mempldo-reg1pw@w@0 ,avcc_1v8_s0regulator-state-memWpldo-reg2pw@w@0,vdd1_1v8_ddr_s3regulator-state-memw@pldo-reg3pw@w@0,avcc_1v8_codec_s0regulator-state-memWpldo-reg4p2Z2Z0 ,vcc_3v3_s3regulator-state-mem2Zpldo-reg5pw@2Z0 ,vccio_sd_s0regulator-state-memWpldo-reg6pw@w@0 ,vccio_1v8_s3regulator-state-memw@nldo-reg1p q q0 ,vdd_0v75_s3regulator-state-mem qnldo-reg2p  ,vdd2l_0v9_ddr_s3regulator-state-mem nldo-reg3p q q,vdd_0v75_hdmi_edp_s0regulator-state-memWnldo-reg4p q q ,avdd_0v75_s0regulator-state-memWnldo-reg5p P P ,vdd_0v85_s0regulator-state-memWpmic@1rockchip,rk806M  ]gdefaultB@&2>JVbnzdvs1-null-pinsgpio_pwrctrl1 pin_fun0Kdvs2-null-pinsgpio_pwrctrl2 pin_fun0Kdvs3-null-pinsgpio_pwrctrl3 pin_fun0Kregulatorsdcdc-reg1pdp0,vdd_cpu_big1_s0Kregulator-state-memWdcdc-reg2pdp0,vdd_cpu_big0_s0Kregulator-state-memWdcdc-reg3pdp~0,vdd_cpu_lit_s0K regulator-state-memWdcdc-reg4p2Z2Z0 ,vcc_3v3_s0regulator-state-memWdcdc-reg5p L0,vdd_cpu_big1_mem_s0regulator-state-memWdcdc-reg6p L0,vdd_cpu_big0_mem_s0regulator-state-memWdcdc-reg7pw@w@0 ,vcc_1v8_s0regulator-state-memWdcdc-reg8p L~0,vdd_cpu_lit_mem_s0regulator-state-memWdcdc-reg9p ,vddq_ddr_s0regulator-state-memWdcdc-reg10p L 0 ,vdd_ddr_s0regulator-state-memWpldo-reg1pw@w@0,vcc_1v8_cam_s0regulator-state-memWpldo-reg2pw@w@0,avdd1v8_ddr_pll_s0regulator-state-memWpldo-reg3pw@w@0,vdd_1v8_pll_s0regulator-state-memWpldo-reg4p2Z2Z0,vcc_3v3_sd_s0regulator-state-memWpldo-reg5p**0,vcc_2v8_cam_s0regulator-state-memWpldo-reg6pw@w@ ,pldo6_s3regulator-state-memw@nldo-reg1p q q0,vdd_0v75_pll_s0regulator-state-memWnldo-reg2p P P,vdd_ddr_pll_s0regulator-state-memWnldo-reg3p P P0 ,avdd_0v85_s0regulator-state-memWnldo-reg4pOO0,avdd_1v2_cam_s0regulator-state-memWnldo-reg5pOO0 ,avdd_1v2_s0regulator-state-memWspi@feb30000(rockchip,rk3588-spirockchip,rk3066-spiMIrQspiclkapb_pclk|wwtxrx ]gdefault+ udisabledserial@feb40000&rockchip,rk3588-uartsnps,dw-apb-uartMLrQbaudclkapb_pclk| txrx]gdefault udisabledserial@feb50000&rockchip,rk3588-uartsnps,dw-apb-uartMMrQbaudclkapb_pclk|  txrx]gdefaultuokayserial@feb60000&rockchip,rk3588-uartsnps,dw-apb-uartMNrQbaudclkapb_pclk|  txrx]gdefault udisabledserial@feb70000&rockchip,rk3588-uartsnps,dw-apb-uartMOrQbaudclkapb_pclk|w w txrx]gdefault udisabledserial@feb80000&rockchip,rk3588-uartsnps,dw-apb-uartMPrQbaudclkapb_pclk|w w txrx]gdefault udisabledserial@feb90000&rockchip,rk3588-uartsnps,dw-apb-uartMQrQbaudclkapb_pclk|w wtxrx]gdefault udisabledserial@feba0000&rockchip,rk3588-uartsnps,dw-apb-uartMRrQbaudclkapb_pclk|SStxrx]gdefault udisabledserial@febb0000&rockchip,rk3588-uartsnps,dw-apb-uartMSrQbaudclkapb_pclk|S S txrx]gdefault udisabledserial@febc0000&rockchip,rk3588-uartsnps,dw-apb-uartMTrQbaudclkapb_pclk|S S txrx]gdefault udisabledpwm@febd0000(rockchip,rk3588-pwmrockchip,rk3328-pwmMrLK Qpwmpclk]gdefault udisabledpwm@febd0010(rockchip,rk3588-pwmrockchip,rk3328-pwmMrLK Qpwmpclk]gdefault udisabledpwm@febd0020(rockchip,rk3588-pwmrockchip,rk3328-pwmM rLK Qpwmpclk]gdefault udisabledpwm@febd0030(rockchip,rk3588-pwmrockchip,rk3328-pwmM0rLK Qpwmpclk]gdefault udisabledpwm@febe0000(rockchip,rk3588-pwmrockchip,rk3328-pwmMrON Qpwmpclk]gdefault udisabledpwm@febe0010(rockchip,rk3588-pwmrockchip,rk3328-pwmMrON Qpwmpclk]gdefault udisabledpwm@febe0020(rockchip,rk3588-pwmrockchip,rk3328-pwmM rON Qpwmpclk]gdefault udisabledpwm@febe0030(rockchip,rk3588-pwmrockchip,rk3328-pwmM0rON Qpwmpclk]gdefault udisabledpwm@febf0000(rockchip,rk3588-pwmrockchip,rk3328-pwmMrRQ Qpwmpclk]gdefault udisabledpwm@febf0010(rockchip,rk3588-pwmrockchip,rk3328-pwmMrRQ Qpwmpclk]gdefault udisabledpwm@febf0020(rockchip,rk3588-pwmrockchip,rk3328-pwmM rRQ Qpwmpclk]gdefault udisabledpwm@febf0030(rockchip,rk3588-pwmrockchip,rk3328-pwmM0rRQ Qpwmpclk]gdefault udisabledtsadc@fec00000rockchip,rk3588-tsadcMrQtsadcapb_pclkyVWtsadc-apbtsadc] ggpiootpout  udisabledadc@fec10000rockchip,rk3588-saradcM!rQsaradcapb_pclkU saradc-apb udisabledi2c@fec80000(rockchip,rk3588-i2crockchip,rk3399-i2cMr Qi2cpclkC]gdefault+ udisabledi2c@fec90000(rockchip,rk3588-i2crockchip,rk3399-i2cMr Qi2cpclkD]gdefault+ udisabledi2c@feca0000(rockchip,rk3588-i2crockchip,rk3399-i2cMr Qi2cpclkE]gdefault+ udisabledspi@fecb0000(rockchip,rk3588-spirockchip,rk3066-spiMJrQspiclkapb_pclk|S Stxrx ]gdefault+ udisabledefuse@fecc0000rockchip,rk3588-otpM rQotpapb_pclkphyarb otpapbarb+cpu-code@2Mid@7Mcpu-leakage@17Mcpu-leakage@18Mcpu-leakage@19Mlog-leakage@1aMgpu-leakage@1bMcpu-version@1cM3npu-leakage@28M(codec-leakage@29M)dma-controller@fed10000arm,pl330arm,primecellM@ Z[rp Qapb_pclkKSsram@ff001000 mmio-sramM=+pinctrlrockchip,rk3588-pinctrl=D+Kgpio@fd8a0000rockchip,gpio-bankMrqr8 KKgpio@fec20000rockchip,gpio-bankMrst8 Kgpio@fec30000rockchip,gpio-bankMruv8@ Kgpio@fec40000rockchip,gpio-bankMrwx8` Kgpio@fec50000rockchip,gpio-bankMryz8 KKpcfg-pull-upDKpcfg-pull-noneQKpcfg-pull-none-drv-level-2Q^Kpcfg-pull-up-drv-level-1D^Kpcfg-pull-up-drv-level-2D^Kpcfg-pull-none-smtQmKauddsmbt1120can0can1can2cifclk32kcpuddrphych0ddrphych1ddrphych2ddrphych3dp0dp1emmcemmc-rstnoutK^emmc-bus8K_emmc-clkK`emmc-cmdKaemmc-data-strobeKbeth1fspigmac1gpuhdmii2c0i2c0m0-xfer  Ki2c1i2c1m0-xfer   Ki2c2i2c2m0-xfer   Ki2c3i2c3m0-xfer   Ki2c4i2c4m0-xfer   Ki2c5i2c5m0-xfer   Ki2c6i2c6m0-xfer   Ki2c7i2c7m0-xfer   Ki2c8i2c8m0-xfer   Ki2s0i2s0-lrckKci2s0-sclkKdi2s0-sdi0Kei2s0-sdi1Kfi2s0-sdi2Kgi2s0-sdi3Khi2s0-sdo0Kii2s0-sdo1Kji2s0-sdo2Kki2s0-sdo3Kli2s1i2s1m0-lrckKmi2s1m0-sclkKni2s1m0-sdi0Koi2s1m0-sdi1Kpi2s1m0-sdi2Kqi2s1m0-sdi3Kri2s1m0-sdo0 Ksi2s1m0-sdo1 Kti2s1m0-sdo2 Kui2s1m0-sdo3 Kvi2s2i2s2m1-lrckKxi2s2m1-sclk Kyi2s2m1-sdi Kzi2s2m1-sdo K{i2s3i2s3-lrckK|i2s3-sclkK}i2s3-sdiK~i2s3-sdoKjtaglitcpumcumipinpupcie20x1pcie30phypcie30x1pcie30x2pcie30x4pdm0pdm1pmicpmic-pinspKpmupwm0pwm0m0-pinsK pwm1pwm1m0-pinsK!pwm2pwm2m0-pinsK"pwm3pwm3m0-pinsK#pwm4pwm4m0-pins Kpwm5pwm5m0-pins Kpwm6pwm6m0-pins Kpwm7pwm7m0-pins Kpwm8pwm8m0-pins Kpwm9pwm9m0-pins Kpwm10pwm10m0-pins Kpwm11pwm11m0-pins Kpwm12pwm12m0-pins Kpwm13pwm13m0-pins Kpwm14pwm14m0-pins Kpwm15pwm15m0-pins Krefclksatasata0sata1sata2sdiosdiom1-pins`K]sdmmcsdmmc-bus4@K\sdmmc-clkKYsdmmc-cmdKZsdmmc-detK[spdif0spdif1spi0spi0m0-pins0Kspi0m0-cs0Kspi0m0-cs1Kspi1spi1m1-pins0Kspi1m1-cs0Kspi1m1-cs1Kspi2spi2m2-pins0 Kspi2m2-cs0 Kspi2m2-cs1Kspi3spi3m1-pins0 Kspi3m1-cs0Kspi3m1-cs1Kspi4spi4m0-pins0Kspi4m0-cs0Kspi4m0-cs1Ktsadctsadc-shutKuart0uart0m1-xfer  Kuart1uart1m1-xfer   Kuart2uart2m0-xfer  Kuart3uart3m1-xfer   Kuart4uart4m1-xfer   Kuart5uart5m1-xfer   Kuart6uart6m1-xfer   Kuart7uart7m1-xfer   Kuart8uart8m1-xfer   Kuart9uart9m1-xfer   Kvopbt656gpio-functsadc-gpio-funcKeth0gmac0gmac0-miim Kgmac0-rx-bus20Kgmac0-tx-bus20Kgmac0-rgmii-clk  Kgmac0-rgmii-bus@  Krtl8211frtl8211f-rst Khym8563hym8563-intKi2s@fddc8000rockchip,rk3588-i2s-tdmM܀rQmclk_txmclk_rxhclky|StxTtx-m udisabledi2s@fddf4000rockchip,rk3588-i2s-tdmM@r99?Qmclk_txmclk_rxhclky6|StxTtx-m udisabledi2s@fddf8000rockchip,rk3588-i2s-tdmM߀r++'Qmclk_txmclk_rxhclky(|SrxTrx-m udisabledi2s@fde00000rockchip,rk3588-i2s-tdmMr&&"Qmclk_txmclk_rxhclky#|SrxTrx-m udisabledethernet@fe1b0000&rockchip,rk3588-gmacsnps,dwmac-4.20aM -macirqeth_wake_irq(r67X]40Qstmmacethclk_mac_refpclk_macaclk_macptp_refT!# stmmacethDU"2CViuokayoutput rgmii-rxid]gdefaultCmdiosnps,dwmac-mdio+ethernet-phy@1ethernet-phy-id001c.c916Mgdefault]N   Kstmmac-axi-configr|Krx-queues-configKqueue0queue1tx-queues-configKqueue0queue1aliases/mmc@fe2e0000/serial@feb50000chosenserial2:1500000n8backlightpwm-backlight avcc12v-dcin-regulatorregulator-fixed ,vcc12v_dcinpKvcc5v0-sys-regulatorregulator-fixed ,vcc5v0_syspLK@LK@K compatibleinterrupt-parent#address-cells#size-cellsmodelcpudevice_typeregenable-methodcapacity-dmips-mhzclocksassigned-clocksassigned-clock-ratescpu-idle-statesi-cache-sizei-cache-line-sizei-cache-setsd-cache-sized-cache-line-sized-cache-setsnext-level-cachedynamic-power-coefficient#cooling-cellscpu-supplyphandleentry-methodlocal-timer-stoparm,psci-suspend-paramentry-latency-usexit-latency-usmin-residency-uscache-levelcache-unifiedarm,smc-idshmem#clock-cells#reset-cellsinterruptsclock-frequencyclock-output-namesinterrupt-namesrangesrockchip,grfclock-namespinctrl-0pinctrl-namesstatusdmasdma-namesreg-shiftreg-io-width#pwm-cells#power-domain-cellspm_qosassigned-clock-parentspower-domainsresetsreset-names#sound-dai-cellsrockchip,php-grfsnps,axi-configsnps,mixed-burstsnps,mtl-rx-configsnps,mtl-tx-configsnps,tsosnps,blensnps,wr_osr_lmtsnps,rd_osr_lmtsnps,rx-queues-to-usesnps,tx-queues-to-usefifo-depthmax-frequencybus-widthno-sdiono-sdnon-removablemmc-hs400-1_8vmmc-hs400-enhanced-stroberockchip,trcm-sync-tx-onlyinterrupt-controllermbi-aliasmbi-rangesmsi-controller#interrupt-cells#msi-cellsaffinityarm,pl330-periph-burst#dma-cellswakeup-sourcenum-cs#gpio-cellsgpio-controllerspi-max-frequencyvcc1-supplyvcc2-supplyvcc3-supplyvcc4-supplyvcc5-supplyvcc6-supplyvcc7-supplyvcc8-supplyvcc9-supplyvcc10-supplyvcc11-supplyvcc12-supplyvcc13-supplyvcc14-supplyvcca-supplypinsfunctionregulator-boot-onregulator-min-microvoltregulator-max-microvoltregulator-ramp-delayregulator-nameregulator-enable-ramp-delayregulator-off-in-suspendregulator-always-onregulator-suspend-microvoltregulator-on-in-suspendrockchip,hw-tshut-temprockchip,hw-tshut-moderockchip,hw-tshut-polaritypinctrl-1#thermal-sensor-cells#io-channel-cellsbitsgpio-rangesbias-pull-upbias-disabledrive-strengthinput-schmitt-enablerockchip,pinsclock_in_outphy-handlephy-moderx_delaytx_delayreset-assert-usreset-deassert-usreset-gpiosmmc0serial2stdout-pathpower-supplypwmsvin-supply