8(khadas,edge2rockchip,rk3588s + 7Khadas Edge2cpus+cpu-mapcluster0core0=core1=core2=core3=cluster1core0=core1=cluster2core0=core1= cpu@0Acpuarm,cortex-a55MQpsci_r y 0, @@ 1@cpu@100Acpuarm,cortex-a55MQpsci_r  @@ 1@cpu@200Acpuarm,cortex-a55MQpsci_r  @@1@cpu@300Acpuarm,cortex-a55MQpsci_r  @@1@cpu@400Acpuarm,cortex-a76MQpsci_r y 0, @@1@cpu@500Acpuarm,cortex-a76MQpsci_r  @@1@cpu@600Acpuarm,cortex-a76MQpsci_r y 0, @@1@cpu@700Acpuarm,cortex-a76MQpsci_r  @@1@ idle-statesHpscicpu-sleeparm,idle-stateUf}dx@ l2-cache-l0cache@@ l2-cache-l1cache@@ l2-cache-l2cache@@l2-cache-l3cache@@l2-cache-b0cache@@l2-cache-b1cache@@l2-cache-b2cache@@l2-cache-b3cache@@l3-cachecache0@@firmwareopteelinaro,optee-tzXsmcscmi arm,scmi-smcɂ+protocol@14M@ protocol@16Mpmu-a55arm,cortex-a55-pmupmu-a76arm,cortex-a76-pmupsci arm,psci-1.0Xsmcclock-0 fixed-clock)׫splltimerarm,armv8-timerP    %"sec-physphysvirthyp-physhyp-virtclock-1 fixed-clockn6xin24mclock-2 fixed-clockxin32ksram@10f000 mmio-sramM2+sram@0arm,scmi-shmemM@syscon@fd58c000rockchip,rk3588-sys-grfsysconMX@Rsyscon@fd5b0000rockchip,rk3588-php-grfsysconM[@syscon@fd5f0000rockchip,rk3588-iocsysconM_@sram@fd600000 mmio-sramM`2`+clock-controller@fd7c0000rockchip,rk3588-cruM|y]q@A.2Fq)׫ׄe/ׄ eZ р 9@i2c@fd880000(rockchip,rk3588-i2crockchip,rk3399-i2cM=rts Fi2cpclkR\default+ jdisabledserial@fd890000&rockchip,rk3588-uartsnps,dw-apb-uartMKrFbaudclkapb_pclkqvtxrxR\default jdisabledpwm@fd8b0000(rockchip,rk3588-pwmrockchip,rk3328-pwmMr FpwmpclkR\default jdisabledpwm@fd8b0010(rockchip,rk3588-pwmrockchip,rk3328-pwmMr FpwmpclkR\default jdisabledpwm@fd8b0020(rockchip,rk3588-pwmrockchip,rk3328-pwmM r FpwmpclkR\default jdisabledpwm@fd8b0030(rockchip,rk3588-pwmrockchip,rk3328-pwmM0r FpwmpclkR \default jdisabledpower-management@fd8d8000&rockchip,rk3588-pmusysconsimple-mfdMpower-controller!rockchip,rk3588-power-controller+jokay@Qpower-domain@8M+power-domain@9M  r!#" !"#+power-domain@10M r!#"$power-domain@11M r!#"%power-domain@12M r&'()power-domain@13M +power-domain@14M(r*power-domain@15M r+power-domain@16Mr ,-.+power-domain@17M r /01power-domain@21Mr 23456789+power-domain@23MrCA:power-domain@14M r*power-domain@15Mr+power-domain@22Mr;power-domain@24Mr[Z]<=+power-domain@25M8rZ>power-domain@26M8rQ?@power-domain@27M0rABCD+power-domain@28M rEFpower-domain@29M(rGHpower-domain@30Mrz{Ipower-domain@31M8rWJKLMpower-domain@33M!rWZ[power-domain@34M"rWZ[power-domain@37M%r2Npower-domain@38M&r45power-domain@40M(Oi2s@fddc0000rockchip,rk3588-i2s-tdmMrFmclk_txmclk_rxhclkyqPvtxQtx-m jdisabledi2s@fddf0000rockchip,rk3588-i2s-tdmMr445Fmclk_txmclk_rxhclky1qPvtxQtx-m jdisabledi2s@fddfc000rockchip,rk3588-i2s-tdmMr00,Fmclk_txmclk_rxhclky-qPvrxQrx-m jdisabledqos@fdf35000rockchip,rk3588-qossysconMP @&qos@fdf35200rockchip,rk3588-qossysconMR @'qos@fdf35400rockchip,rk3588-qossysconMT @(qos@fdf35600rockchip,rk3588-qossysconMV @)qos@fdf36000rockchip,rk3588-qossysconM` @Iqos@fdf39000rockchip,rk3588-qossysconM @Nqos@fdf3d800rockchip,rk3588-qossysconM @Oqos@fdf3e000rockchip,rk3588-qossysconM @Kqos@fdf3e200rockchip,rk3588-qossysconM @Jqos@fdf3e400rockchip,rk3588-qossysconM @Lqos@fdf3e600rockchip,rk3588-qossysconM @Mqos@fdf40000rockchip,rk3588-qossysconM @Gqos@fdf40200rockchip,rk3588-qossysconM @Hqos@fdf40400rockchip,rk3588-qossysconM @Aqos@fdf40500rockchip,rk3588-qossysconM @Bqos@fdf40600rockchip,rk3588-qossysconM @Cqos@fdf40800rockchip,rk3588-qossysconM @Dqos@fdf41000rockchip,rk3588-qossysconM @Eqos@fdf41100rockchip,rk3588-qossysconM @Fqos@fdf60000rockchip,rk3588-qossysconM @,qos@fdf60200rockchip,rk3588-qossysconM @-qos@fdf60400rockchip,rk3588-qossysconM @.qos@fdf61000rockchip,rk3588-qossysconM @/qos@fdf61200rockchip,rk3588-qossysconM @0qos@fdf61400rockchip,rk3588-qossysconM @1qos@fdf62000rockchip,rk3588-qossysconM @*qos@fdf63000rockchip,rk3588-qossysconM0 @+qos@fdf64000rockchip,rk3588-qossysconM@ @:qos@fdf66000rockchip,rk3588-qossysconM` @2qos@fdf66200rockchip,rk3588-qossysconMb @3qos@fdf66400rockchip,rk3588-qossysconMd @4qos@fdf66600rockchip,rk3588-qossysconMf @5qos@fdf66800rockchip,rk3588-qossysconMh @6qos@fdf66a00rockchip,rk3588-qossysconMj @7qos@fdf66c00rockchip,rk3588-qossysconMl @8qos@fdf66e00rockchip,rk3588-qossysconMn @9qos@fdf67000rockchip,rk3588-qossysconMp @;qos@fdf67200rockchip,rk3588-qossysconMr qos@fdf70000rockchip,rk3588-qossysconM @$qos@fdf71000rockchip,rk3588-qossysconM @%qos@fdf72000rockchip,rk3588-qossysconM @!qos@fdf72200rockchip,rk3588-qossysconM" @"qos@fdf72400rockchip,rk3588-qossysconM$ @#qos@fdf80000rockchip,rk3588-qossysconM @>qos@fdf81000rockchip,rk3588-qossysconM @?qos@fdf81200rockchip,rk3588-qossysconM @@qos@fdf82000rockchip,rk3588-qossysconM @<qos@fdf82200rockchip,rk3588-qossysconM" @=ethernet@fe1c0000&rockchip,rk3588-gmacsnps,dwmac-4.20aM "macirqeth_wake_irq(r67Y^50Fstmmacethclk_mac_refpclk_macaclk_macptp_refQ!$ stmmaceth9RS'8TKU^ jdisabledmdiosnps,dwmac-mdio+stmmac-axi-configgq@Srx-queues-config@Tqueue0queue1tx-queues-config@Uqueue0queue1mmc@fe2c00000rockchip,rk3588-dw-mshcrockchip,rk3288-dw-mshcM,@ r  Fbiuciuciu-driveciu-sample \defaultRVWXYQ( jdisabledmmc@fe2d00000rockchip,rk3588-dw-mshcrockchip,rk3288-dw-mshcM-@ rFbiuciuciu-driveciu-sample \defaultRZQ% jdisabledmmc@fe2e0000rockchip,rk3588-dwcmshcM.y-., n6 (r,*+-.Fcorebusaxiblocktimer R[\]^_\default(corebusaxiblocktimerjokay i2s@fe470000rockchip,rk3588-i2s-tdmMGr+/(Fmclk_txmclk_rxhclky)-qvtxrxQ&*+ tx-mrx-m%\default(R`abcdefghi jdisabledi2s@fe480000rockchip,rk3588-i2s-tdmMHry}uFmclk_txmclk_rxhclkqvtxrx^_ tx-mrx-m%\default(Rjklmnopqrs jdisabledi2s@fe490000(rockchip,rk3588-i2srockchip,rk3066-i2sMIrFi2s_clki2s_hclkyqttvtxrxQ&%\defaultRuvwx jdisabledi2s@fe4a0000(rockchip,rk3588-i2srockchip,rk3066-i2sMJr%Fi2s_clki2s_hclky"qttvtxrxQ&%\defaultRyz{| jdisabledinterrupt-controller@fe600000 arm,gic-v3 M`h @Ua_8j2y+@msi-controller@fe640000arm,gic-v3-itsMdjmsi-controller@fe660000arm,gic-v3-itsMfjppi-partitionsinterrupt-partition-0@interrupt-partition-1 @dma-controller@fea10000arm,pl330arm,primecellM@ VWrn Fapb_pclk@dma-controller@fea30000arm,pl330arm,primecellM@ XYro Fapb_pclk@ti2c@fea90000(rockchip,rk3588-i2crockchip,rk3399-i2cMr{ Fi2cpclk>R}\default+ jdisabledi2c@feaa0000(rockchip,rk3588-i2crockchip,rk3399-i2cMr| Fi2cpclk?R~\default+ jdisabledi2c@feab0000(rockchip,rk3588-i2crockchip,rk3399-i2cMr} Fi2cpclk@R\default+ jdisabledi2c@feac0000(rockchip,rk3588-i2crockchip,rk3399-i2cMr~ Fi2cpclkAR\default+ jdisabledi2c@fead0000(rockchip,rk3588-i2crockchip,rk3399-i2cMr Fi2cpclkBR\default+ jdisabledtimer@feae0000,rockchip,rk3588-timerrockchip,rk3288-timerM !rTW Fpclktimerwatchdog@feaf0000 rockchip,rk3588-wdtsnps,dw-wdtMrdc Ftclkpclk;spi@feb00000(rockchip,rk3588-spirockchip,rk3066-spiMFrFspiclkapb_pclkqvtxrx R\default+ jdisabledspi@feb10000(rockchip,rk3588-spirockchip,rk3066-spiMGrFspiclkapb_pclkqvtxrx R\default+ jdisabledspi@feb20000(rockchip,rk3588-spirockchip,rk3066-spiMHrFspiclkapb_pclkqttvtxrx R\default+ jdisabledspi@feb30000(rockchip,rk3588-spirockchip,rk3066-spiMIrFspiclkapb_pclkqttvtxrx R\default+ jdisabledserial@feb40000&rockchip,rk3588-uartsnps,dw-apb-uartMLrFbaudclkapb_pclkq vtxrxR\default jdisabledserial@feb50000&rockchip,rk3588-uartsnps,dw-apb-uartMMrFbaudclkapb_pclkq  vtxrxR\defaultjokayserial@feb60000&rockchip,rk3588-uartsnps,dw-apb-uartMNrFbaudclkapb_pclkq  vtxrxR\default jdisabledserial@feb70000&rockchip,rk3588-uartsnps,dw-apb-uartMOrFbaudclkapb_pclkqt t vtxrxR\default jdisabledserial@feb80000&rockchip,rk3588-uartsnps,dw-apb-uartMPrFbaudclkapb_pclkqt t vtxrxR\default jdisabledserial@feb90000&rockchip,rk3588-uartsnps,dw-apb-uartMQrFbaudclkapb_pclkqt tvtxrxR\default jdisabledserial@feba0000&rockchip,rk3588-uartsnps,dw-apb-uartMRrFbaudclkapb_pclkqPPvtxrxR\default jdisabledserial@febb0000&rockchip,rk3588-uartsnps,dw-apb-uartMSrFbaudclkapb_pclkqP P vtxrxR\default jdisabledserial@febc0000&rockchip,rk3588-uartsnps,dw-apb-uartMTrFbaudclkapb_pclkqP P vtxrxR\default jdisabledpwm@febd0000(rockchip,rk3588-pwmrockchip,rk3328-pwmMrLK FpwmpclkR\default jdisabledpwm@febd0010(rockchip,rk3588-pwmrockchip,rk3328-pwmMrLK FpwmpclkR\default jdisabledpwm@febd0020(rockchip,rk3588-pwmrockchip,rk3328-pwmM rLK FpwmpclkR\default jdisabledpwm@febd0030(rockchip,rk3588-pwmrockchip,rk3328-pwmM0rLK FpwmpclkR\default jdisabledpwm@febe0000(rockchip,rk3588-pwmrockchip,rk3328-pwmMrON FpwmpclkR\default jdisabledpwm@febe0010(rockchip,rk3588-pwmrockchip,rk3328-pwmMrON FpwmpclkR\default jdisabledpwm@febe0020(rockchip,rk3588-pwmrockchip,rk3328-pwmM rON FpwmpclkR\default jdisabledpwm@febe0030(rockchip,rk3588-pwmrockchip,rk3328-pwmM0rON FpwmpclkR\default jdisabledpwm@febf0000(rockchip,rk3588-pwmrockchip,rk3328-pwmMrRQ FpwmpclkR\default jdisabledpwm@febf0010(rockchip,rk3588-pwmrockchip,rk3328-pwmMrRQ FpwmpclkR\default jdisabledpwm@febf0020(rockchip,rk3588-pwmrockchip,rk3328-pwmM rRQ FpwmpclkR\default jdisabledpwm@febf0030(rockchip,rk3588-pwmrockchip,rk3328-pwmM0rRQ FpwmpclkR\default jdisabledtsadc@fec00000rockchip,rk3588-tsadcMrFtsadcapb_pclkyVWtsadc-apbtsadcR \gpiootpout jdisabledadc@fec10000rockchip,rk3588-saradcM0rFsaradcapb_pclkU saradc-apb jdisabledi2c@fec80000(rockchip,rk3588-i2crockchip,rk3399-i2cMr Fi2cpclkCR\default+ jdisabledi2c@fec90000(rockchip,rk3588-i2crockchip,rk3399-i2cMr Fi2cpclkDR\default+ jdisabledi2c@feca0000(rockchip,rk3588-i2crockchip,rk3399-i2cMr Fi2cpclkER\default+ jdisabledspi@fecb0000(rockchip,rk3588-spirockchip,rk3066-spiMJrFspiclkapb_pclkqP Pvtxrx R\default+ jdisabledefuse@fecc0000rockchip,rk3588-otpM rFotpapb_pclkphyarb otpapbarb+cpu-code@2Mid@7Mcpu-leakage@17Mcpu-leakage@18Mcpu-leakage@19Mlog-leakage@1aMgpu-leakage@1bMcpu-version@1cMBnpu-leakage@28M(codec-leakage@29M)dma-controller@fed10000arm,pl330arm,primecellM@ Z[rp Fapb_pclk@Psram@ff001000 mmio-sramM2+pinctrlrockchip,rk3588-pinctrl29+@gpio@fd8a0000rockchip,gpio-bankMrqrGW @cygpio@fec20000rockchip,gpio-bankMrstGW @cygpio@fec30000rockchip,gpio-bankMruvGW@ @cygpio@fec40000rockchip,gpio-bankMrwxGW` @cygpio@fec50000rockchip,gpio-bankMryzGW @cypcfg-pull-upo@pcfg-pull-none|@pcfg-pull-none-drv-level-2|@pcfg-pull-up-drv-level-1o@pcfg-pull-up-drv-level-2o@pcfg-pull-none-smt|@auddsmbt1120can0can1can2cifclk32kcpuddrphych0ddrphych1ddrphych2ddrphych3dp0dp1emmcemmc-rstnout@[emmc-bus8@\emmc-clk@]emmc-cmd@^emmc-data-strobe@_eth1fspigmac1gpuhdmii2c0i2c0m0-xfer  @i2c1i2c1m0-xfer   @}i2c2i2c2m0-xfer   @~i2c3i2c3m0-xfer   @i2c4i2c4m0-xfer   @i2c5i2c5m0-xfer   @i2c6i2c6m0-xfer   @i2c7i2c7m0-xfer   @i2c8i2c8m0-xfer   @i2s0i2s0-lrck@`i2s0-sclk@ai2s0-sdi0@bi2s0-sdi1@ci2s0-sdi2@di2s0-sdi3@ei2s0-sdo0@fi2s0-sdo1@gi2s0-sdo2@hi2s0-sdo3@ii2s1i2s1m0-lrck@ji2s1m0-sclk@ki2s1m0-sdi0@li2s1m0-sdi1@mi2s1m0-sdi2@ni2s1m0-sdi3@oi2s1m0-sdo0 @pi2s1m0-sdo1 @qi2s1m0-sdo2 @ri2s1m0-sdo3 @si2s2i2s2m1-lrck@ui2s2m1-sclk @vi2s2m1-sdi @wi2s2m1-sdo @xi2s3i2s3-lrck@yi2s3-sclk@zi2s3-sdi@{i2s3-sdo@|jtaglitcpumcumipinpupcie20x1pcie30phypcie30x1pcie30x2pcie30x4pdm0pdm1pmicpmupwm0pwm0m0-pins@pwm1pwm1m0-pins@pwm2pwm2m0-pins@pwm3pwm3m0-pins@ pwm4pwm4m0-pins @pwm5pwm5m0-pins @pwm6pwm6m0-pins @pwm7pwm7m0-pins @pwm8pwm8m0-pins @pwm9pwm9m0-pins @pwm10pwm10m0-pins @pwm11pwm11m0-pins @pwm12pwm12m0-pins @pwm13pwm13m0-pins @pwm14pwm14m0-pins @pwm15pwm15m0-pins @refclksatasata0sata1sata2sdiosdiom1-pins`@Zsdmmcsdmmc-bus4@@Ysdmmc-clk@Vsdmmc-cmd@Wsdmmc-det@Xspdif0spdif1spi0spi0m0-pins0@spi0m0-cs0@spi0m0-cs1@spi1spi1m1-pins0@spi1m1-cs0@spi1m1-cs1@spi2spi2m2-pins0 @spi2m2-cs0 @spi2m2-cs1@spi3spi3m1-pins0 @spi3m1-cs0@spi3m1-cs1@spi4spi4m0-pins0@spi4m0-cs0@spi4m0-cs1@tsadctsadc-shut@uart0uart0m1-xfer  @uart1uart1m1-xfer   @uart2uart2m0-xfer  @uart3uart3m1-xfer   @uart4uart4m1-xfer   @uart5uart5m1-xfer   @uart6uart6m1-xfer   @uart7uart7m1-xfer   @uart8uart8m1-xfer   @uart9uart9m1-xfer   @vopbt656gpio-functsadc-gpio-func@aliases/mmc@fe2e0000/serial@feb50000chosenserial2:1500000n8 compatibleinterrupt-parent#address-cells#size-cellsmodelcpudevice_typeregenable-methodcapacity-dmips-mhzclocksassigned-clocksassigned-clock-ratescpu-idle-statesi-cache-sizei-cache-line-sizei-cache-setsd-cache-sized-cache-line-sized-cache-setsnext-level-cachedynamic-power-coefficient#cooling-cellsphandleentry-methodlocal-timer-stoparm,psci-suspend-paramentry-latency-usexit-latency-usmin-residency-uscache-levelcache-unifiedarm,smc-idshmem#clock-cells#reset-cellsinterruptsclock-frequencyclock-output-namesinterrupt-namesrangesrockchip,grfclock-namespinctrl-0pinctrl-namesstatusdmasdma-namesreg-shiftreg-io-width#pwm-cells#power-domain-cellspm_qosassigned-clock-parentspower-domainsresetsreset-names#sound-dai-cellsrockchip,php-grfsnps,axi-configsnps,mixed-burstsnps,mtl-rx-configsnps,mtl-tx-configsnps,tsosnps,blensnps,wr_osr_lmtsnps,rd_osr_lmtsnps,rx-queues-to-usesnps,tx-queues-to-usefifo-depthmax-frequencybus-widthno-sdiono-sdnon-removablemmc-hs400-1_8vmmc-hs400-enhanced-stroberockchip,trcm-sync-tx-onlyinterrupt-controllermbi-aliasmbi-rangesmsi-controller#interrupt-cells#msi-cellsaffinityarm,pl330-periph-burst#dma-cellsnum-csrockchip,hw-tshut-temprockchip,hw-tshut-moderockchip,hw-tshut-polaritypinctrl-1#thermal-sensor-cells#io-channel-cellsbitsgpio-controllergpio-ranges#gpio-cellsbias-pull-upbias-disabledrive-strengthinput-schmitt-enablerockchip,pinsmmc0serial2stdout-path