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EVEX_INSTRUCTIONS()::
# EMITTING VADDPH (VADDPH-128-1)
{
ICLASS:      VADDPH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_128
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR 
PATTERN:    EVV 0x58 VNP MAP5 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn]  VL128  W0
OPERANDS:    REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 REG3=XMM_B3():r:dq:f16
IFORM:       VADDPH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512
}

{
ICLASS:      VADDPH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_128
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR 
PATTERN:    EVV 0x58 VNP MAP5 MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn]  MODRM()  VL128  W0    ESIZE_16_BITS() NELEM_FULL()
OPERANDS:    REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 MEM0:r:vv:f16:TXT=BCASTSTR
IFORM:       VADDPH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512
}


# EMITTING VADDPH (VADDPH-256-1)
{
ICLASS:      VADDPH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_256
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR 
PATTERN:    EVV 0x58 VNP MAP5 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn]  VL256  W0
OPERANDS:    REG0=YMM_R3():w:qq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f16 REG3=YMM_B3():r:qq:f16
IFORM:       VADDPH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512
}

{
ICLASS:      VADDPH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_256
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR 
PATTERN:    EVV 0x58 VNP MAP5 MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn]  MODRM()  VL256  W0    ESIZE_16_BITS() NELEM_FULL()
OPERANDS:    REG0=YMM_R3():w:qq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f16 MEM0:r:vv:f16:TXT=BCASTSTR
IFORM:       VADDPH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512
}


# EMITTING VADDPH (VADDPH-512-1)
{
ICLASS:      VADDPH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR 
PATTERN:    EVV 0x58 VNP MAP5 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn]  VL512  W0
OPERANDS:    REG0=ZMM_R3():w:zf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf16 REG3=ZMM_B3():r:zf16
IFORM:       VADDPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512
}

{
ICLASS:      VADDPH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR 
PATTERN:    EVV 0x58 VNP MAP5 MOD[0b11] MOD=3 BCRC=1 UBIT=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND()  W0
OPERANDS:    REG0=ZMM_R3():w:zf16:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf16 REG3=ZMM_B3():r:zf16
IFORM:       VADDPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512
}

{
ICLASS:      VADDPH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR 
PATTERN:    EVV 0x58 VNP MAP5 MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn]  MODRM()  VL512  W0    ESIZE_16_BITS() NELEM_FULL()
OPERANDS:    REG0=ZMM_R3():w:zf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf16 MEM0:r:vv:f16:TXT=BCASTSTR
IFORM:       VADDPH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512
}


# EMITTING VADDSH (VADDSH-128-1)
{
ICLASS:      VADDSH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_SCALAR
EXCEPTIONS:     AVX512-E3
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR SIMD_SCALAR 
PATTERN:    EVV 0x58 VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn]  FIX_ROUND_LEN128() W0   
OPERANDS:    REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 REG3=XMM_B3():r:dq:f16
IFORM:       VADDSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512
}

{
ICLASS:      VADDSH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_SCALAR
EXCEPTIONS:     AVX512-E3
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR SIMD_SCALAR 
PATTERN:    EVV 0x58 VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 UBIT=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND()  W0   
OPERANDS:    REG0=XMM_R3():w:dq:f16:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 REG3=XMM_B3():r:dq:f16
IFORM:       VADDSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512
}

{
ICLASS:      VADDSH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_SCALAR
EXCEPTIONS:     AVX512-E3
REAL_OPCODE: Y
ATTRIBUTES:  DISP8_SCALAR MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR SIMD_SCALAR 
PATTERN:    EVV 0x58 VF3 MAP5 MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn] BCRC=0 MODRM()  FIX_ROUND_LEN128() W0    ESIZE_16_BITS() NELEM_SCALAR() 
OPERANDS:    REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 MEM0:r:wrd:f16
IFORM:       VADDSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512
}


# EMITTING VCMPPH (VCMPPH-128-1)
{
ICLASS:      VCMPPH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_128
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR 
PATTERN:    EVV 0xC2 VNP V0F3A MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn]  VL128  W0    ZEROING=0 UIMM8() 
OPERANDS:    REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:f16 REG3=XMM_B3():r:dq:f16 IMM0:r:b
IFORM:       VCMPPH_MASKmskw_MASKmskw_XMMf16_XMMf16_IMM8_AVX512
}

{
ICLASS:      VCMPPH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_128
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR 
PATTERN:    EVV 0xC2 VNP V0F3A MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn]  MODRM()  VL128  W0    ZEROING=0 UIMM8()  ESIZE_16_BITS() NELEM_FULL() 
OPERANDS:    REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:f16 MEM0:r:vv:f16:TXT=BCASTSTR IMM0:r:b
IFORM:       VCMPPH_MASKmskw_MASKmskw_XMMf16_MEMf16_IMM8_AVX512
}


# EMITTING VCMPPH (VCMPPH-256-1)
{
ICLASS:      VCMPPH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_256
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR 
PATTERN:    EVV 0xC2 VNP V0F3A MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn]  VL256  W0    ZEROING=0 UIMM8() 
OPERANDS:    REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:f16 REG3=YMM_B3():r:qq:f16 IMM0:r:b
IFORM:       VCMPPH_MASKmskw_MASKmskw_YMMf16_YMMf16_IMM8_AVX512
}

{
ICLASS:      VCMPPH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_256
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR 
PATTERN:    EVV 0xC2 VNP V0F3A MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn]  MODRM()  VL256  W0    ZEROING=0 UIMM8()  ESIZE_16_BITS() NELEM_FULL() 
OPERANDS:    REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:f16 MEM0:r:vv:f16:TXT=BCASTSTR IMM0:r:b
IFORM:       VCMPPH_MASKmskw_MASKmskw_YMMf16_MEMf16_IMM8_AVX512
}


# EMITTING VCMPPH (VCMPPH-512-1)
{
ICLASS:      VCMPPH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR 
PATTERN:    EVV 0xC2 VNP V0F3A MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn]  VL512  W0    ZEROING=0 UIMM8() 
OPERANDS:    REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zf16 REG3=ZMM_B3():r:zf16 IMM0:r:b
IFORM:       VCMPPH_MASKmskw_MASKmskw_ZMMf16_ZMMf16_IMM8_AVX512
}

{
ICLASS:      VCMPPH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR 
PATTERN:    EVV 0xC2 VNP V0F3A MOD[0b11] MOD=3 BCRC=1 UBIT=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE()  W0    ZEROING=0 UIMM8() 
OPERANDS:    REG0=MASK_R():w:mskw:TXT=SAESTR REG1=MASK1():r:mskw REG2=ZMM_N3():r:zf16 REG3=ZMM_B3():r:zf16 IMM0:r:b
IFORM:       VCMPPH_MASKmskw_MASKmskw_ZMMf16_ZMMf16_IMM8_AVX512
}

{
ICLASS:      VCMPPH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR 
PATTERN:    EVV 0xC2 VNP V0F3A MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn]  MODRM()  VL512  W0    ZEROING=0 UIMM8()  ESIZE_16_BITS() NELEM_FULL() 
OPERANDS:    REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zf16 MEM0:r:vv:f16:TXT=BCASTSTR IMM0:r:b
IFORM:       VCMPPH_MASKmskw_MASKmskw_ZMMf16_MEMf16_IMM8_AVX512
}


# EMITTING VCMPSH (VCMPSH-128-1)
{
ICLASS:      VCMPSH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_SCALAR
EXCEPTIONS:     AVX512-E3
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR SIMD_SCALAR 
PATTERN:    EVV 0xC2 VF3 V0F3A MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn]  FIX_ROUND_LEN128() W0    ZEROING=0 UIMM8() 
OPERANDS:    REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:f16 REG3=XMM_B3():r:dq:f16 IMM0:r:b
IFORM:       VCMPSH_MASKmskw_MASKmskw_XMMf16_XMMf16_IMM8_AVX512
}

{
ICLASS:      VCMPSH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_SCALAR
EXCEPTIONS:     AVX512-E3
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR SIMD_SCALAR 
PATTERN:    EVV 0xC2 VF3 V0F3A MOD[0b11] MOD=3 BCRC=1 UBIT=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE()  W0    ZEROING=0 UIMM8() 
OPERANDS:    REG0=MASK_R():w:mskw:TXT=SAESTR REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:f16 REG3=XMM_B3():r:dq:f16 IMM0:r:b
IFORM:       VCMPSH_MASKmskw_MASKmskw_XMMf16_XMMf16_IMM8_AVX512
}

{
ICLASS:      VCMPSH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_SCALAR
EXCEPTIONS:     AVX512-E3
REAL_OPCODE: Y
ATTRIBUTES:  DISP8_SCALAR MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR SIMD_SCALAR 
PATTERN:    EVV 0xC2 VF3 V0F3A MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn] BCRC=0 MODRM()  FIX_ROUND_LEN128() W0    ZEROING=0 UIMM8()  ESIZE_16_BITS() NELEM_SCALAR() 
OPERANDS:    REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:f16 MEM0:r:wrd:f16 IMM0:r:b
IFORM:       VCMPSH_MASKmskw_MASKmskw_XMMf16_MEMf16_IMM8_AVX512
}


# EMITTING VCOMISH (VCOMISH-128-1)
{
ICLASS:      VCOMISH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_SCALAR
EXCEPTIONS:     AVX512-E3NF
REAL_OPCODE: Y
FLAGS:       MUST [  zf-mod pf-mod cf-mod of-0 sf-0 af-0  ]
ATTRIBUTES:  MXCSR SIMD_SCALAR 
PATTERN:    EVV 0x2F VNP MAP5 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn]  FIX_ROUND_LEN128() W0  NOEVSR  ZEROING=0 MASK=0 
OPERANDS:    REG0=XMM_R3():r:dq:f16 REG1=XMM_B3():r:dq:f16
IFORM:       VCOMISH_XMMf16_XMMf16_AVX512
}

{
ICLASS:      VCOMISH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_SCALAR
EXCEPTIONS:     AVX512-E3NF
REAL_OPCODE: Y
FLAGS:       MUST [  zf-mod pf-mod cf-mod of-0 sf-0 af-0  ]
ATTRIBUTES:  MXCSR SIMD_SCALAR 
PATTERN:    EVV 0x2F VNP MAP5 MOD[0b11] MOD=3 BCRC=1 UBIT=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE()  W0  NOEVSR  ZEROING=0 MASK=0 
OPERANDS:    REG0=XMM_R3():r:dq:f16:TXT=SAESTR REG1=XMM_B3():r:dq:f16
IFORM:       VCOMISH_XMMf16_XMMf16_AVX512
}

{
ICLASS:      VCOMISH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_SCALAR
EXCEPTIONS:     AVX512-E3NF
REAL_OPCODE: Y
FLAGS:       MUST [  zf-mod pf-mod cf-mod of-0 sf-0 af-0  ]
ATTRIBUTES:  DISP8_SCALAR MXCSR SIMD_SCALAR 
PATTERN:    EVV 0x2F VNP MAP5 MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn] BCRC=0 MODRM()  FIX_ROUND_LEN128() W0  NOEVSR  ZEROING=0 MASK=0  ESIZE_16_BITS() NELEM_SCALAR() 
OPERANDS:    REG0=XMM_R3():r:dq:f16 MEM0:r:wrd:f16
IFORM:       VCOMISH_XMMf16_MEMf16_AVX512
}


# EMITTING VCVTDQ2PH (VCVTDQ2PH-128-1)
{
ICLASS:      VCVTDQ2PH
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_128
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR 
PATTERN:    EVV 0x5B VNP MAP5 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn]  VL128  W0  NOEVSR 
OPERANDS:    REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i32
IFORM:       VCVTDQ2PH_XMMf16_MASKmskw_XMMi32_AVX512
}

{
ICLASS:      VCVTDQ2PH
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_128
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR 
PATTERN:    EVV 0x5B VNP MAP5 MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn]  MODRM()  VL128  W0  NOEVSR  ESIZE_32_BITS() NELEM_FULL() 
OPERANDS:    REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:i32:TXT=BCASTSTR
IFORM:       VCVTDQ2PH_XMMf16_MASKmskw_MEMi32_AVX512_VL128
}


# EMITTING VCVTDQ2PH (VCVTDQ2PH-256-1)
{
ICLASS:      VCVTDQ2PH
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_256
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR 
PATTERN:    EVV 0x5B VNP MAP5 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn]  VL256  W0  NOEVSR 
OPERANDS:    REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:i32
IFORM:       VCVTDQ2PH_XMMf16_MASKmskw_YMMi32_AVX512
}

{
ICLASS:      VCVTDQ2PH
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_256
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR 
PATTERN:    EVV 0x5B VNP MAP5 MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn]  MODRM()  VL256  W0  NOEVSR  ESIZE_32_BITS() NELEM_FULL() 
OPERANDS:    REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:i32:TXT=BCASTSTR
IFORM:       VCVTDQ2PH_XMMf16_MASKmskw_MEMi32_AVX512_VL256
}


# EMITTING VCVTDQ2PH (VCVTDQ2PH-512-1)
{
ICLASS:      VCVTDQ2PH
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR 
PATTERN:    EVV 0x5B VNP MAP5 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn]  VL512  W0  NOEVSR 
OPERANDS:    REG0=YMM_R3():w:qq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zi32
IFORM:       VCVTDQ2PH_YMMf16_MASKmskw_ZMMi32_AVX512
}

{
ICLASS:      VCVTDQ2PH
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR 
PATTERN:    EVV 0x5B VNP MAP5 MOD[0b11] MOD=3 BCRC=1 UBIT=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND()  W0  NOEVSR 
OPERANDS:    REG0=YMM_R3():w:qq:f16:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zi32
IFORM:       VCVTDQ2PH_YMMf16_MASKmskw_ZMMi32_AVX512
}

{
ICLASS:      VCVTDQ2PH
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR 
PATTERN:    EVV 0x5B VNP MAP5 MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn]  MODRM()  VL512  W0  NOEVSR  ESIZE_32_BITS() NELEM_FULL() 
OPERANDS:    REG0=YMM_R3():w:qq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:i32:TXT=BCASTSTR
IFORM:       VCVTDQ2PH_YMMf16_MASKmskw_MEMi32_AVX512
}


# EMITTING VCVTPD2PH (VCVTPD2PH-128-1)
{
ICLASS:      VCVTPD2PH
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_128
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR USES_DAZ 
PATTERN:    EVV 0x5A V66 MAP5 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn]  VL128  W1  NOEVSR 
OPERANDS:    REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f64
IFORM:       VCVTPD2PH_XMMf16_MASKmskw_XMMf64_AVX512
}

{
ICLASS:      VCVTPD2PH
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_128
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR USES_DAZ 
PATTERN:    EVV 0x5A V66 MAP5 MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn]  MODRM()  VL128  W1  NOEVSR  ESIZE_64_BITS() NELEM_FULL() 
OPERANDS:    REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR
IFORM:       VCVTPD2PH_XMMf16_MASKmskw_MEMf64_AVX512_VL128
}


# EMITTING VCVTPD2PH (VCVTPD2PH-256-1)
{
ICLASS:      VCVTPD2PH
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_256
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR USES_DAZ 
PATTERN:    EVV 0x5A V66 MAP5 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn]  VL256  W1  NOEVSR 
OPERANDS:    REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f64
IFORM:       VCVTPD2PH_XMMf16_MASKmskw_YMMf64_AVX512
}

{
ICLASS:      VCVTPD2PH
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_256
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR USES_DAZ 
PATTERN:    EVV 0x5A V66 MAP5 MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn]  MODRM()  VL256  W1  NOEVSR  ESIZE_64_BITS() NELEM_FULL() 
OPERANDS:    REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR
IFORM:       VCVTPD2PH_XMMf16_MASKmskw_MEMf64_AVX512_VL256
}


# EMITTING VCVTPD2PH (VCVTPD2PH-512-1)
{
ICLASS:      VCVTPD2PH
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR USES_DAZ 
PATTERN:    EVV 0x5A V66 MAP5 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn]  VL512  W1  NOEVSR 
OPERANDS:    REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64
IFORM:       VCVTPD2PH_XMMf16_MASKmskw_ZMMf64_AVX512
}

{
ICLASS:      VCVTPD2PH
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR USES_DAZ 
PATTERN:    EVV 0x5A V66 MAP5 MOD[0b11] MOD=3 BCRC=1 UBIT=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND()  W1  NOEVSR 
OPERANDS:    REG0=XMM_R3():w:dq:f16:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64
IFORM:       VCVTPD2PH_XMMf16_MASKmskw_ZMMf64_AVX512
}

{
ICLASS:      VCVTPD2PH
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR USES_DAZ 
PATTERN:    EVV 0x5A V66 MAP5 MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn]  MODRM()  VL512  W1  NOEVSR  ESIZE_64_BITS() NELEM_FULL() 
OPERANDS:    REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR
IFORM:       VCVTPD2PH_XMMf16_MASKmskw_MEMf64_AVX512_VL512
}


# EMITTING VCVTPH2DQ (VCVTPH2DQ-128-1)
{
ICLASS:      VCVTPH2DQ
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_128
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR 
PATTERN:    EVV 0x5B V66 MAP5 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn]  VL128  W0  NOEVSR 
OPERANDS:    REG0=XMM_R3():w:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f16
IFORM:       VCVTPH2DQ_XMMi32_MASKmskw_XMMf16_AVX512
}

{
ICLASS:      VCVTPH2DQ
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_128
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_HALF MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR 
PATTERN:    EVV 0x5B V66 MAP5 MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn]  MODRM()  VL128  W0  NOEVSR  ESIZE_16_BITS() NELEM_HALF() 
OPERANDS:    REG0=XMM_R3():w:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f16:TXT=BCASTSTR
IFORM:       VCVTPH2DQ_XMMi32_MASKmskw_MEMf16_AVX512
}


# EMITTING VCVTPH2DQ (VCVTPH2DQ-256-1)
{
ICLASS:      VCVTPH2DQ
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_256
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR 
PATTERN:    EVV 0x5B V66 MAP5 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn]  VL256  W0  NOEVSR 
OPERANDS:    REG0=YMM_R3():w:qq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f16
IFORM:       VCVTPH2DQ_YMMi32_MASKmskw_XMMf16_AVX512
}

{
ICLASS:      VCVTPH2DQ
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_256
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_HALF MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR 
PATTERN:    EVV 0x5B V66 MAP5 MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn]  MODRM()  VL256  W0  NOEVSR  ESIZE_16_BITS() NELEM_HALF() 
OPERANDS:    REG0=YMM_R3():w:qq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f16:TXT=BCASTSTR
IFORM:       VCVTPH2DQ_YMMi32_MASKmskw_MEMf16_AVX512
}


# EMITTING VCVTPH2DQ (VCVTPH2DQ-512-1)
{
ICLASS:      VCVTPH2DQ
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR 
PATTERN:    EVV 0x5B V66 MAP5 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn]  VL512  W0  NOEVSR 
OPERANDS:    REG0=ZMM_R3():w:zi32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f16
IFORM:       VCVTPH2DQ_ZMMi32_MASKmskw_YMMf16_AVX512
}

{
ICLASS:      VCVTPH2DQ
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR 
PATTERN:    EVV 0x5B V66 MAP5 MOD[0b11] MOD=3 BCRC=1 UBIT=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND()  W0  NOEVSR 
OPERANDS:    REG0=ZMM_R3():w:zi32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f16
IFORM:       VCVTPH2DQ_ZMMi32_MASKmskw_YMMf16_AVX512
}

{
ICLASS:      VCVTPH2DQ
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_HALF MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR 
PATTERN:    EVV 0x5B V66 MAP5 MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn]  MODRM()  VL512  W0  NOEVSR  ESIZE_16_BITS() NELEM_HALF() 
OPERANDS:    REG0=ZMM_R3():w:zi32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f16:TXT=BCASTSTR
IFORM:       VCVTPH2DQ_ZMMi32_MASKmskw_MEMf16_AVX512
}


# EMITTING VCVTPH2PD (VCVTPH2PD-128-1)
{
ICLASS:      VCVTPH2PD
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_128
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR USES_FTZ 
PATTERN:    EVV 0x5A VNP MAP5 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn]  VL128  W0  NOEVSR 
OPERANDS:    REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f16
IFORM:       VCVTPH2PD_XMMf64_MASKmskw_XMMf16_AVX512
}

{
ICLASS:      VCVTPH2PD
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_128
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_QUARTER MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR USES_FTZ 
PATTERN:    EVV 0x5A VNP MAP5 MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn]  MODRM()  VL128  W0  NOEVSR  ESIZE_16_BITS() NELEM_QUARTER() 
OPERANDS:    REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f16:TXT=BCASTSTR
IFORM:       VCVTPH2PD_XMMf64_MASKmskw_MEMf16_AVX512
}


# EMITTING VCVTPH2PD (VCVTPH2PD-256-1)
{
ICLASS:      VCVTPH2PD
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_256
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR USES_FTZ 
PATTERN:    EVV 0x5A VNP MAP5 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn]  VL256  W0  NOEVSR 
OPERANDS:    REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f16
IFORM:       VCVTPH2PD_YMMf64_MASKmskw_XMMf16_AVX512
}

{
ICLASS:      VCVTPH2PD
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_256
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_QUARTER MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR USES_FTZ 
PATTERN:    EVV 0x5A VNP MAP5 MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn]  MODRM()  VL256  W0  NOEVSR  ESIZE_16_BITS() NELEM_QUARTER() 
OPERANDS:    REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f16:TXT=BCASTSTR
IFORM:       VCVTPH2PD_YMMf64_MASKmskw_MEMf16_AVX512
}


# EMITTING VCVTPH2PD (VCVTPH2PD-512-1)
{
ICLASS:      VCVTPH2PD
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR USES_FTZ 
PATTERN:    EVV 0x5A VNP MAP5 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn]  VL512  W0  NOEVSR 
OPERANDS:    REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f16
IFORM:       VCVTPH2PD_ZMMf64_MASKmskw_XMMf16_AVX512
}

{
ICLASS:      VCVTPH2PD
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR USES_FTZ 
PATTERN:    EVV 0x5A VNP MAP5 MOD[0b11] MOD=3 BCRC=1 UBIT=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE()  W0  NOEVSR 
OPERANDS:    REG0=ZMM_R3():w:zf64:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f16
IFORM:       VCVTPH2PD_ZMMf64_MASKmskw_XMMf16_AVX512
}

{
ICLASS:      VCVTPH2PD
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_QUARTER MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR USES_FTZ 
PATTERN:    EVV 0x5A VNP MAP5 MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn]  MODRM()  VL512  W0  NOEVSR  ESIZE_16_BITS() NELEM_QUARTER() 
OPERANDS:    REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f16:TXT=BCASTSTR
IFORM:       VCVTPH2PD_ZMMf64_MASKmskw_MEMf16_AVX512
}


# EMITTING VCVTPH2PSX (VCVTPH2PSX-128-1)
{
ICLASS:      VCVTPH2PSX
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_128
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR USES_FTZ 
PATTERN:    EVV 0x13 V66 MAP6 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn]  VL128  W0  NOEVSR 
OPERANDS:    REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f16
IFORM:       VCVTPH2PSX_XMMf32_MASKmskw_XMMf16_AVX512
}

{
ICLASS:      VCVTPH2PSX
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_128
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_HALF MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR USES_FTZ 
PATTERN:    EVV 0x13 V66 MAP6 MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn]  MODRM()  VL128  W0  NOEVSR  ESIZE_16_BITS() NELEM_HALF() 
OPERANDS:    REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f16:TXT=BCASTSTR
IFORM:       VCVTPH2PSX_XMMf32_MASKmskw_MEMf16_AVX512
}


# EMITTING VCVTPH2PSX (VCVTPH2PSX-256-1)
{
ICLASS:      VCVTPH2PSX
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_256
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR USES_FTZ 
PATTERN:    EVV 0x13 V66 MAP6 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn]  VL256  W0  NOEVSR 
OPERANDS:    REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f16
IFORM:       VCVTPH2PSX_YMMf32_MASKmskw_XMMf16_AVX512
}

{
ICLASS:      VCVTPH2PSX
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_256
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_HALF MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR USES_FTZ 
PATTERN:    EVV 0x13 V66 MAP6 MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn]  MODRM()  VL256  W0  NOEVSR  ESIZE_16_BITS() NELEM_HALF() 
OPERANDS:    REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f16:TXT=BCASTSTR
IFORM:       VCVTPH2PSX_YMMf32_MASKmskw_MEMf16_AVX512
}


# EMITTING VCVTPH2PSX (VCVTPH2PSX-512-1)
{
ICLASS:      VCVTPH2PSX
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR USES_FTZ 
PATTERN:    EVV 0x13 V66 MAP6 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn]  VL512  W0  NOEVSR 
OPERANDS:    REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f16
IFORM:       VCVTPH2PSX_ZMMf32_MASKmskw_YMMf16_AVX512
}

{
ICLASS:      VCVTPH2PSX
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR USES_FTZ 
PATTERN:    EVV 0x13 V66 MAP6 MOD[0b11] MOD=3 BCRC=1 UBIT=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE()  W0  NOEVSR 
OPERANDS:    REG0=ZMM_R3():w:zf32:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f16
IFORM:       VCVTPH2PSX_ZMMf32_MASKmskw_YMMf16_AVX512
}

{
ICLASS:      VCVTPH2PSX
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_HALF MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR USES_FTZ 
PATTERN:    EVV 0x13 V66 MAP6 MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn]  MODRM()  VL512  W0  NOEVSR  ESIZE_16_BITS() NELEM_HALF() 
OPERANDS:    REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f16:TXT=BCASTSTR
IFORM:       VCVTPH2PSX_ZMMf32_MASKmskw_MEMf16_AVX512
}


# EMITTING VCVTPH2QQ (VCVTPH2QQ-128-1)
{
ICLASS:      VCVTPH2QQ
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_128
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR 
PATTERN:    EVV 0x7B V66 MAP5 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn]  VL128  W0  NOEVSR 
OPERANDS:    REG0=XMM_R3():w:dq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f16
IFORM:       VCVTPH2QQ_XMMi64_MASKmskw_XMMf16_AVX512
}

{
ICLASS:      VCVTPH2QQ
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_128
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_QUARTER MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR 
PATTERN:    EVV 0x7B V66 MAP5 MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn]  MODRM()  VL128  W0  NOEVSR  ESIZE_16_BITS() NELEM_QUARTER() 
OPERANDS:    REG0=XMM_R3():w:dq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f16:TXT=BCASTSTR
IFORM:       VCVTPH2QQ_XMMi64_MASKmskw_MEMf16_AVX512
}


# EMITTING VCVTPH2QQ (VCVTPH2QQ-256-1)
{
ICLASS:      VCVTPH2QQ
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_256
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR 
PATTERN:    EVV 0x7B V66 MAP5 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn]  VL256  W0  NOEVSR 
OPERANDS:    REG0=YMM_R3():w:qq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f16
IFORM:       VCVTPH2QQ_YMMi64_MASKmskw_XMMf16_AVX512
}

{
ICLASS:      VCVTPH2QQ
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_256
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_QUARTER MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR 
PATTERN:    EVV 0x7B V66 MAP5 MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn]  MODRM()  VL256  W0  NOEVSR  ESIZE_16_BITS() NELEM_QUARTER() 
OPERANDS:    REG0=YMM_R3():w:qq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f16:TXT=BCASTSTR
IFORM:       VCVTPH2QQ_YMMi64_MASKmskw_MEMf16_AVX512
}


# EMITTING VCVTPH2QQ (VCVTPH2QQ-512-1)
{
ICLASS:      VCVTPH2QQ
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR 
PATTERN:    EVV 0x7B V66 MAP5 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn]  VL512  W0  NOEVSR 
OPERANDS:    REG0=ZMM_R3():w:zi64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f16
IFORM:       VCVTPH2QQ_ZMMi64_MASKmskw_XMMf16_AVX512
}

{
ICLASS:      VCVTPH2QQ
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR 
PATTERN:    EVV 0x7B V66 MAP5 MOD[0b11] MOD=3 BCRC=1 UBIT=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND()  W0  NOEVSR 
OPERANDS:    REG0=ZMM_R3():w:zi64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f16
IFORM:       VCVTPH2QQ_ZMMi64_MASKmskw_XMMf16_AVX512
}

{
ICLASS:      VCVTPH2QQ
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_QUARTER MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR 
PATTERN:    EVV 0x7B V66 MAP5 MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn]  MODRM()  VL512  W0  NOEVSR  ESIZE_16_BITS() NELEM_QUARTER() 
OPERANDS:    REG0=ZMM_R3():w:zi64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f16:TXT=BCASTSTR
IFORM:       VCVTPH2QQ_ZMMi64_MASKmskw_MEMf16_AVX512
}


# EMITTING VCVTPH2UDQ (VCVTPH2UDQ-128-1)
{
ICLASS:      VCVTPH2UDQ
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_128
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR 
PATTERN:    EVV 0x79 VNP MAP5 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn]  VL128  W0  NOEVSR 
OPERANDS:    REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f16
IFORM:       VCVTPH2UDQ_XMMu32_MASKmskw_XMMf16_AVX512
}

{
ICLASS:      VCVTPH2UDQ
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_128
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_HALF MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR 
PATTERN:    EVV 0x79 VNP MAP5 MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn]  MODRM()  VL128  W0  NOEVSR  ESIZE_16_BITS() NELEM_HALF() 
OPERANDS:    REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f16:TXT=BCASTSTR
IFORM:       VCVTPH2UDQ_XMMu32_MASKmskw_MEMf16_AVX512
}


# EMITTING VCVTPH2UDQ (VCVTPH2UDQ-256-1)
{
ICLASS:      VCVTPH2UDQ
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_256
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR 
PATTERN:    EVV 0x79 VNP MAP5 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn]  VL256  W0  NOEVSR 
OPERANDS:    REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f16
IFORM:       VCVTPH2UDQ_YMMu32_MASKmskw_XMMf16_AVX512
}

{
ICLASS:      VCVTPH2UDQ
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_256
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_HALF MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR 
PATTERN:    EVV 0x79 VNP MAP5 MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn]  MODRM()  VL256  W0  NOEVSR  ESIZE_16_BITS() NELEM_HALF() 
OPERANDS:    REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f16:TXT=BCASTSTR
IFORM:       VCVTPH2UDQ_YMMu32_MASKmskw_MEMf16_AVX512
}


# EMITTING VCVTPH2UDQ (VCVTPH2UDQ-512-1)
{
ICLASS:      VCVTPH2UDQ
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR 
PATTERN:    EVV 0x79 VNP MAP5 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn]  VL512  W0  NOEVSR 
OPERANDS:    REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f16
IFORM:       VCVTPH2UDQ_ZMMu32_MASKmskw_YMMf16_AVX512
}

{
ICLASS:      VCVTPH2UDQ
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR 
PATTERN:    EVV 0x79 VNP MAP5 MOD[0b11] MOD=3 BCRC=1 UBIT=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND()  W0  NOEVSR 
OPERANDS:    REG0=ZMM_R3():w:zu32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f16
IFORM:       VCVTPH2UDQ_ZMMu32_MASKmskw_YMMf16_AVX512
}

{
ICLASS:      VCVTPH2UDQ
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_HALF MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR 
PATTERN:    EVV 0x79 VNP MAP5 MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn]  MODRM()  VL512  W0  NOEVSR  ESIZE_16_BITS() NELEM_HALF() 
OPERANDS:    REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f16:TXT=BCASTSTR
IFORM:       VCVTPH2UDQ_ZMMu32_MASKmskw_MEMf16_AVX512
}


# EMITTING VCVTPH2UQQ (VCVTPH2UQQ-128-1)
{
ICLASS:      VCVTPH2UQQ
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_128
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR 
PATTERN:    EVV 0x79 V66 MAP5 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn]  VL128  W0  NOEVSR 
OPERANDS:    REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f16
IFORM:       VCVTPH2UQQ_XMMu64_MASKmskw_XMMf16_AVX512
}

{
ICLASS:      VCVTPH2UQQ
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_128
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_QUARTER MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR 
PATTERN:    EVV 0x79 V66 MAP5 MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn]  MODRM()  VL128  W0  NOEVSR  ESIZE_16_BITS() NELEM_QUARTER() 
OPERANDS:    REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f16:TXT=BCASTSTR
IFORM:       VCVTPH2UQQ_XMMu64_MASKmskw_MEMf16_AVX512
}


# EMITTING VCVTPH2UQQ (VCVTPH2UQQ-256-1)
{
ICLASS:      VCVTPH2UQQ
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_256
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR 
PATTERN:    EVV 0x79 V66 MAP5 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn]  VL256  W0  NOEVSR 
OPERANDS:    REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f16
IFORM:       VCVTPH2UQQ_YMMu64_MASKmskw_XMMf16_AVX512
}

{
ICLASS:      VCVTPH2UQQ
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_256
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_QUARTER MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR 
PATTERN:    EVV 0x79 V66 MAP5 MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn]  MODRM()  VL256  W0  NOEVSR  ESIZE_16_BITS() NELEM_QUARTER() 
OPERANDS:    REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f16:TXT=BCASTSTR
IFORM:       VCVTPH2UQQ_YMMu64_MASKmskw_MEMf16_AVX512
}


# EMITTING VCVTPH2UQQ (VCVTPH2UQQ-512-1)
{
ICLASS:      VCVTPH2UQQ
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR 
PATTERN:    EVV 0x79 V66 MAP5 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn]  VL512  W0  NOEVSR 
OPERANDS:    REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f16
IFORM:       VCVTPH2UQQ_ZMMu64_MASKmskw_XMMf16_AVX512
}

{
ICLASS:      VCVTPH2UQQ
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR 
PATTERN:    EVV 0x79 V66 MAP5 MOD[0b11] MOD=3 BCRC=1 UBIT=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND()  W0  NOEVSR 
OPERANDS:    REG0=ZMM_R3():w:zu64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f16
IFORM:       VCVTPH2UQQ_ZMMu64_MASKmskw_XMMf16_AVX512
}

{
ICLASS:      VCVTPH2UQQ
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_QUARTER MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR 
PATTERN:    EVV 0x79 V66 MAP5 MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn]  MODRM()  VL512  W0  NOEVSR  ESIZE_16_BITS() NELEM_QUARTER() 
OPERANDS:    REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f16:TXT=BCASTSTR
IFORM:       VCVTPH2UQQ_ZMMu64_MASKmskw_MEMf16_AVX512
}


# EMITTING VCVTPH2UW (VCVTPH2UW-128-1)
{
ICLASS:      VCVTPH2UW
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_128
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR 
PATTERN:    EVV 0x7D VNP MAP5 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn]  VL128  W0  NOEVSR 
OPERANDS:    REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f16
IFORM:       VCVTPH2UW_XMMu16_MASKmskw_XMMf16_AVX512
}

{
ICLASS:      VCVTPH2UW
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_128
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR 
PATTERN:    EVV 0x7D VNP MAP5 MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn]  MODRM()  VL128  W0  NOEVSR  ESIZE_16_BITS() NELEM_FULL() 
OPERANDS:    REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f16:TXT=BCASTSTR
IFORM:       VCVTPH2UW_XMMu16_MASKmskw_MEMf16_AVX512
}


# EMITTING VCVTPH2UW (VCVTPH2UW-256-1)
{
ICLASS:      VCVTPH2UW
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_256
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR 
PATTERN:    EVV 0x7D VNP MAP5 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn]  VL256  W0  NOEVSR 
OPERANDS:    REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f16
IFORM:       VCVTPH2UW_YMMu16_MASKmskw_YMMf16_AVX512
}

{
ICLASS:      VCVTPH2UW
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_256
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR 
PATTERN:    EVV 0x7D VNP MAP5 MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn]  MODRM()  VL256  W0  NOEVSR  ESIZE_16_BITS() NELEM_FULL() 
OPERANDS:    REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f16:TXT=BCASTSTR
IFORM:       VCVTPH2UW_YMMu16_MASKmskw_MEMf16_AVX512
}


# EMITTING VCVTPH2UW (VCVTPH2UW-512-1)
{
ICLASS:      VCVTPH2UW
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR 
PATTERN:    EVV 0x7D VNP MAP5 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn]  VL512  W0  NOEVSR 
OPERANDS:    REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf16
IFORM:       VCVTPH2UW_ZMMu16_MASKmskw_ZMMf16_AVX512
}

{
ICLASS:      VCVTPH2UW
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR 
PATTERN:    EVV 0x7D VNP MAP5 MOD[0b11] MOD=3 BCRC=1 UBIT=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND()  W0  NOEVSR 
OPERANDS:    REG0=ZMM_R3():w:zu16:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf16
IFORM:       VCVTPH2UW_ZMMu16_MASKmskw_ZMMf16_AVX512
}

{
ICLASS:      VCVTPH2UW
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR 
PATTERN:    EVV 0x7D VNP MAP5 MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn]  MODRM()  VL512  W0  NOEVSR  ESIZE_16_BITS() NELEM_FULL() 
OPERANDS:    REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f16:TXT=BCASTSTR
IFORM:       VCVTPH2UW_ZMMu16_MASKmskw_MEMf16_AVX512
}


# EMITTING VCVTPH2W (VCVTPH2W-128-1)
{
ICLASS:      VCVTPH2W
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_128
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR 
PATTERN:    EVV 0x7D V66 MAP5 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn]  VL128  W0  NOEVSR 
OPERANDS:    REG0=XMM_R3():w:dq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f16
IFORM:       VCVTPH2W_XMMi16_MASKmskw_XMMf16_AVX512
}

{
ICLASS:      VCVTPH2W
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_128
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR 
PATTERN:    EVV 0x7D V66 MAP5 MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn]  MODRM()  VL128  W0  NOEVSR  ESIZE_16_BITS() NELEM_FULL() 
OPERANDS:    REG0=XMM_R3():w:dq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f16:TXT=BCASTSTR
IFORM:       VCVTPH2W_XMMi16_MASKmskw_MEMf16_AVX512
}


# EMITTING VCVTPH2W (VCVTPH2W-256-1)
{
ICLASS:      VCVTPH2W
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_256
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR 
PATTERN:    EVV 0x7D V66 MAP5 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn]  VL256  W0  NOEVSR 
OPERANDS:    REG0=YMM_R3():w:qq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f16
IFORM:       VCVTPH2W_YMMi16_MASKmskw_YMMf16_AVX512
}

{
ICLASS:      VCVTPH2W
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_256
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR 
PATTERN:    EVV 0x7D V66 MAP5 MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn]  MODRM()  VL256  W0  NOEVSR  ESIZE_16_BITS() NELEM_FULL() 
OPERANDS:    REG0=YMM_R3():w:qq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f16:TXT=BCASTSTR
IFORM:       VCVTPH2W_YMMi16_MASKmskw_MEMf16_AVX512
}


# EMITTING VCVTPH2W (VCVTPH2W-512-1)
{
ICLASS:      VCVTPH2W
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR 
PATTERN:    EVV 0x7D V66 MAP5 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn]  VL512  W0  NOEVSR 
OPERANDS:    REG0=ZMM_R3():w:zi16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf16
IFORM:       VCVTPH2W_ZMMi16_MASKmskw_ZMMf16_AVX512
}

{
ICLASS:      VCVTPH2W
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR 
PATTERN:    EVV 0x7D V66 MAP5 MOD[0b11] MOD=3 BCRC=1 UBIT=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND()  W0  NOEVSR 
OPERANDS:    REG0=ZMM_R3():w:zi16:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf16
IFORM:       VCVTPH2W_ZMMi16_MASKmskw_ZMMf16_AVX512
}

{
ICLASS:      VCVTPH2W
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR 
PATTERN:    EVV 0x7D V66 MAP5 MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn]  MODRM()  VL512  W0  NOEVSR  ESIZE_16_BITS() NELEM_FULL() 
OPERANDS:    REG0=ZMM_R3():w:zi16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f16:TXT=BCASTSTR
IFORM:       VCVTPH2W_ZMMi16_MASKmskw_MEMf16_AVX512
}


# EMITTING VCVTPS2PHX (VCVTPS2PHX-128-1)
{
ICLASS:      VCVTPS2PHX
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_128
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR USES_DAZ 
PATTERN:    EVV 0x1D V66 MAP5 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn]  VL128  W0  NOEVSR 
OPERANDS:    REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f32
IFORM:       VCVTPS2PHX_XMMf16_MASKmskw_XMMf32_AVX512
}

{
ICLASS:      VCVTPS2PHX
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_128
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR USES_DAZ 
PATTERN:    EVV 0x1D V66 MAP5 MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn]  MODRM()  VL128  W0  NOEVSR  ESIZE_32_BITS() NELEM_FULL() 
OPERANDS:    REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR
IFORM:       VCVTPS2PHX_XMMf16_MASKmskw_MEMf32_AVX512_VL128
}


# EMITTING VCVTPS2PHX (VCVTPS2PHX-256-1)
{
ICLASS:      VCVTPS2PHX
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_256
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR USES_DAZ 
PATTERN:    EVV 0x1D V66 MAP5 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn]  VL256  W0  NOEVSR 
OPERANDS:    REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f32
IFORM:       VCVTPS2PHX_XMMf16_MASKmskw_YMMf32_AVX512
}

{
ICLASS:      VCVTPS2PHX
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_256
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR USES_DAZ 
PATTERN:    EVV 0x1D V66 MAP5 MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn]  MODRM()  VL256  W0  NOEVSR  ESIZE_32_BITS() NELEM_FULL() 
OPERANDS:    REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR
IFORM:       VCVTPS2PHX_XMMf16_MASKmskw_MEMf32_AVX512_VL256
}


# EMITTING VCVTPS2PHX (VCVTPS2PHX-512-1)
{
ICLASS:      VCVTPS2PHX
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR USES_DAZ 
PATTERN:    EVV 0x1D V66 MAP5 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn]  VL512  W0  NOEVSR 
OPERANDS:    REG0=YMM_R3():w:qq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf32
IFORM:       VCVTPS2PHX_YMMf16_MASKmskw_ZMMf32_AVX512
}

{
ICLASS:      VCVTPS2PHX
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR USES_DAZ 
PATTERN:    EVV 0x1D V66 MAP5 MOD[0b11] MOD=3 BCRC=1 UBIT=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND()  W0  NOEVSR 
OPERANDS:    REG0=YMM_R3():w:qq:f16:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf32
IFORM:       VCVTPS2PHX_YMMf16_MASKmskw_ZMMf32_AVX512
}

{
ICLASS:      VCVTPS2PHX
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR USES_DAZ 
PATTERN:    EVV 0x1D V66 MAP5 MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn]  MODRM()  VL512  W0  NOEVSR  ESIZE_32_BITS() NELEM_FULL() 
OPERANDS:    REG0=YMM_R3():w:qq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR
IFORM:       VCVTPS2PHX_YMMf16_MASKmskw_MEMf32_AVX512_VL512
}


# EMITTING VCVTQQ2PH (VCVTQQ2PH-128-1)
{
ICLASS:      VCVTQQ2PH
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_128
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR 
PATTERN:    EVV 0x5B VNP MAP5 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn]  VL128  W1  NOEVSR 
OPERANDS:    REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u64
IFORM:       VCVTQQ2PH_XMMf16_MASKmskw_XMMu64_AVX512
}

{
ICLASS:      VCVTQQ2PH
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_128
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR 
PATTERN:    EVV 0x5B VNP MAP5 MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn]  MODRM()  VL128  W1  NOEVSR  ESIZE_64_BITS() NELEM_FULL() 
OPERANDS:    REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u64:TXT=BCASTSTR
IFORM:       VCVTQQ2PH_XMMf16_MASKmskw_MEMu64_AVX512_VL128
}


# EMITTING VCVTQQ2PH (VCVTQQ2PH-256-1)
{
ICLASS:      VCVTQQ2PH
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_256
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR 
PATTERN:    EVV 0x5B VNP MAP5 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn]  VL256  W1  NOEVSR 
OPERANDS:    REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u64
IFORM:       VCVTQQ2PH_XMMf16_MASKmskw_YMMu64_AVX512
}

{
ICLASS:      VCVTQQ2PH
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_256
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR 
PATTERN:    EVV 0x5B VNP MAP5 MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn]  MODRM()  VL256  W1  NOEVSR  ESIZE_64_BITS() NELEM_FULL() 
OPERANDS:    REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u64:TXT=BCASTSTR
IFORM:       VCVTQQ2PH_XMMf16_MASKmskw_MEMu64_AVX512_VL256
}


# EMITTING VCVTQQ2PH (VCVTQQ2PH-512-1)
{
ICLASS:      VCVTQQ2PH
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR 
PATTERN:    EVV 0x5B VNP MAP5 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn]  VL512  W1  NOEVSR 
OPERANDS:    REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu64
IFORM:       VCVTQQ2PH_XMMf16_MASKmskw_ZMMu64_AVX512
}

{
ICLASS:      VCVTQQ2PH
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR 
PATTERN:    EVV 0x5B VNP MAP5 MOD[0b11] MOD=3 BCRC=1 UBIT=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND()  W1  NOEVSR 
OPERANDS:    REG0=XMM_R3():w:dq:f16:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu64
IFORM:       VCVTQQ2PH_XMMf16_MASKmskw_ZMMu64_AVX512
}

{
ICLASS:      VCVTQQ2PH
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR 
PATTERN:    EVV 0x5B VNP MAP5 MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn]  MODRM()  VL512  W1  NOEVSR  ESIZE_64_BITS() NELEM_FULL() 
OPERANDS:    REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u64:TXT=BCASTSTR
IFORM:       VCVTQQ2PH_XMMf16_MASKmskw_MEMu64_AVX512_VL512
}


# EMITTING VCVTSD2SH (VCVTSD2SH-128-1)
{
ICLASS:      VCVTSD2SH
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_SCALAR
EXCEPTIONS:     AVX512-E3
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR SIMD_SCALAR USES_DAZ 
PATTERN:    EVV 0x5A VF2 MAP5 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn]  FIX_ROUND_LEN128() W1   
OPERANDS:    REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64
IFORM:       VCVTSD2SH_XMMf16_MASKmskw_XMMf64_XMMf64_AVX512
}

{
ICLASS:      VCVTSD2SH
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_SCALAR
EXCEPTIONS:     AVX512-E3
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR SIMD_SCALAR USES_DAZ 
PATTERN:    EVV 0x5A VF2 MAP5 MOD[0b11] MOD=3 BCRC=1 UBIT=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND()  W1   
OPERANDS:    REG0=XMM_R3():w:dq:f16:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64
IFORM:       VCVTSD2SH_XMMf16_MASKmskw_XMMf64_XMMf64_AVX512
}

{
ICLASS:      VCVTSD2SH
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_SCALAR
EXCEPTIONS:     AVX512-E3
REAL_OPCODE: Y
ATTRIBUTES:  DISP8_SCALAR MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR SIMD_SCALAR USES_DAZ 
PATTERN:    EVV 0x5A VF2 MAP5 MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn] BCRC=0 MODRM()  FIX_ROUND_LEN128() W1    ESIZE_64_BITS() NELEM_SCALAR() 
OPERANDS:    REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:q:f64
IFORM:       VCVTSD2SH_XMMf16_MASKmskw_XMMf64_MEMf64_AVX512
}


# EMITTING VCVTSH2SD (VCVTSH2SD-128-1)
{
ICLASS:      VCVTSH2SD
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_SCALAR
EXCEPTIONS:     AVX512-E3
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR SIMD_SCALAR USES_FTZ 
PATTERN:    EVV 0x5A VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn]  FIX_ROUND_LEN128() W0   
OPERANDS:    REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f16
IFORM:       VCVTSH2SD_XMMf64_MASKmskw_XMMf64_XMMf16_AVX512
}

{
ICLASS:      VCVTSH2SD
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_SCALAR
EXCEPTIONS:     AVX512-E3
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR SIMD_SCALAR USES_FTZ 
PATTERN:    EVV 0x5A VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 UBIT=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE()  W0   
OPERANDS:    REG0=XMM_R3():w:dq:f64:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f16
IFORM:       VCVTSH2SD_XMMf64_MASKmskw_XMMf64_XMMf16_AVX512
}

{
ICLASS:      VCVTSH2SD
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_SCALAR
EXCEPTIONS:     AVX512-E3
REAL_OPCODE: Y
ATTRIBUTES:  DISP8_SCALAR MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR SIMD_SCALAR USES_FTZ 
PATTERN:    EVV 0x5A VF3 MAP5 MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn] BCRC=0 MODRM()  FIX_ROUND_LEN128() W0    ESIZE_16_BITS() NELEM_SCALAR() 
OPERANDS:    REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:wrd:f16
IFORM:       VCVTSH2SD_XMMf64_MASKmskw_XMMf64_MEMf16_AVX512
}


# EMITTING VCVTSH2SI (VCVTSH2SI-128-1-mode64)
{
ICLASS:      VCVTSH2SI
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_SCALAR
EXCEPTIONS:     AVX512-E3NF
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR SIMD_SCALAR 
PATTERN:    EVV 0x2D VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn]  FIX_ROUND_LEN128() W0  mode64  NOEVSR  ZEROING=0 MASK=0 EVEXR4_ONE() 
OPERANDS:    REG0=GPR32_R():w:d:i32 REG1=XMM_B3():r:dq:f16
IFORM:       VCVTSH2SI_GPR32i32_XMMf16_AVX512
}

{
ICLASS:      VCVTSH2SI
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_SCALAR
EXCEPTIONS:     AVX512-E3NF
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR SIMD_SCALAR 
PATTERN:    EVV 0x2D VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 UBIT=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND()  W0  mode64  NOEVSR  ZEROING=0 MASK=0 EVEXR4_ONE() 
OPERANDS:    REG0=GPR32_R():w:d:i32:TXT=ROUNDC REG1=XMM_B3():r:dq:f16
IFORM:       VCVTSH2SI_GPR32i32_XMMf16_AVX512
}

{
ICLASS:      VCVTSH2SI
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_SCALAR
EXCEPTIONS:     AVX512-E3NF
REAL_OPCODE: Y
ATTRIBUTES:  DISP8_GPR_WRITER_LDOP_D MXCSR SIMD_SCALAR 
PATTERN:    EVV 0x2D VF3 MAP5 MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn] BCRC=0 MODRM()  FIX_ROUND_LEN128() W0  mode64  NOEVSR  ZEROING=0 MASK=0  ESIZE_16_BITS() NELEM_GPR_WRITER_LDOP_D() EVEXR4_ONE() 
OPERANDS:    REG0=GPR32_R():w:d:i32 MEM0:r:wrd:f16
IFORM:       VCVTSH2SI_GPR32i32_MEMf16_AVX512
}


# EMITTING VCVTSH2SI (VCVTSH2SI-128-1-not64)
{
ICLASS:      VCVTSH2SI
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_SCALAR
EXCEPTIONS:     AVX512-E3NF
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR SIMD_SCALAR 
PATTERN:    EVV 0x2D VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn]  FIX_ROUND_LEN128()   not64  NOEVSR  ZEROING=0 MASK=0 EVEXR4_ONE() 
OPERANDS:    REG0=GPR32_R():w:d:i32 REG1=XMM_B3():r:dq:f16
IFORM:       VCVTSH2SI_GPR32i32_XMMf16_AVX512
}

{
ICLASS:      VCVTSH2SI
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_SCALAR
EXCEPTIONS:     AVX512-E3NF
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR SIMD_SCALAR 
PATTERN:    EVV 0x2D VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 UBIT=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND()    not64  NOEVSR  ZEROING=0 MASK=0 EVEXR4_ONE() 
OPERANDS:    REG0=GPR32_R():w:d:i32:TXT=ROUNDC REG1=XMM_B3():r:dq:f16
IFORM:       VCVTSH2SI_GPR32i32_XMMf16_AVX512
}

{
ICLASS:      VCVTSH2SI
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_SCALAR
EXCEPTIONS:     AVX512-E3NF
REAL_OPCODE: Y
ATTRIBUTES:  DISP8_GPR_WRITER_LDOP_D MXCSR SIMD_SCALAR 
PATTERN:    EVV 0x2D VF3 MAP5 MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn] BCRC=0 MODRM()  FIX_ROUND_LEN128()   not64  NOEVSR  ZEROING=0 MASK=0  ESIZE_16_BITS() NELEM_GPR_WRITER_LDOP_D() EVEXR4_ONE() 
OPERANDS:    REG0=GPR32_R():w:d:i32 MEM0:r:wrd:f16
IFORM:       VCVTSH2SI_GPR32i32_MEMf16_AVX512
}


# EMITTING VCVTSH2SI (VCVTSH2SI-128-2)
{
ICLASS:      VCVTSH2SI
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_SCALAR
EXCEPTIONS:     AVX512-E3NF
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR SIMD_SCALAR 
PATTERN:    EVV 0x2D VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn]  FIX_ROUND_LEN128() W1  mode64  NOEVSR  ZEROING=0 MASK=0 EVEXR4_ONE() 
OPERANDS:    REG0=GPR64_R():w:q:i64 REG1=XMM_B3():r:dq:f16
IFORM:       VCVTSH2SI_GPR64i64_XMMf16_AVX512
}

{
ICLASS:      VCVTSH2SI
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_SCALAR
EXCEPTIONS:     AVX512-E3NF
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR SIMD_SCALAR 
PATTERN:    EVV 0x2D VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 UBIT=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND()  W1  mode64  NOEVSR  ZEROING=0 MASK=0 EVEXR4_ONE() 
OPERANDS:    REG0=GPR64_R():w:q:i64:TXT=ROUNDC REG1=XMM_B3():r:dq:f16
IFORM:       VCVTSH2SI_GPR64i64_XMMf16_AVX512
}

{
ICLASS:      VCVTSH2SI
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_SCALAR
EXCEPTIONS:     AVX512-E3NF
REAL_OPCODE: Y
ATTRIBUTES:  DISP8_GPR_WRITER_LDOP_D MXCSR SIMD_SCALAR 
PATTERN:    EVV 0x2D VF3 MAP5 MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn] BCRC=0 MODRM()  FIX_ROUND_LEN128() W1  mode64  NOEVSR  ZEROING=0 MASK=0  ESIZE_16_BITS() NELEM_GPR_WRITER_LDOP_D() EVEXR4_ONE() 
OPERANDS:    REG0=GPR64_R():w:q:i64 MEM0:r:wrd:f16
IFORM:       VCVTSH2SI_GPR64i64_MEMf16_AVX512
}


# EMITTING VCVTSH2SS (VCVTSH2SS-128-1)
{
ICLASS:      VCVTSH2SS
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_SCALAR
EXCEPTIONS:     AVX512-E3
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR SIMD_SCALAR USES_FTZ 
PATTERN:    EVV 0x13 VNP MAP6 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn]  FIX_ROUND_LEN128() W0   
OPERANDS:    REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f16
IFORM:       VCVTSH2SS_XMMf32_MASKmskw_XMMf32_XMMf16_AVX512
}

{
ICLASS:      VCVTSH2SS
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_SCALAR
EXCEPTIONS:     AVX512-E3
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR SIMD_SCALAR USES_FTZ 
PATTERN:    EVV 0x13 VNP MAP6 MOD[0b11] MOD=3 BCRC=1 UBIT=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE()  W0   
OPERANDS:    REG0=XMM_R3():w:dq:f32:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f16
IFORM:       VCVTSH2SS_XMMf32_MASKmskw_XMMf32_XMMf16_AVX512
}

{
ICLASS:      VCVTSH2SS
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_SCALAR
EXCEPTIONS:     AVX512-E3
REAL_OPCODE: Y
ATTRIBUTES:  DISP8_SCALAR MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR SIMD_SCALAR USES_FTZ 
PATTERN:    EVV 0x13 VNP MAP6 MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn] BCRC=0 MODRM()  FIX_ROUND_LEN128() W0    ESIZE_16_BITS() NELEM_SCALAR() 
OPERANDS:    REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:wrd:f16
IFORM:       VCVTSH2SS_XMMf32_MASKmskw_XMMf32_MEMf16_AVX512
}


# EMITTING VCVTSH2USI (VCVTSH2USI-128-1-mode64)
{
ICLASS:      VCVTSH2USI
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_SCALAR
EXCEPTIONS:     AVX512-E3NF
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR SIMD_SCALAR 
PATTERN:    EVV 0x79 VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn]  FIX_ROUND_LEN128() W0  mode64  NOEVSR  ZEROING=0 MASK=0 EVEXR4_ONE() 
OPERANDS:    REG0=GPR32_R():w:d:u32 REG1=XMM_B3():r:dq:f16
IFORM:       VCVTSH2USI_GPR32u32_XMMf16_AVX512
}

{
ICLASS:      VCVTSH2USI
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_SCALAR
EXCEPTIONS:     AVX512-E3NF
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR SIMD_SCALAR 
PATTERN:    EVV 0x79 VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 UBIT=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND()  W0  mode64  NOEVSR  ZEROING=0 MASK=0 EVEXR4_ONE() 
OPERANDS:    REG0=GPR32_R():w:d:u32:TXT=ROUNDC REG1=XMM_B3():r:dq:f16
IFORM:       VCVTSH2USI_GPR32u32_XMMf16_AVX512
}

{
ICLASS:      VCVTSH2USI
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_SCALAR
EXCEPTIONS:     AVX512-E3NF
REAL_OPCODE: Y
ATTRIBUTES:  DISP8_GPR_WRITER_LDOP_D MXCSR SIMD_SCALAR 
PATTERN:    EVV 0x79 VF3 MAP5 MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn] BCRC=0 MODRM()  FIX_ROUND_LEN128() W0  mode64  NOEVSR  ZEROING=0 MASK=0  ESIZE_16_BITS() NELEM_GPR_WRITER_LDOP_D() EVEXR4_ONE() 
OPERANDS:    REG0=GPR32_R():w:d:u32 MEM0:r:wrd:f16
IFORM:       VCVTSH2USI_GPR32u32_MEMf16_AVX512
}


# EMITTING VCVTSH2USI (VCVTSH2USI-128-1-not64)
{
ICLASS:      VCVTSH2USI
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_SCALAR
EXCEPTIONS:     AVX512-E3NF
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR SIMD_SCALAR 
PATTERN:    EVV 0x79 VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn]  FIX_ROUND_LEN128()   not64  NOEVSR  ZEROING=0 MASK=0 EVEXR4_ONE() 
OPERANDS:    REG0=GPR32_R():w:d:u32 REG1=XMM_B3():r:dq:f16
IFORM:       VCVTSH2USI_GPR32u32_XMMf16_AVX512
}

{
ICLASS:      VCVTSH2USI
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_SCALAR
EXCEPTIONS:     AVX512-E3NF
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR SIMD_SCALAR 
PATTERN:    EVV 0x79 VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 UBIT=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND()    not64  NOEVSR  ZEROING=0 MASK=0 EVEXR4_ONE() 
OPERANDS:    REG0=GPR32_R():w:d:u32:TXT=ROUNDC REG1=XMM_B3():r:dq:f16
IFORM:       VCVTSH2USI_GPR32u32_XMMf16_AVX512
}

{
ICLASS:      VCVTSH2USI
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_SCALAR
EXCEPTIONS:     AVX512-E3NF
REAL_OPCODE: Y
ATTRIBUTES:  DISP8_GPR_WRITER_LDOP_D MXCSR SIMD_SCALAR 
PATTERN:    EVV 0x79 VF3 MAP5 MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn] BCRC=0 MODRM()  FIX_ROUND_LEN128()   not64  NOEVSR  ZEROING=0 MASK=0  ESIZE_16_BITS() NELEM_GPR_WRITER_LDOP_D() EVEXR4_ONE() 
OPERANDS:    REG0=GPR32_R():w:d:u32 MEM0:r:wrd:f16
IFORM:       VCVTSH2USI_GPR32u32_MEMf16_AVX512
}


# EMITTING VCVTSH2USI (VCVTSH2USI-128-2)
{
ICLASS:      VCVTSH2USI
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_SCALAR
EXCEPTIONS:     AVX512-E3NF
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR SIMD_SCALAR 
PATTERN:    EVV 0x79 VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn]  FIX_ROUND_LEN128() W1  mode64  NOEVSR  ZEROING=0 MASK=0 EVEXR4_ONE() 
OPERANDS:    REG0=GPR64_R():w:q:u64 REG1=XMM_B3():r:dq:f16
IFORM:       VCVTSH2USI_GPR64u64_XMMf16_AVX512
}

{
ICLASS:      VCVTSH2USI
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_SCALAR
EXCEPTIONS:     AVX512-E3NF
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR SIMD_SCALAR 
PATTERN:    EVV 0x79 VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 UBIT=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND()  W1  mode64  NOEVSR  ZEROING=0 MASK=0 EVEXR4_ONE() 
OPERANDS:    REG0=GPR64_R():w:q:u64:TXT=ROUNDC REG1=XMM_B3():r:dq:f16
IFORM:       VCVTSH2USI_GPR64u64_XMMf16_AVX512
}

{
ICLASS:      VCVTSH2USI
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_SCALAR
EXCEPTIONS:     AVX512-E3NF
REAL_OPCODE: Y
ATTRIBUTES:  DISP8_GPR_WRITER_LDOP_D MXCSR SIMD_SCALAR 
PATTERN:    EVV 0x79 VF3 MAP5 MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn] BCRC=0 MODRM()  FIX_ROUND_LEN128() W1  mode64  NOEVSR  ZEROING=0 MASK=0  ESIZE_16_BITS() NELEM_GPR_WRITER_LDOP_D() EVEXR4_ONE() 
OPERANDS:    REG0=GPR64_R():w:q:u64 MEM0:r:wrd:f16
IFORM:       VCVTSH2USI_GPR64u64_MEMf16_AVX512
}


# EMITTING VCVTSI2SH (VCVTSI2SH-128-1-mode64)
{
ICLASS:      VCVTSI2SH
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_SCALAR
EXCEPTIONS:     AVX512-E3NF
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR SIMD_SCALAR 
PATTERN:    EVV 0x2A VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn]  FIX_ROUND_LEN128() W0  mode64    ZEROING=0 MASK=0 
OPERANDS:    REG0=XMM_R3():w:dq:f16 REG1=XMM_N3():r:dq:f16 REG2=GPR32_B():r:d:i32
IFORM:       VCVTSI2SH_XMMf16_XMMf16_GPR32i32_AVX512
}

{
ICLASS:      VCVTSI2SH
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_SCALAR
EXCEPTIONS:     AVX512-E3NF
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR SIMD_SCALAR 
PATTERN:    EVV 0x2A VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 UBIT=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND()  W0  mode64    ZEROING=0 MASK=0 
OPERANDS:    REG0=XMM_R3():w:dq:f16:TXT=ROUNDC REG1=XMM_N3():r:dq:f16 REG2=GPR32_B():r:d:i32
IFORM:       VCVTSI2SH_XMMf16_XMMf16_GPR32i32_AVX512
}

{
ICLASS:      VCVTSI2SH
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_SCALAR
EXCEPTIONS:     AVX512-E3NF
REAL_OPCODE: Y
ATTRIBUTES:  DISP8_GPR_READER MXCSR SIMD_SCALAR 
PATTERN:    EVV 0x2A VF3 MAP5 MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn] BCRC=0 MODRM()  FIX_ROUND_LEN128() W0  mode64    ZEROING=0 MASK=0  ESIZE_32_BITS() NELEM_GPR_READER() 
OPERANDS:    REG0=XMM_R3():w:dq:f16 REG1=XMM_N3():r:dq:f16 MEM0:r:d:i32
IFORM:       VCVTSI2SH_XMMf16_XMMf16_MEMi32_AVX512
}


# EMITTING VCVTSI2SH (VCVTSI2SH-128-1-not64)
{
ICLASS:      VCVTSI2SH
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_SCALAR
EXCEPTIONS:     AVX512-E3NF
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR SIMD_SCALAR 
PATTERN:    EVV 0x2A VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn]  FIX_ROUND_LEN128()   not64    ZEROING=0 MASK=0 
OPERANDS:    REG0=XMM_R3():w:dq:f16 REG1=XMM_N3():r:dq:f16 REG2=GPR32_B():r:d:i32
IFORM:       VCVTSI2SH_XMMf16_XMMf16_GPR32i32_AVX512
}

{
ICLASS:      VCVTSI2SH
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_SCALAR
EXCEPTIONS:     AVX512-E3NF
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR SIMD_SCALAR 
PATTERN:    EVV 0x2A VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 UBIT=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND()    not64    ZEROING=0 MASK=0 
OPERANDS:    REG0=XMM_R3():w:dq:f16:TXT=ROUNDC REG1=XMM_N3():r:dq:f16 REG2=GPR32_B():r:d:i32
IFORM:       VCVTSI2SH_XMMf16_XMMf16_GPR32i32_AVX512
}

{
ICLASS:      VCVTSI2SH
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_SCALAR
EXCEPTIONS:     AVX512-E3NF
REAL_OPCODE: Y
ATTRIBUTES:  DISP8_GPR_READER MXCSR SIMD_SCALAR 
PATTERN:    EVV 0x2A VF3 MAP5 MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn] BCRC=0 MODRM()  FIX_ROUND_LEN128()   not64    ZEROING=0 MASK=0  ESIZE_32_BITS() NELEM_GPR_READER() 
OPERANDS:    REG0=XMM_R3():w:dq:f16 REG1=XMM_N3():r:dq:f16 MEM0:r:d:i32
IFORM:       VCVTSI2SH_XMMf16_XMMf16_MEMi32_AVX512
}


# EMITTING VCVTSI2SH (VCVTSI2SH-128-2)
{
ICLASS:      VCVTSI2SH
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_SCALAR
EXCEPTIONS:     AVX512-E3NF
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR SIMD_SCALAR 
PATTERN:    EVV 0x2A VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn]  FIX_ROUND_LEN128() W1  mode64    ZEROING=0 MASK=0 
OPERANDS:    REG0=XMM_R3():w:dq:f16 REG1=XMM_N3():r:dq:f16 REG2=GPR64_B():r:q:i64
IFORM:       VCVTSI2SH_XMMf16_XMMf16_GPR64i64_AVX512
}

{
ICLASS:      VCVTSI2SH
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_SCALAR
EXCEPTIONS:     AVX512-E3NF
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR SIMD_SCALAR 
PATTERN:    EVV 0x2A VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 UBIT=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND()  W1  mode64    ZEROING=0 MASK=0
OPERANDS:    REG0=XMM_R3():w:dq:f16:TXT=ROUNDC REG1=XMM_N3():r:dq:f16 REG2=GPR64_B():r:q:i64
IFORM:       VCVTSI2SH_XMMf16_XMMf16_GPR64i64_AVX512
}

{
ICLASS:      VCVTSI2SH
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_SCALAR
EXCEPTIONS:     AVX512-E3NF
REAL_OPCODE: Y
ATTRIBUTES:  DISP8_GPR_READER MXCSR SIMD_SCALAR 
PATTERN:    EVV 0x2A VF3 MAP5 MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn] BCRC=0 MODRM()  FIX_ROUND_LEN128() W1  mode64    ZEROING=0 MASK=0  ESIZE_64_BITS() NELEM_GPR_READER() 
OPERANDS:    REG0=XMM_R3():w:dq:f16 REG1=XMM_N3():r:dq:f16 MEM0:r:q:i64
IFORM:       VCVTSI2SH_XMMf16_XMMf16_MEMi64_AVX512
}


# EMITTING VCVTSS2SH (VCVTSS2SH-128-1)
{
ICLASS:      VCVTSS2SH
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_SCALAR
EXCEPTIONS:     AVX512-E3
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR SIMD_SCALAR USES_DAZ 
PATTERN:    EVV 0x1D VNP MAP5 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn]  FIX_ROUND_LEN128() W0   
OPERANDS:    REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 REG3=XMM_B3():r:dq:f32
IFORM:       VCVTSS2SH_XMMf16_MASKmskw_XMMf16_XMMf32_AVX512
}

{
ICLASS:      VCVTSS2SH
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_SCALAR
EXCEPTIONS:     AVX512-E3
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR SIMD_SCALAR USES_DAZ 
PATTERN:    EVV 0x1D VNP MAP5 MOD[0b11] MOD=3 BCRC=1 UBIT=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND()  W0   
OPERANDS:    REG0=XMM_R3():w:dq:f16:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 REG3=XMM_B3():r:dq:f32
IFORM:       VCVTSS2SH_XMMf16_MASKmskw_XMMf16_XMMf32_AVX512
}

{
ICLASS:      VCVTSS2SH
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_SCALAR
EXCEPTIONS:     AVX512-E3
REAL_OPCODE: Y
ATTRIBUTES:  DISP8_SCALAR MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR SIMD_SCALAR USES_DAZ 
PATTERN:    EVV 0x1D VNP MAP5 MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn] BCRC=0 MODRM()  FIX_ROUND_LEN128() W0    ESIZE_32_BITS() NELEM_SCALAR() 
OPERANDS:    REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 MEM0:r:d:f32
IFORM:       VCVTSS2SH_XMMf16_MASKmskw_XMMf16_MEMf32_AVX512
}


# EMITTING VCVTTPH2DQ (VCVTTPH2DQ-128-1)
{
ICLASS:      VCVTTPH2DQ
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_128
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR 
PATTERN:    EVV 0x5B VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn]  VL128  W0  NOEVSR 
OPERANDS:    REG0=XMM_R3():w:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f16
IFORM:       VCVTTPH2DQ_XMMi32_MASKmskw_XMMf16_AVX512
}

{
ICLASS:      VCVTTPH2DQ
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_128
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_HALF MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR 
PATTERN:    EVV 0x5B VF3 MAP5 MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn]  MODRM()  VL128  W0  NOEVSR  ESIZE_16_BITS() NELEM_HALF() 
OPERANDS:    REG0=XMM_R3():w:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f16:TXT=BCASTSTR
IFORM:       VCVTTPH2DQ_XMMi32_MASKmskw_MEMf16_AVX512
}


# EMITTING VCVTTPH2DQ (VCVTTPH2DQ-256-1)
{
ICLASS:      VCVTTPH2DQ
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_256
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR 
PATTERN:    EVV 0x5B VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn]  VL256  W0  NOEVSR 
OPERANDS:    REG0=YMM_R3():w:qq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f16
IFORM:       VCVTTPH2DQ_YMMi32_MASKmskw_XMMf16_AVX512
}

{
ICLASS:      VCVTTPH2DQ
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_256
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_HALF MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR 
PATTERN:    EVV 0x5B VF3 MAP5 MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn]  MODRM()  VL256  W0  NOEVSR  ESIZE_16_BITS() NELEM_HALF() 
OPERANDS:    REG0=YMM_R3():w:qq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f16:TXT=BCASTSTR
IFORM:       VCVTTPH2DQ_YMMi32_MASKmskw_MEMf16_AVX512
}


# EMITTING VCVTTPH2DQ (VCVTTPH2DQ-512-1)
{
ICLASS:      VCVTTPH2DQ
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR 
PATTERN:    EVV 0x5B VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn]  VL512  W0  NOEVSR 
OPERANDS:    REG0=ZMM_R3():w:zi32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f16
IFORM:       VCVTTPH2DQ_ZMMi32_MASKmskw_YMMf16_AVX512
}

{
ICLASS:      VCVTTPH2DQ
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR 
PATTERN:    EVV 0x5B VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 UBIT=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE()  W0  NOEVSR 
OPERANDS:    REG0=ZMM_R3():w:zi32:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f16
IFORM:       VCVTTPH2DQ_ZMMi32_MASKmskw_YMMf16_AVX512
}

{
ICLASS:      VCVTTPH2DQ
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_HALF MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR 
PATTERN:    EVV 0x5B VF3 MAP5 MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn]  MODRM()  VL512  W0  NOEVSR  ESIZE_16_BITS() NELEM_HALF() 
OPERANDS:    REG0=ZMM_R3():w:zi32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f16:TXT=BCASTSTR
IFORM:       VCVTTPH2DQ_ZMMi32_MASKmskw_MEMf16_AVX512
}


# EMITTING VCVTTPH2QQ (VCVTTPH2QQ-128-1)
{
ICLASS:      VCVTTPH2QQ
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_128
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR 
PATTERN:    EVV 0x7A V66 MAP5 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn]  VL128  W0  NOEVSR 
OPERANDS:    REG0=XMM_R3():w:dq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f16
IFORM:       VCVTTPH2QQ_XMMi64_MASKmskw_XMMf16_AVX512
}

{
ICLASS:      VCVTTPH2QQ
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_128
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_QUARTER MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR 
PATTERN:    EVV 0x7A V66 MAP5 MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn]  MODRM()  VL128  W0  NOEVSR  ESIZE_16_BITS() NELEM_QUARTER() 
OPERANDS:    REG0=XMM_R3():w:dq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f16:TXT=BCASTSTR
IFORM:       VCVTTPH2QQ_XMMi64_MASKmskw_MEMf16_AVX512
}


# EMITTING VCVTTPH2QQ (VCVTTPH2QQ-256-1)
{
ICLASS:      VCVTTPH2QQ
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_256
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR 
PATTERN:    EVV 0x7A V66 MAP5 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn]  VL256  W0  NOEVSR 
OPERANDS:    REG0=YMM_R3():w:qq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f16
IFORM:       VCVTTPH2QQ_YMMi64_MASKmskw_XMMf16_AVX512
}

{
ICLASS:      VCVTTPH2QQ
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_256
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_QUARTER MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR 
PATTERN:    EVV 0x7A V66 MAP5 MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn]  MODRM()  VL256  W0  NOEVSR  ESIZE_16_BITS() NELEM_QUARTER() 
OPERANDS:    REG0=YMM_R3():w:qq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f16:TXT=BCASTSTR
IFORM:       VCVTTPH2QQ_YMMi64_MASKmskw_MEMf16_AVX512
}


# EMITTING VCVTTPH2QQ (VCVTTPH2QQ-512-1)
{
ICLASS:      VCVTTPH2QQ
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR 
PATTERN:    EVV 0x7A V66 MAP5 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn]  VL512  W0  NOEVSR 
OPERANDS:    REG0=ZMM_R3():w:zi64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f16
IFORM:       VCVTTPH2QQ_ZMMi64_MASKmskw_XMMf16_AVX512
}

{
ICLASS:      VCVTTPH2QQ
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR 
PATTERN:    EVV 0x7A V66 MAP5 MOD[0b11] MOD=3 BCRC=1 UBIT=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE()  W0  NOEVSR 
OPERANDS:    REG0=ZMM_R3():w:zi64:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f16
IFORM:       VCVTTPH2QQ_ZMMi64_MASKmskw_XMMf16_AVX512
}

{
ICLASS:      VCVTTPH2QQ
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_QUARTER MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR 
PATTERN:    EVV 0x7A V66 MAP5 MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn]  MODRM()  VL512  W0  NOEVSR  ESIZE_16_BITS() NELEM_QUARTER() 
OPERANDS:    REG0=ZMM_R3():w:zi64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f16:TXT=BCASTSTR
IFORM:       VCVTTPH2QQ_ZMMi64_MASKmskw_MEMf16_AVX512
}


# EMITTING VCVTTPH2UDQ (VCVTTPH2UDQ-128-1)
{
ICLASS:      VCVTTPH2UDQ
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_128
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR 
PATTERN:    EVV 0x78 VNP MAP5 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn]  VL128  W0  NOEVSR 
OPERANDS:    REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f16
IFORM:       VCVTTPH2UDQ_XMMu32_MASKmskw_XMMf16_AVX512
}

{
ICLASS:      VCVTTPH2UDQ
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_128
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_HALF MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR 
PATTERN:    EVV 0x78 VNP MAP5 MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn]  MODRM()  VL128  W0  NOEVSR  ESIZE_16_BITS() NELEM_HALF() 
OPERANDS:    REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f16:TXT=BCASTSTR
IFORM:       VCVTTPH2UDQ_XMMu32_MASKmskw_MEMf16_AVX512
}


# EMITTING VCVTTPH2UDQ (VCVTTPH2UDQ-256-1)
{
ICLASS:      VCVTTPH2UDQ
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_256
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR 
PATTERN:    EVV 0x78 VNP MAP5 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn]  VL256  W0  NOEVSR 
OPERANDS:    REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f16
IFORM:       VCVTTPH2UDQ_YMMu32_MASKmskw_XMMf16_AVX512
}

{
ICLASS:      VCVTTPH2UDQ
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_256
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_HALF MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR 
PATTERN:    EVV 0x78 VNP MAP5 MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn]  MODRM()  VL256  W0  NOEVSR  ESIZE_16_BITS() NELEM_HALF() 
OPERANDS:    REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f16:TXT=BCASTSTR
IFORM:       VCVTTPH2UDQ_YMMu32_MASKmskw_MEMf16_AVX512
}


# EMITTING VCVTTPH2UDQ (VCVTTPH2UDQ-512-1)
{
ICLASS:      VCVTTPH2UDQ
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR 
PATTERN:    EVV 0x78 VNP MAP5 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn]  VL512  W0  NOEVSR 
OPERANDS:    REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f16
IFORM:       VCVTTPH2UDQ_ZMMu32_MASKmskw_YMMf16_AVX512
}

{
ICLASS:      VCVTTPH2UDQ
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR 
PATTERN:    EVV 0x78 VNP MAP5 MOD[0b11] MOD=3 BCRC=1 UBIT=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE()  W0  NOEVSR 
OPERANDS:    REG0=ZMM_R3():w:zu32:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f16
IFORM:       VCVTTPH2UDQ_ZMMu32_MASKmskw_YMMf16_AVX512
}

{
ICLASS:      VCVTTPH2UDQ
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_HALF MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR 
PATTERN:    EVV 0x78 VNP MAP5 MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn]  MODRM()  VL512  W0  NOEVSR  ESIZE_16_BITS() NELEM_HALF() 
OPERANDS:    REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f16:TXT=BCASTSTR
IFORM:       VCVTTPH2UDQ_ZMMu32_MASKmskw_MEMf16_AVX512
}


# EMITTING VCVTTPH2UQQ (VCVTTPH2UQQ-128-1)
{
ICLASS:      VCVTTPH2UQQ
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_128
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR 
PATTERN:    EVV 0x78 V66 MAP5 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn]  VL128  W0  NOEVSR 
OPERANDS:    REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f16
IFORM:       VCVTTPH2UQQ_XMMu64_MASKmskw_XMMf16_AVX512
}

{
ICLASS:      VCVTTPH2UQQ
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_128
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_QUARTER MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR 
PATTERN:    EVV 0x78 V66 MAP5 MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn]  MODRM()  VL128  W0  NOEVSR  ESIZE_16_BITS() NELEM_QUARTER() 
OPERANDS:    REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f16:TXT=BCASTSTR
IFORM:       VCVTTPH2UQQ_XMMu64_MASKmskw_MEMf16_AVX512
}


# EMITTING VCVTTPH2UQQ (VCVTTPH2UQQ-256-1)
{
ICLASS:      VCVTTPH2UQQ
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_256
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR 
PATTERN:    EVV 0x78 V66 MAP5 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn]  VL256  W0  NOEVSR 
OPERANDS:    REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f16
IFORM:       VCVTTPH2UQQ_YMMu64_MASKmskw_XMMf16_AVX512
}

{
ICLASS:      VCVTTPH2UQQ
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_256
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_QUARTER MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR 
PATTERN:    EVV 0x78 V66 MAP5 MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn]  MODRM()  VL256  W0  NOEVSR  ESIZE_16_BITS() NELEM_QUARTER() 
OPERANDS:    REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f16:TXT=BCASTSTR
IFORM:       VCVTTPH2UQQ_YMMu64_MASKmskw_MEMf16_AVX512
}


# EMITTING VCVTTPH2UQQ (VCVTTPH2UQQ-512-1)
{
ICLASS:      VCVTTPH2UQQ
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR 
PATTERN:    EVV 0x78 V66 MAP5 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn]  VL512  W0  NOEVSR 
OPERANDS:    REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f16
IFORM:       VCVTTPH2UQQ_ZMMu64_MASKmskw_XMMf16_AVX512
}

{
ICLASS:      VCVTTPH2UQQ
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR 
PATTERN:    EVV 0x78 V66 MAP5 MOD[0b11] MOD=3 BCRC=1 UBIT=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE()  W0  NOEVSR 
OPERANDS:    REG0=ZMM_R3():w:zu64:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f16
IFORM:       VCVTTPH2UQQ_ZMMu64_MASKmskw_XMMf16_AVX512
}

{
ICLASS:      VCVTTPH2UQQ
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_QUARTER MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR 
PATTERN:    EVV 0x78 V66 MAP5 MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn]  MODRM()  VL512  W0  NOEVSR  ESIZE_16_BITS() NELEM_QUARTER() 
OPERANDS:    REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f16:TXT=BCASTSTR
IFORM:       VCVTTPH2UQQ_ZMMu64_MASKmskw_MEMf16_AVX512
}


# EMITTING VCVTTPH2UW (VCVTTPH2UW-128-1)
{
ICLASS:      VCVTTPH2UW
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_128
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR 
PATTERN:    EVV 0x7C VNP MAP5 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn]  VL128  W0  NOEVSR 
OPERANDS:    REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f16
IFORM:       VCVTTPH2UW_XMMu16_MASKmskw_XMMf16_AVX512
}

{
ICLASS:      VCVTTPH2UW
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_128
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR 
PATTERN:    EVV 0x7C VNP MAP5 MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn]  MODRM()  VL128  W0  NOEVSR  ESIZE_16_BITS() NELEM_FULL() 
OPERANDS:    REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f16:TXT=BCASTSTR
IFORM:       VCVTTPH2UW_XMMu16_MASKmskw_MEMf16_AVX512
}


# EMITTING VCVTTPH2UW (VCVTTPH2UW-256-1)
{
ICLASS:      VCVTTPH2UW
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_256
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR 
PATTERN:    EVV 0x7C VNP MAP5 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn]  VL256  W0  NOEVSR 
OPERANDS:    REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f16
IFORM:       VCVTTPH2UW_YMMu16_MASKmskw_YMMf16_AVX512
}

{
ICLASS:      VCVTTPH2UW
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_256
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR 
PATTERN:    EVV 0x7C VNP MAP5 MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn]  MODRM()  VL256  W0  NOEVSR  ESIZE_16_BITS() NELEM_FULL() 
OPERANDS:    REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f16:TXT=BCASTSTR
IFORM:       VCVTTPH2UW_YMMu16_MASKmskw_MEMf16_AVX512
}


# EMITTING VCVTTPH2UW (VCVTTPH2UW-512-1)
{
ICLASS:      VCVTTPH2UW
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR 
PATTERN:    EVV 0x7C VNP MAP5 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn]  VL512  W0  NOEVSR 
OPERANDS:    REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf16
IFORM:       VCVTTPH2UW_ZMMu16_MASKmskw_ZMMf16_AVX512
}

{
ICLASS:      VCVTTPH2UW
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR 
PATTERN:    EVV 0x7C VNP MAP5 MOD[0b11] MOD=3 BCRC=1 UBIT=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE()  W0  NOEVSR 
OPERANDS:    REG0=ZMM_R3():w:zu16:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf16
IFORM:       VCVTTPH2UW_ZMMu16_MASKmskw_ZMMf16_AVX512
}

{
ICLASS:      VCVTTPH2UW
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR 
PATTERN:    EVV 0x7C VNP MAP5 MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn]  MODRM()  VL512  W0  NOEVSR  ESIZE_16_BITS() NELEM_FULL() 
OPERANDS:    REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f16:TXT=BCASTSTR
IFORM:       VCVTTPH2UW_ZMMu16_MASKmskw_MEMf16_AVX512
}


# EMITTING VCVTTPH2W (VCVTTPH2W-128-1)
{
ICLASS:      VCVTTPH2W
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_128
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR 
PATTERN:    EVV 0x7C V66 MAP5 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn]  VL128  W0  NOEVSR 
OPERANDS:    REG0=XMM_R3():w:dq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f16
IFORM:       VCVTTPH2W_XMMi16_MASKmskw_XMMf16_AVX512
}

{
ICLASS:      VCVTTPH2W
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_128
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR 
PATTERN:    EVV 0x7C V66 MAP5 MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn]  MODRM()  VL128  W0  NOEVSR  ESIZE_16_BITS() NELEM_FULL() 
OPERANDS:    REG0=XMM_R3():w:dq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f16:TXT=BCASTSTR
IFORM:       VCVTTPH2W_XMMi16_MASKmskw_MEMf16_AVX512
}


# EMITTING VCVTTPH2W (VCVTTPH2W-256-1)
{
ICLASS:      VCVTTPH2W
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_256
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR 
PATTERN:    EVV 0x7C V66 MAP5 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn]  VL256  W0  NOEVSR 
OPERANDS:    REG0=YMM_R3():w:qq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f16
IFORM:       VCVTTPH2W_YMMi16_MASKmskw_YMMf16_AVX512
}

{
ICLASS:      VCVTTPH2W
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_256
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR 
PATTERN:    EVV 0x7C V66 MAP5 MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn]  MODRM()  VL256  W0  NOEVSR  ESIZE_16_BITS() NELEM_FULL() 
OPERANDS:    REG0=YMM_R3():w:qq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f16:TXT=BCASTSTR
IFORM:       VCVTTPH2W_YMMi16_MASKmskw_MEMf16_AVX512
}


# EMITTING VCVTTPH2W (VCVTTPH2W-512-1)
{
ICLASS:      VCVTTPH2W
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR 
PATTERN:    EVV 0x7C V66 MAP5 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn]  VL512  W0  NOEVSR 
OPERANDS:    REG0=ZMM_R3():w:zi16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf16
IFORM:       VCVTTPH2W_ZMMi16_MASKmskw_ZMMf16_AVX512
}

{
ICLASS:      VCVTTPH2W
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR 
PATTERN:    EVV 0x7C V66 MAP5 MOD[0b11] MOD=3 BCRC=1 UBIT=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE()  W0  NOEVSR 
OPERANDS:    REG0=ZMM_R3():w:zi16:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf16
IFORM:       VCVTTPH2W_ZMMi16_MASKmskw_ZMMf16_AVX512
}

{
ICLASS:      VCVTTPH2W
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR 
PATTERN:    EVV 0x7C V66 MAP5 MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn]  MODRM()  VL512  W0  NOEVSR  ESIZE_16_BITS() NELEM_FULL() 
OPERANDS:    REG0=ZMM_R3():w:zi16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f16:TXT=BCASTSTR
IFORM:       VCVTTPH2W_ZMMi16_MASKmskw_MEMf16_AVX512
}


# EMITTING VCVTTSH2SI (VCVTTSH2SI-128-1-mode64)
{
ICLASS:      VCVTTSH2SI
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_SCALAR
EXCEPTIONS:     AVX512-E3NF
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR SIMD_SCALAR 
PATTERN:    EVV 0x2C VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn]  FIX_ROUND_LEN128() W0  mode64  NOEVSR  ZEROING=0 MASK=0 EVEXR4_ONE() 
OPERANDS:    REG0=GPR32_R():w:d:i32 REG1=XMM_B3():r:dq:f16
IFORM:       VCVTTSH2SI_GPR32i32_XMMf16_AVX512
}

{
ICLASS:      VCVTTSH2SI
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_SCALAR
EXCEPTIONS:     AVX512-E3NF
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR SIMD_SCALAR 
PATTERN:    EVV 0x2C VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 UBIT=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE()  W0  mode64  NOEVSR  ZEROING=0 MASK=0 EVEXR4_ONE() 
OPERANDS:    REG0=GPR32_R():w:d:i32:TXT=SAESTR REG1=XMM_B3():r:dq:f16
IFORM:       VCVTTSH2SI_GPR32i32_XMMf16_AVX512
}

{
ICLASS:      VCVTTSH2SI
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_SCALAR
EXCEPTIONS:     AVX512-E3NF
REAL_OPCODE: Y
ATTRIBUTES:  DISP8_GPR_WRITER_LDOP_D MXCSR SIMD_SCALAR 
PATTERN:    EVV 0x2C VF3 MAP5 MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn] BCRC=0 MODRM()  FIX_ROUND_LEN128() W0  mode64  NOEVSR  ZEROING=0 MASK=0  ESIZE_16_BITS() NELEM_GPR_WRITER_LDOP_D() EVEXR4_ONE() 
OPERANDS:    REG0=GPR32_R():w:d:i32 MEM0:r:wrd:f16
IFORM:       VCVTTSH2SI_GPR32i32_MEMf16_AVX512
}


# EMITTING VCVTTSH2SI (VCVTTSH2SI-128-1-not64)
{
ICLASS:      VCVTTSH2SI
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_SCALAR
EXCEPTIONS:     AVX512-E3NF
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR SIMD_SCALAR 
PATTERN:    EVV 0x2C VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn]  FIX_ROUND_LEN128()   not64  NOEVSR  ZEROING=0 MASK=0 EVEXR4_ONE() 
OPERANDS:    REG0=GPR32_R():w:d:i32 REG1=XMM_B3():r:dq:f16
IFORM:       VCVTTSH2SI_GPR32i32_XMMf16_AVX512
}

{
ICLASS:      VCVTTSH2SI
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_SCALAR
EXCEPTIONS:     AVX512-E3NF
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR SIMD_SCALAR 
PATTERN:    EVV 0x2C VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 UBIT=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE()    not64  NOEVSR  ZEROING=0 MASK=0 EVEXR4_ONE() 
OPERANDS:    REG0=GPR32_R():w:d:i32:TXT=SAESTR REG1=XMM_B3():r:dq:f16
IFORM:       VCVTTSH2SI_GPR32i32_XMMf16_AVX512
}

{
ICLASS:      VCVTTSH2SI
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_SCALAR
EXCEPTIONS:     AVX512-E3NF
REAL_OPCODE: Y
ATTRIBUTES:  DISP8_GPR_WRITER_LDOP_D MXCSR SIMD_SCALAR 
PATTERN:    EVV 0x2C VF3 MAP5 MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn] BCRC=0 MODRM()  FIX_ROUND_LEN128()   not64  NOEVSR  ZEROING=0 MASK=0  ESIZE_16_BITS() NELEM_GPR_WRITER_LDOP_D() EVEXR4_ONE() 
OPERANDS:    REG0=GPR32_R():w:d:i32 MEM0:r:wrd:f16
IFORM:       VCVTTSH2SI_GPR32i32_MEMf16_AVX512
}


# EMITTING VCVTTSH2SI (VCVTTSH2SI-128-2)
{
ICLASS:      VCVTTSH2SI
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_SCALAR
EXCEPTIONS:     AVX512-E3NF
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR SIMD_SCALAR 
PATTERN:    EVV 0x2C VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn]  FIX_ROUND_LEN128() W1  mode64  NOEVSR  ZEROING=0 MASK=0 EVEXR4_ONE() 
OPERANDS:    REG0=GPR64_R():w:q:i64 REG1=XMM_B3():r:dq:f16
IFORM:       VCVTTSH2SI_GPR64i64_XMMf16_AVX512
}

{
ICLASS:      VCVTTSH2SI
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_SCALAR
EXCEPTIONS:     AVX512-E3NF
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR SIMD_SCALAR 
PATTERN:    EVV 0x2C VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 UBIT=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE()  W1  mode64  NOEVSR  ZEROING=0 MASK=0 EVEXR4_ONE() 
OPERANDS:    REG0=GPR64_R():w:q:i64:TXT=SAESTR REG1=XMM_B3():r:dq:f16
IFORM:       VCVTTSH2SI_GPR64i64_XMMf16_AVX512
}

{
ICLASS:      VCVTTSH2SI
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_SCALAR
EXCEPTIONS:     AVX512-E3NF
REAL_OPCODE: Y
ATTRIBUTES:  DISP8_GPR_WRITER_LDOP_D MXCSR SIMD_SCALAR 
PATTERN:    EVV 0x2C VF3 MAP5 MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn] BCRC=0 MODRM()  FIX_ROUND_LEN128() W1  mode64  NOEVSR  ZEROING=0 MASK=0  ESIZE_16_BITS() NELEM_GPR_WRITER_LDOP_D() EVEXR4_ONE() 
OPERANDS:    REG0=GPR64_R():w:q:i64 MEM0:r:wrd:f16
IFORM:       VCVTTSH2SI_GPR64i64_MEMf16_AVX512
}


# EMITTING VCVTTSH2USI (VCVTTSH2USI-128-1-mode64)
{
ICLASS:      VCVTTSH2USI
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_SCALAR
EXCEPTIONS:     AVX512-E3NF
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR SIMD_SCALAR 
PATTERN:    EVV 0x78 VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn]  FIX_ROUND_LEN128() W0  mode64  NOEVSR  ZEROING=0 MASK=0 EVEXR4_ONE() 
OPERANDS:    REG0=GPR32_R():w:d:u32 REG1=XMM_B3():r:dq:f16
IFORM:       VCVTTSH2USI_GPR32u32_XMMf16_AVX512
}

{
ICLASS:      VCVTTSH2USI
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_SCALAR
EXCEPTIONS:     AVX512-E3NF
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR SIMD_SCALAR 
PATTERN:    EVV 0x78 VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 UBIT=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE()  W0  mode64  NOEVSR  ZEROING=0 MASK=0 EVEXR4_ONE() 
OPERANDS:    REG0=GPR32_R():w:d:u32:TXT=SAESTR REG1=XMM_B3():r:dq:f16
IFORM:       VCVTTSH2USI_GPR32u32_XMMf16_AVX512
}

{
ICLASS:      VCVTTSH2USI
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_SCALAR
EXCEPTIONS:     AVX512-E3NF
REAL_OPCODE: Y
ATTRIBUTES:  DISP8_GPR_WRITER_LDOP_D MXCSR SIMD_SCALAR 
PATTERN:    EVV 0x78 VF3 MAP5 MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn] BCRC=0 MODRM()  FIX_ROUND_LEN128() W0  mode64  NOEVSR  ZEROING=0 MASK=0  ESIZE_16_BITS() NELEM_GPR_WRITER_LDOP_D() EVEXR4_ONE() 
OPERANDS:    REG0=GPR32_R():w:d:u32 MEM0:r:wrd:f16
IFORM:       VCVTTSH2USI_GPR32u32_MEMf16_AVX512
}


# EMITTING VCVTTSH2USI (VCVTTSH2USI-128-1-not64)
{
ICLASS:      VCVTTSH2USI
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_SCALAR
EXCEPTIONS:     AVX512-E3NF
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR SIMD_SCALAR 
PATTERN:    EVV 0x78 VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn]  FIX_ROUND_LEN128()   not64  NOEVSR  ZEROING=0 MASK=0 EVEXR4_ONE() 
OPERANDS:    REG0=GPR32_R():w:d:u32 REG1=XMM_B3():r:dq:f16
IFORM:       VCVTTSH2USI_GPR32u32_XMMf16_AVX512
}

{
ICLASS:      VCVTTSH2USI
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_SCALAR
EXCEPTIONS:     AVX512-E3NF
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR SIMD_SCALAR 
PATTERN:    EVV 0x78 VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 UBIT=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE()    not64  NOEVSR  ZEROING=0 MASK=0 EVEXR4_ONE() 
OPERANDS:    REG0=GPR32_R():w:d:u32:TXT=SAESTR REG1=XMM_B3():r:dq:f16
IFORM:       VCVTTSH2USI_GPR32u32_XMMf16_AVX512
}

{
ICLASS:      VCVTTSH2USI
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_SCALAR
EXCEPTIONS:     AVX512-E3NF
REAL_OPCODE: Y
ATTRIBUTES:  DISP8_GPR_WRITER_LDOP_D MXCSR SIMD_SCALAR 
PATTERN:    EVV 0x78 VF3 MAP5 MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn] BCRC=0 MODRM()  FIX_ROUND_LEN128()   not64  NOEVSR  ZEROING=0 MASK=0  ESIZE_16_BITS() NELEM_GPR_WRITER_LDOP_D() EVEXR4_ONE() 
OPERANDS:    REG0=GPR32_R():w:d:u32 MEM0:r:wrd:f16
IFORM:       VCVTTSH2USI_GPR32u32_MEMf16_AVX512
}


# EMITTING VCVTTSH2USI (VCVTTSH2USI-128-2)
{
ICLASS:      VCVTTSH2USI
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_SCALAR
EXCEPTIONS:     AVX512-E3NF
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR SIMD_SCALAR 
PATTERN:    EVV 0x78 VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn]  FIX_ROUND_LEN128() W1  mode64  NOEVSR  ZEROING=0 MASK=0 EVEXR4_ONE() 
OPERANDS:    REG0=GPR64_R():w:q:u64 REG1=XMM_B3():r:dq:f16
IFORM:       VCVTTSH2USI_GPR64u64_XMMf16_AVX512
}

{
ICLASS:      VCVTTSH2USI
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_SCALAR
EXCEPTIONS:     AVX512-E3NF
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR SIMD_SCALAR 
PATTERN:    EVV 0x78 VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 UBIT=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE()  W1  mode64  NOEVSR  ZEROING=0 MASK=0 EVEXR4_ONE() 
OPERANDS:    REG0=GPR64_R():w:q:u64:TXT=SAESTR REG1=XMM_B3():r:dq:f16
IFORM:       VCVTTSH2USI_GPR64u64_XMMf16_AVX512
}

{
ICLASS:      VCVTTSH2USI
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_SCALAR
EXCEPTIONS:     AVX512-E3NF
REAL_OPCODE: Y
ATTRIBUTES:  DISP8_GPR_WRITER_LDOP_D MXCSR SIMD_SCALAR 
PATTERN:    EVV 0x78 VF3 MAP5 MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn] BCRC=0 MODRM()  FIX_ROUND_LEN128() W1  mode64  NOEVSR  ZEROING=0 MASK=0  ESIZE_16_BITS() NELEM_GPR_WRITER_LDOP_D() EVEXR4_ONE() 
OPERANDS:    REG0=GPR64_R():w:q:u64 MEM0:r:wrd:f16
IFORM:       VCVTTSH2USI_GPR64u64_MEMf16_AVX512
}


# EMITTING VCVTUDQ2PH (VCVTUDQ2PH-128-1)
{
ICLASS:      VCVTUDQ2PH
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_128
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR 
PATTERN:    EVV 0x7A VF2 MAP5 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn]  VL128  W0  NOEVSR 
OPERANDS:    REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u32
IFORM:       VCVTUDQ2PH_XMMf16_MASKmskw_XMMu32_AVX512
}

{
ICLASS:      VCVTUDQ2PH
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_128
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR 
PATTERN:    EVV 0x7A VF2 MAP5 MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn]  MODRM()  VL128  W0  NOEVSR  ESIZE_32_BITS() NELEM_FULL() 
OPERANDS:    REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u32:TXT=BCASTSTR
IFORM:       VCVTUDQ2PH_XMMf16_MASKmskw_MEMu32_AVX512_VL128
}


# EMITTING VCVTUDQ2PH (VCVTUDQ2PH-256-1)
{
ICLASS:      VCVTUDQ2PH
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_256
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR 
PATTERN:    EVV 0x7A VF2 MAP5 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn]  VL256  W0  NOEVSR 
OPERANDS:    REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u32
IFORM:       VCVTUDQ2PH_XMMf16_MASKmskw_YMMu32_AVX512
}

{
ICLASS:      VCVTUDQ2PH
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_256
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR 
PATTERN:    EVV 0x7A VF2 MAP5 MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn]  MODRM()  VL256  W0  NOEVSR  ESIZE_32_BITS() NELEM_FULL() 
OPERANDS:    REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u32:TXT=BCASTSTR
IFORM:       VCVTUDQ2PH_XMMf16_MASKmskw_MEMu32_AVX512_VL256
}


# EMITTING VCVTUDQ2PH (VCVTUDQ2PH-512-1)
{
ICLASS:      VCVTUDQ2PH
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR 
PATTERN:    EVV 0x7A VF2 MAP5 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn]  VL512  W0  NOEVSR 
OPERANDS:    REG0=YMM_R3():w:qq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu32
IFORM:       VCVTUDQ2PH_YMMf16_MASKmskw_ZMMu32_AVX512
}

{
ICLASS:      VCVTUDQ2PH
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR 
PATTERN:    EVV 0x7A VF2 MAP5 MOD[0b11] MOD=3 BCRC=1 UBIT=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND()  W0  NOEVSR 
OPERANDS:    REG0=YMM_R3():w:qq:f16:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu32
IFORM:       VCVTUDQ2PH_YMMf16_MASKmskw_ZMMu32_AVX512
}

{
ICLASS:      VCVTUDQ2PH
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR 
PATTERN:    EVV 0x7A VF2 MAP5 MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn]  MODRM()  VL512  W0  NOEVSR  ESIZE_32_BITS() NELEM_FULL() 
OPERANDS:    REG0=YMM_R3():w:qq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u32:TXT=BCASTSTR
IFORM:       VCVTUDQ2PH_YMMf16_MASKmskw_MEMu32_AVX512
}


# EMITTING VCVTUQQ2PH (VCVTUQQ2PH-128-1)
{
ICLASS:      VCVTUQQ2PH
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_128
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR 
PATTERN:    EVV 0x7A VF2 MAP5 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn]  VL128  W1  NOEVSR 
OPERANDS:    REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u64
IFORM:       VCVTUQQ2PH_XMMf16_MASKmskw_XMMu64_AVX512
}

{
ICLASS:      VCVTUQQ2PH
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_128
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR 
PATTERN:    EVV 0x7A VF2 MAP5 MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn]  MODRM()  VL128  W1  NOEVSR  ESIZE_64_BITS() NELEM_FULL() 
OPERANDS:    REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u64:TXT=BCASTSTR
IFORM:       VCVTUQQ2PH_XMMf16_MASKmskw_MEMu64_AVX512_VL128
}


# EMITTING VCVTUQQ2PH (VCVTUQQ2PH-256-1)
{
ICLASS:      VCVTUQQ2PH
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_256
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR 
PATTERN:    EVV 0x7A VF2 MAP5 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn]  VL256  W1  NOEVSR 
OPERANDS:    REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u64
IFORM:       VCVTUQQ2PH_XMMf16_MASKmskw_YMMu64_AVX512
}

{
ICLASS:      VCVTUQQ2PH
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_256
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR 
PATTERN:    EVV 0x7A VF2 MAP5 MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn]  MODRM()  VL256  W1  NOEVSR  ESIZE_64_BITS() NELEM_FULL() 
OPERANDS:    REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u64:TXT=BCASTSTR
IFORM:       VCVTUQQ2PH_XMMf16_MASKmskw_MEMu64_AVX512_VL256
}


# EMITTING VCVTUQQ2PH (VCVTUQQ2PH-512-1)
{
ICLASS:      VCVTUQQ2PH
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR 
PATTERN:    EVV 0x7A VF2 MAP5 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn]  VL512  W1  NOEVSR 
OPERANDS:    REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu64
IFORM:       VCVTUQQ2PH_XMMf16_MASKmskw_ZMMu64_AVX512
}

{
ICLASS:      VCVTUQQ2PH
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR 
PATTERN:    EVV 0x7A VF2 MAP5 MOD[0b11] MOD=3 BCRC=1 UBIT=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND()  W1  NOEVSR 
OPERANDS:    REG0=XMM_R3():w:dq:f16:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu64
IFORM:       VCVTUQQ2PH_XMMf16_MASKmskw_ZMMu64_AVX512
}

{
ICLASS:      VCVTUQQ2PH
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR 
PATTERN:    EVV 0x7A VF2 MAP5 MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn]  MODRM()  VL512  W1  NOEVSR  ESIZE_64_BITS() NELEM_FULL() 
OPERANDS:    REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u64:TXT=BCASTSTR
IFORM:       VCVTUQQ2PH_XMMf16_MASKmskw_MEMu64_AVX512_VL512
}


# EMITTING VCVTUSI2SH (VCVTUSI2SH-128-1-mode64)
{
ICLASS:      VCVTUSI2SH
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_SCALAR
EXCEPTIONS:     AVX512-E3NF
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR SIMD_SCALAR 
PATTERN:    EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn]  FIX_ROUND_LEN128() W0  mode64    ZEROING=0 MASK=0 
OPERANDS:    REG0=XMM_R3():w:dq:f16 REG1=XMM_N3():r:dq:f16 REG2=GPR32_B():r:d:u32
IFORM:       VCVTUSI2SH_XMMf16_XMMf16_GPR32u32_AVX512
}

{
ICLASS:      VCVTUSI2SH
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_SCALAR
EXCEPTIONS:     AVX512-E3NF
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR SIMD_SCALAR 
PATTERN:    EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 UBIT=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND()  W0  mode64    ZEROING=0 MASK=0 
OPERANDS:    REG0=XMM_R3():w:dq:f16:TXT=ROUNDC REG1=XMM_N3():r:dq:f16 REG2=GPR32_B():r:d:u32
IFORM:       VCVTUSI2SH_XMMf16_XMMf16_GPR32u32_AVX512
}

{
ICLASS:      VCVTUSI2SH
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_SCALAR
EXCEPTIONS:     AVX512-E3NF
REAL_OPCODE: Y
ATTRIBUTES:  DISP8_GPR_READER MXCSR SIMD_SCALAR 
PATTERN:    EVV 0x7B VF3 MAP5 MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn] BCRC=0 MODRM()  FIX_ROUND_LEN128() W0  mode64    ZEROING=0 MASK=0  ESIZE_32_BITS() NELEM_GPR_READER() 
OPERANDS:    REG0=XMM_R3():w:dq:f16 REG1=XMM_N3():r:dq:f16 MEM0:r:d:u32
IFORM:       VCVTUSI2SH_XMMf16_XMMf16_MEMu32_AVX512
}


# EMITTING VCVTUSI2SH (VCVTUSI2SH-128-1-not64)
{
ICLASS:      VCVTUSI2SH
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_SCALAR
EXCEPTIONS:     AVX512-E3NF
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR SIMD_SCALAR 
PATTERN:    EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn]  FIX_ROUND_LEN128()   not64    ZEROING=0 MASK=0 
OPERANDS:    REG0=XMM_R3():w:dq:f16 REG1=XMM_N3():r:dq:f16 REG2=GPR32_B():r:d:u32
IFORM:       VCVTUSI2SH_XMMf16_XMMf16_GPR32u32_AVX512
}

{
ICLASS:      VCVTUSI2SH
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_SCALAR
EXCEPTIONS:     AVX512-E3NF
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR SIMD_SCALAR 
PATTERN:    EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 UBIT=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND()    not64    ZEROING=0 MASK=0 
OPERANDS:    REG0=XMM_R3():w:dq:f16:TXT=ROUNDC REG1=XMM_N3():r:dq:f16 REG2=GPR32_B():r:d:u32
IFORM:       VCVTUSI2SH_XMMf16_XMMf16_GPR32u32_AVX512
}

{
ICLASS:      VCVTUSI2SH
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_SCALAR
EXCEPTIONS:     AVX512-E3NF
REAL_OPCODE: Y
ATTRIBUTES:  DISP8_GPR_READER MXCSR SIMD_SCALAR 
PATTERN:    EVV 0x7B VF3 MAP5 MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn] BCRC=0 MODRM()  FIX_ROUND_LEN128()   not64    ZEROING=0 MASK=0  ESIZE_32_BITS() NELEM_GPR_READER() 
OPERANDS:    REG0=XMM_R3():w:dq:f16 REG1=XMM_N3():r:dq:f16 MEM0:r:d:u32
IFORM:       VCVTUSI2SH_XMMf16_XMMf16_MEMu32_AVX512
}


# EMITTING VCVTUSI2SH (VCVTUSI2SH-128-2)
{
ICLASS:      VCVTUSI2SH
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_SCALAR
EXCEPTIONS:     AVX512-E3NF
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR SIMD_SCALAR 
PATTERN:    EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn]  FIX_ROUND_LEN128() W1  mode64    ZEROING=0 MASK=0 
OPERANDS:    REG0=XMM_R3():w:dq:f16 REG1=XMM_N3():r:dq:f16 REG2=GPR64_B():r:q:u64
IFORM:       VCVTUSI2SH_XMMf16_XMMf16_GPR64u64_AVX512
}

{
ICLASS:      VCVTUSI2SH
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_SCALAR
EXCEPTIONS:     AVX512-E3NF
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR SIMD_SCALAR 
PATTERN:    EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 UBIT=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND()  W1  mode64    ZEROING=0 MASK=0 
OPERANDS:    REG0=XMM_R3():w:dq:f16:TXT=ROUNDC REG1=XMM_N3():r:dq:f16 REG2=GPR64_B():r:q:u64
IFORM:       VCVTUSI2SH_XMMf16_XMMf16_GPR64u64_AVX512
}

{
ICLASS:      VCVTUSI2SH
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_SCALAR
EXCEPTIONS:     AVX512-E3NF
REAL_OPCODE: Y
ATTRIBUTES:  DISP8_GPR_READER MXCSR SIMD_SCALAR 
PATTERN:    EVV 0x7B VF3 MAP5 MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn] BCRC=0 MODRM()  FIX_ROUND_LEN128() W1  mode64    ZEROING=0 MASK=0  ESIZE_64_BITS() NELEM_GPR_READER() 
OPERANDS:    REG0=XMM_R3():w:dq:f16 REG1=XMM_N3():r:dq:f16 MEM0:r:q:u64
IFORM:       VCVTUSI2SH_XMMf16_XMMf16_MEMu64_AVX512
}


# EMITTING VCVTUW2PH (VCVTUW2PH-128-1)
{
ICLASS:      VCVTUW2PH
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_128
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR 
PATTERN:    EVV 0x7D VF2 MAP5 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn]  VL128  W0  NOEVSR 
OPERANDS:    REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u16
IFORM:       VCVTUW2PH_XMMf16_MASKmskw_XMMu16_AVX512
}

{
ICLASS:      VCVTUW2PH
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_128
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR 
PATTERN:    EVV 0x7D VF2 MAP5 MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn]  MODRM()  VL128  W0  NOEVSR  ESIZE_16_BITS() NELEM_FULL() 
OPERANDS:    REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u16:TXT=BCASTSTR
IFORM:       VCVTUW2PH_XMMf16_MASKmskw_MEMu16_AVX512
}


# EMITTING VCVTUW2PH (VCVTUW2PH-256-1)
{
ICLASS:      VCVTUW2PH
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_256
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR 
PATTERN:    EVV 0x7D VF2 MAP5 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn]  VL256  W0  NOEVSR 
OPERANDS:    REG0=YMM_R3():w:qq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u16
IFORM:       VCVTUW2PH_YMMf16_MASKmskw_YMMu16_AVX512
}

{
ICLASS:      VCVTUW2PH
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_256
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR 
PATTERN:    EVV 0x7D VF2 MAP5 MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn]  MODRM()  VL256  W0  NOEVSR  ESIZE_16_BITS() NELEM_FULL() 
OPERANDS:    REG0=YMM_R3():w:qq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u16:TXT=BCASTSTR
IFORM:       VCVTUW2PH_YMMf16_MASKmskw_MEMu16_AVX512
}


# EMITTING VCVTUW2PH (VCVTUW2PH-512-1)
{
ICLASS:      VCVTUW2PH
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR 
PATTERN:    EVV 0x7D VF2 MAP5 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn]  VL512  W0  NOEVSR 
OPERANDS:    REG0=ZMM_R3():w:zf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu16
IFORM:       VCVTUW2PH_ZMMf16_MASKmskw_ZMMu16_AVX512
}

{
ICLASS:      VCVTUW2PH
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR 
PATTERN:    EVV 0x7D VF2 MAP5 MOD[0b11] MOD=3 BCRC=1 UBIT=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND()  W0  NOEVSR 
OPERANDS:    REG0=ZMM_R3():w:zf16:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu16
IFORM:       VCVTUW2PH_ZMMf16_MASKmskw_ZMMu16_AVX512
}

{
ICLASS:      VCVTUW2PH
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR 
PATTERN:    EVV 0x7D VF2 MAP5 MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn]  MODRM()  VL512  W0  NOEVSR  ESIZE_16_BITS() NELEM_FULL() 
OPERANDS:    REG0=ZMM_R3():w:zf16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u16:TXT=BCASTSTR
IFORM:       VCVTUW2PH_ZMMf16_MASKmskw_MEMu16_AVX512
}


# EMITTING VCVTW2PH (VCVTW2PH-128-1)
{
ICLASS:      VCVTW2PH
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_128
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR 
PATTERN:    EVV 0x7D VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn]  VL128  W0  NOEVSR 
OPERANDS:    REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i16
IFORM:       VCVTW2PH_XMMf16_MASKmskw_XMMi16_AVX512
}

{
ICLASS:      VCVTW2PH
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_128
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR 
PATTERN:    EVV 0x7D VF3 MAP5 MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn]  MODRM()  VL128  W0  NOEVSR  ESIZE_16_BITS() NELEM_FULL() 
OPERANDS:    REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:i16:TXT=BCASTSTR
IFORM:       VCVTW2PH_XMMf16_MASKmskw_MEMi16_AVX512
}


# EMITTING VCVTW2PH (VCVTW2PH-256-1)
{
ICLASS:      VCVTW2PH
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_256
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR 
PATTERN:    EVV 0x7D VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn]  VL256  W0  NOEVSR 
OPERANDS:    REG0=YMM_R3():w:qq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:i16
IFORM:       VCVTW2PH_YMMf16_MASKmskw_YMMi16_AVX512
}

{
ICLASS:      VCVTW2PH
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_256
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR 
PATTERN:    EVV 0x7D VF3 MAP5 MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn]  MODRM()  VL256  W0  NOEVSR  ESIZE_16_BITS() NELEM_FULL() 
OPERANDS:    REG0=YMM_R3():w:qq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:i16:TXT=BCASTSTR
IFORM:       VCVTW2PH_YMMf16_MASKmskw_MEMi16_AVX512
}


# EMITTING VCVTW2PH (VCVTW2PH-512-1)
{
ICLASS:      VCVTW2PH
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR 
PATTERN:    EVV 0x7D VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn]  VL512  W0  NOEVSR 
OPERANDS:    REG0=ZMM_R3():w:zf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zi16
IFORM:       VCVTW2PH_ZMMf16_MASKmskw_ZMMi16_AVX512
}

{
ICLASS:      VCVTW2PH
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR 
PATTERN:    EVV 0x7D VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 UBIT=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND()  W0  NOEVSR 
OPERANDS:    REG0=ZMM_R3():w:zf16:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zi16
IFORM:       VCVTW2PH_ZMMf16_MASKmskw_ZMMi16_AVX512
}

{
ICLASS:      VCVTW2PH
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR 
PATTERN:    EVV 0x7D VF3 MAP5 MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn]  MODRM()  VL512  W0  NOEVSR  ESIZE_16_BITS() NELEM_FULL() 
OPERANDS:    REG0=ZMM_R3():w:zf16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:i16:TXT=BCASTSTR
IFORM:       VCVTW2PH_ZMMf16_MASKmskw_MEMi16_AVX512
}


# EMITTING VDIVPH (VDIVPH-128-1)
{
ICLASS:      VDIVPH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_128
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR 
PATTERN:    EVV 0x5E VNP MAP5 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn]  VL128  W0   
OPERANDS:    REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 REG3=XMM_B3():r:dq:f16
IFORM:       VDIVPH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512
}

{
ICLASS:      VDIVPH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_128
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR 
PATTERN:    EVV 0x5E VNP MAP5 MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn]  MODRM()  VL128  W0    ESIZE_16_BITS() NELEM_FULL() 
OPERANDS:    REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 MEM0:r:vv:f16:TXT=BCASTSTR
IFORM:       VDIVPH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512
}


# EMITTING VDIVPH (VDIVPH-256-1)
{
ICLASS:      VDIVPH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_256
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR 
PATTERN:    EVV 0x5E VNP MAP5 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn]  VL256  W0   
OPERANDS:    REG0=YMM_R3():w:qq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f16 REG3=YMM_B3():r:qq:f16
IFORM:       VDIVPH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512
}

{
ICLASS:      VDIVPH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_256
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR 
PATTERN:    EVV 0x5E VNP MAP5 MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn]  MODRM()  VL256  W0    ESIZE_16_BITS() NELEM_FULL() 
OPERANDS:    REG0=YMM_R3():w:qq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f16 MEM0:r:vv:f16:TXT=BCASTSTR
IFORM:       VDIVPH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512
}


# EMITTING VDIVPH (VDIVPH-512-1)
{
ICLASS:      VDIVPH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR 
PATTERN:    EVV 0x5E VNP MAP5 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn]  VL512  W0   
OPERANDS:    REG0=ZMM_R3():w:zf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf16 REG3=ZMM_B3():r:zf16
IFORM:       VDIVPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512
}

{
ICLASS:      VDIVPH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR 
PATTERN:    EVV 0x5E VNP MAP5 MOD[0b11] MOD=3 BCRC=1 UBIT=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND()  W0   
OPERANDS:    REG0=ZMM_R3():w:zf16:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf16 REG3=ZMM_B3():r:zf16
IFORM:       VDIVPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512
}

{
ICLASS:      VDIVPH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR 
PATTERN:    EVV 0x5E VNP MAP5 MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn]  MODRM()  VL512  W0    ESIZE_16_BITS() NELEM_FULL() 
OPERANDS:    REG0=ZMM_R3():w:zf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf16 MEM0:r:vv:f16:TXT=BCASTSTR
IFORM:       VDIVPH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512
}


# EMITTING VDIVSH (VDIVSH-128-1)
{
ICLASS:      VDIVSH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_SCALAR
EXCEPTIONS:     AVX512-E3
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR SIMD_SCALAR 
PATTERN:    EVV 0x5E VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn]  FIX_ROUND_LEN128() W0   
OPERANDS:    REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 REG3=XMM_B3():r:dq:f16
IFORM:       VDIVSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512
}

{
ICLASS:      VDIVSH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_SCALAR
EXCEPTIONS:     AVX512-E3
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR SIMD_SCALAR 
PATTERN:    EVV 0x5E VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 UBIT=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND()  W0   
OPERANDS:    REG0=XMM_R3():w:dq:f16:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 REG3=XMM_B3():r:dq:f16
IFORM:       VDIVSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512
}

{
ICLASS:      VDIVSH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_SCALAR
EXCEPTIONS:     AVX512-E3
REAL_OPCODE: Y
ATTRIBUTES:  DISP8_SCALAR MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR SIMD_SCALAR 
PATTERN:    EVV 0x5E VF3 MAP5 MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn] BCRC=0 MODRM()  FIX_ROUND_LEN128() W0    ESIZE_16_BITS() NELEM_SCALAR() 
OPERANDS:    REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 MEM0:r:wrd:f16
IFORM:       VDIVSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512
}


# EMITTING VFCMADDCPH (VFCMADDCPH-128-1)
{
ICLASS:      VFCMADDCPH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_128
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR NO_SRC_DEST_MATCH 
PATTERN:    EVV 0x56 VF2 MAP6 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn]  VL128  W0   
OPERANDS:    REG0=XMM_R3():rw:dq:2f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:2f16 REG3=XMM_B3():r:dq:2f16
IFORM:       VFCMADDCPH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512
}

{
ICLASS:      VFCMADDCPH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_128
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR NO_SRC_DEST_MATCH 
PATTERN:    EVV 0x56 VF2 MAP6 MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn]  MODRM()  VL128  W0    ESIZE_32_BITS() NELEM_FULL() 
OPERANDS:    REG0=XMM_R3():rw:dq:2f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:2f16 MEM0:r:vv:2f16:TXT=BCASTSTR
IFORM:       VFCMADDCPH_XMM2f16_MASKmskw_XMM2f16_MEM2f16_AVX512
}


# EMITTING VFCMADDCPH (VFCMADDCPH-256-1)
{
ICLASS:      VFCMADDCPH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_256
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR NO_SRC_DEST_MATCH 
PATTERN:    EVV 0x56 VF2 MAP6 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn]  VL256  W0   
OPERANDS:    REG0=YMM_R3():rw:qq:2f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:2f16 REG3=YMM_B3():r:qq:2f16
IFORM:       VFCMADDCPH_YMM2f16_MASKmskw_YMM2f16_YMM2f16_AVX512
}

{
ICLASS:      VFCMADDCPH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_256
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR NO_SRC_DEST_MATCH 
PATTERN:    EVV 0x56 VF2 MAP6 MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn]  MODRM()  VL256  W0    ESIZE_32_BITS() NELEM_FULL() 
OPERANDS:    REG0=YMM_R3():rw:qq:2f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:2f16 MEM0:r:vv:2f16:TXT=BCASTSTR
IFORM:       VFCMADDCPH_YMM2f16_MASKmskw_YMM2f16_MEM2f16_AVX512
}


# EMITTING VFCMADDCPH (VFCMADDCPH-512-1)
{
ICLASS:      VFCMADDCPH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_512
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR NO_SRC_DEST_MATCH 
PATTERN:    EVV 0x56 VF2 MAP6 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn]  VL512  W0   
OPERANDS:    REG0=ZMM_R3():rw:z2f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:z2f16 REG3=ZMM_B3():r:z2f16
IFORM:       VFCMADDCPH_ZMM2f16_MASKmskw_ZMM2f16_ZMM2f16_AVX512
}

{
ICLASS:      VFCMADDCPH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_512
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR NO_SRC_DEST_MATCH 
PATTERN:    EVV 0x56 VF2 MAP6 MOD[0b11] MOD=3 BCRC=1 UBIT=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND()  W0   
OPERANDS:    REG0=ZMM_R3():rw:z2f16:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:z2f16 REG3=ZMM_B3():r:z2f16
IFORM:       VFCMADDCPH_ZMM2f16_MASKmskw_ZMM2f16_ZMM2f16_AVX512
}

{
ICLASS:      VFCMADDCPH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_512
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR NO_SRC_DEST_MATCH 
PATTERN:    EVV 0x56 VF2 MAP6 MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn]  MODRM()  VL512  W0    ESIZE_32_BITS() NELEM_FULL() 
OPERANDS:    REG0=ZMM_R3():rw:z2f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:z2f16 MEM0:r:vv:2f16:TXT=BCASTSTR
IFORM:       VFCMADDCPH_ZMM2f16_MASKmskw_ZMM2f16_MEM2f16_AVX512
}


# EMITTING VFCMADDCSH (VFCMADDCSH-128-1)
{
ICLASS:      VFCMADDCSH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_SCALAR
EXCEPTIONS:     AVX512-E10
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR NO_SRC_DEST_MATCH SIMD_SCALAR 
PATTERN:    EVV 0x57 VF2 MAP6 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn]  FIX_ROUND_LEN128() W0   
OPERANDS:    REG0=XMM_R3():rw:dq:2f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:2f16 REG3=XMM_B3():r:dq:2f16
IFORM:       VFCMADDCSH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512
}

{
ICLASS:      VFCMADDCSH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_SCALAR
EXCEPTIONS:     AVX512-E10
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR NO_SRC_DEST_MATCH SIMD_SCALAR 
PATTERN:    EVV 0x57 VF2 MAP6 MOD[0b11] MOD=3 BCRC=1 UBIT=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND()  W0   
OPERANDS:    REG0=XMM_R3():rw:dq:2f16:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:2f16 REG3=XMM_B3():r:dq:2f16
IFORM:       VFCMADDCSH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512
}

{
ICLASS:      VFCMADDCSH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_SCALAR
EXCEPTIONS:     AVX512-E10
REAL_OPCODE: Y
ATTRIBUTES:  DISP8_SCALAR MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR NO_SRC_DEST_MATCH SIMD_SCALAR 
PATTERN:    EVV 0x57 VF2 MAP6 MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn] BCRC=0 MODRM()  FIX_ROUND_LEN128() W0    ESIZE_32_BITS() NELEM_SCALAR() 
OPERANDS:    REG0=XMM_R3():rw:dq:2f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:2f16 MEM0:r:d:2f16
IFORM:       VFCMADDCSH_XMM2f16_MASKmskw_XMM2f16_MEM2f16_AVX512
}


# EMITTING VFCMULCPH (VFCMULCPH-128-1)
{
ICLASS:      VFCMULCPH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_128
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR NO_SRC_DEST_MATCH 
PATTERN:    EVV 0xD6 VF2 MAP6 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn]  VL128  W0   
OPERANDS:    REG0=XMM_R3():w:dq:2f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:2f16 REG3=XMM_B3():r:dq:2f16
IFORM:       VFCMULCPH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512
}

{
ICLASS:      VFCMULCPH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_128
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR NO_SRC_DEST_MATCH 
PATTERN:    EVV 0xD6 VF2 MAP6 MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn]  MODRM()  VL128  W0    ESIZE_32_BITS() NELEM_FULL() 
OPERANDS:    REG0=XMM_R3():w:dq:2f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:2f16 MEM0:r:vv:2f16:TXT=BCASTSTR
IFORM:       VFCMULCPH_XMM2f16_MASKmskw_XMM2f16_MEM2f16_AVX512
}


# EMITTING VFCMULCPH (VFCMULCPH-256-1)
{
ICLASS:      VFCMULCPH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_256
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR NO_SRC_DEST_MATCH 
PATTERN:    EVV 0xD6 VF2 MAP6 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn]  VL256  W0   
OPERANDS:    REG0=YMM_R3():w:qq:2f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:2f16 REG3=YMM_B3():r:qq:2f16
IFORM:       VFCMULCPH_YMM2f16_MASKmskw_YMM2f16_YMM2f16_AVX512
}

{
ICLASS:      VFCMULCPH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_256
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR NO_SRC_DEST_MATCH 
PATTERN:    EVV 0xD6 VF2 MAP6 MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn]  MODRM()  VL256  W0    ESIZE_32_BITS() NELEM_FULL() 
OPERANDS:    REG0=YMM_R3():w:qq:2f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:2f16 MEM0:r:vv:2f16:TXT=BCASTSTR
IFORM:       VFCMULCPH_YMM2f16_MASKmskw_YMM2f16_MEM2f16_AVX512
}


# EMITTING VFCMULCPH (VFCMULCPH-512-1)
{
ICLASS:      VFCMULCPH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_512
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR NO_SRC_DEST_MATCH 
PATTERN:    EVV 0xD6 VF2 MAP6 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn]  VL512  W0   
OPERANDS:    REG0=ZMM_R3():w:z2f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:z2f16 REG3=ZMM_B3():r:z2f16
IFORM:       VFCMULCPH_ZMM2f16_MASKmskw_ZMM2f16_ZMM2f16_AVX512
}

{
ICLASS:      VFCMULCPH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_512
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR NO_SRC_DEST_MATCH 
PATTERN:    EVV 0xD6 VF2 MAP6 MOD[0b11] MOD=3 BCRC=1 UBIT=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND()  W0   
OPERANDS:    REG0=ZMM_R3():w:z2f16:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:z2f16 REG3=ZMM_B3():r:z2f16
IFORM:       VFCMULCPH_ZMM2f16_MASKmskw_ZMM2f16_ZMM2f16_AVX512
}

{
ICLASS:      VFCMULCPH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_512
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR NO_SRC_DEST_MATCH 
PATTERN:    EVV 0xD6 VF2 MAP6 MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn]  MODRM()  VL512  W0    ESIZE_32_BITS() NELEM_FULL() 
OPERANDS:    REG0=ZMM_R3():w:z2f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:z2f16 MEM0:r:vv:2f16:TXT=BCASTSTR
IFORM:       VFCMULCPH_ZMM2f16_MASKmskw_ZMM2f16_MEM2f16_AVX512
}


# EMITTING VFCMULCSH (VFCMULCSH-128-1)
{
ICLASS:      VFCMULCSH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_SCALAR
EXCEPTIONS:     AVX512-E10
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR NO_SRC_DEST_MATCH SIMD_SCALAR 
PATTERN:    EVV 0xD7 VF2 MAP6 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn]  FIX_ROUND_LEN128() W0   
OPERANDS:    REG0=XMM_R3():w:dq:2f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:2f16 REG3=XMM_B3():r:dq:2f16
IFORM:       VFCMULCSH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512
}

{
ICLASS:      VFCMULCSH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_SCALAR
EXCEPTIONS:     AVX512-E10
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR NO_SRC_DEST_MATCH SIMD_SCALAR 
PATTERN:    EVV 0xD7 VF2 MAP6 MOD[0b11] MOD=3 BCRC=1 UBIT=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND()  W0   
OPERANDS:    REG0=XMM_R3():w:dq:2f16:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:2f16 REG3=XMM_B3():r:dq:2f16
IFORM:       VFCMULCSH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512
}

{
ICLASS:      VFCMULCSH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_SCALAR
EXCEPTIONS:     AVX512-E10
REAL_OPCODE: Y
ATTRIBUTES:  DISP8_SCALAR MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR NO_SRC_DEST_MATCH SIMD_SCALAR 
PATTERN:    EVV 0xD7 VF2 MAP6 MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn] BCRC=0 MODRM()  FIX_ROUND_LEN128() W0    ESIZE_32_BITS() NELEM_SCALAR() 
OPERANDS:    REG0=XMM_R3():w:dq:2f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:2f16 MEM0:r:d:2f16
IFORM:       VFCMULCSH_XMM2f16_MASKmskw_XMM2f16_MEM2f16_AVX512
}


# EMITTING VFMADD132PH (VFMADD132PH-128-1)
{
ICLASS:      VFMADD132PH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_128
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR 
PATTERN:    EVV 0x98 V66 MAP6 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn]  VL128  W0   
OPERANDS:    REG0=XMM_R3():rw:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 REG3=XMM_B3():r:dq:f16
IFORM:       VFMADD132PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512
}

{
ICLASS:      VFMADD132PH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_128
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR 
PATTERN:    EVV 0x98 V66 MAP6 MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn]  MODRM()  VL128  W0    ESIZE_16_BITS() NELEM_FULL() 
OPERANDS:    REG0=XMM_R3():rw:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 MEM0:r:vv:f16:TXT=BCASTSTR
IFORM:       VFMADD132PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512
}


# EMITTING VFMADD132PH (VFMADD132PH-256-1)
{
ICLASS:      VFMADD132PH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_256
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR 
PATTERN:    EVV 0x98 V66 MAP6 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn]  VL256  W0   
OPERANDS:    REG0=YMM_R3():rw:qq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f16 REG3=YMM_B3():r:qq:f16
IFORM:       VFMADD132PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512
}

{
ICLASS:      VFMADD132PH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_256
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR 
PATTERN:    EVV 0x98 V66 MAP6 MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn]  MODRM()  VL256  W0    ESIZE_16_BITS() NELEM_FULL() 
OPERANDS:    REG0=YMM_R3():rw:qq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f16 MEM0:r:vv:f16:TXT=BCASTSTR
IFORM:       VFMADD132PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512
}


# EMITTING VFMADD132PH (VFMADD132PH-512-1)
{
ICLASS:      VFMADD132PH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR 
PATTERN:    EVV 0x98 V66 MAP6 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn]  VL512  W0   
OPERANDS:    REG0=ZMM_R3():rw:zf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf16 REG3=ZMM_B3():r:zf16
IFORM:       VFMADD132PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512
}

{
ICLASS:      VFMADD132PH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR 
PATTERN:    EVV 0x98 V66 MAP6 MOD[0b11] MOD=3 BCRC=1 UBIT=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND()  W0   
OPERANDS:    REG0=ZMM_R3():rw:zf16:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf16 REG3=ZMM_B3():r:zf16
IFORM:       VFMADD132PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512
}

{
ICLASS:      VFMADD132PH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR 
PATTERN:    EVV 0x98 V66 MAP6 MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn]  MODRM()  VL512  W0    ESIZE_16_BITS() NELEM_FULL() 
OPERANDS:    REG0=ZMM_R3():rw:zf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf16 MEM0:r:vv:f16:TXT=BCASTSTR
IFORM:       VFMADD132PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512
}


# EMITTING VFMADD132SH (VFMADD132SH-128-1)
{
ICLASS:      VFMADD132SH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_SCALAR
EXCEPTIONS:     AVX512-E3
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR SIMD_SCALAR 
PATTERN:    EVV 0x99 V66 MAP6 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn]  FIX_ROUND_LEN128() W0   
OPERANDS:    REG0=XMM_R3():rw:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 REG3=XMM_B3():r:dq:f16
IFORM:       VFMADD132SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512
}

{
ICLASS:      VFMADD132SH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_SCALAR
EXCEPTIONS:     AVX512-E3
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR SIMD_SCALAR 
PATTERN:    EVV 0x99 V66 MAP6 MOD[0b11] MOD=3 BCRC=1 UBIT=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND()  W0   
OPERANDS:    REG0=XMM_R3():rw:dq:f16:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 REG3=XMM_B3():r:dq:f16
IFORM:       VFMADD132SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512
}

{
ICLASS:      VFMADD132SH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_SCALAR
EXCEPTIONS:     AVX512-E3
REAL_OPCODE: Y
ATTRIBUTES:  DISP8_SCALAR MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR SIMD_SCALAR 
PATTERN:    EVV 0x99 V66 MAP6 MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn] BCRC=0 MODRM()  FIX_ROUND_LEN128() W0    ESIZE_16_BITS() NELEM_SCALAR() 
OPERANDS:    REG0=XMM_R3():rw:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 MEM0:r:wrd:f16
IFORM:       VFMADD132SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512
}


# EMITTING VFMADD213PH (VFMADD213PH-128-1)
{
ICLASS:      VFMADD213PH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_128
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR 
PATTERN:    EVV 0xA8 V66 MAP6 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn]  VL128  W0   
OPERANDS:    REG0=XMM_R3():rw:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 REG3=XMM_B3():r:dq:f16
IFORM:       VFMADD213PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512
}

{
ICLASS:      VFMADD213PH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_128
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR 
PATTERN:    EVV 0xA8 V66 MAP6 MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn]  MODRM()  VL128  W0    ESIZE_16_BITS() NELEM_FULL() 
OPERANDS:    REG0=XMM_R3():rw:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 MEM0:r:vv:f16:TXT=BCASTSTR
IFORM:       VFMADD213PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512
}


# EMITTING VFMADD213PH (VFMADD213PH-256-1)
{
ICLASS:      VFMADD213PH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_256
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR 
PATTERN:    EVV 0xA8 V66 MAP6 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn]  VL256  W0   
OPERANDS:    REG0=YMM_R3():rw:qq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f16 REG3=YMM_B3():r:qq:f16
IFORM:       VFMADD213PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512
}

{
ICLASS:      VFMADD213PH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_256
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR 
PATTERN:    EVV 0xA8 V66 MAP6 MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn]  MODRM()  VL256  W0    ESIZE_16_BITS() NELEM_FULL() 
OPERANDS:    REG0=YMM_R3():rw:qq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f16 MEM0:r:vv:f16:TXT=BCASTSTR
IFORM:       VFMADD213PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512
}


# EMITTING VFMADD213PH (VFMADD213PH-512-1)
{
ICLASS:      VFMADD213PH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR 
PATTERN:    EVV 0xA8 V66 MAP6 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn]  VL512  W0   
OPERANDS:    REG0=ZMM_R3():rw:zf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf16 REG3=ZMM_B3():r:zf16
IFORM:       VFMADD213PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512
}

{
ICLASS:      VFMADD213PH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR 
PATTERN:    EVV 0xA8 V66 MAP6 MOD[0b11] MOD=3 BCRC=1 UBIT=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND()  W0   
OPERANDS:    REG0=ZMM_R3():rw:zf16:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf16 REG3=ZMM_B3():r:zf16
IFORM:       VFMADD213PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512
}

{
ICLASS:      VFMADD213PH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR 
PATTERN:    EVV 0xA8 V66 MAP6 MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn]  MODRM()  VL512  W0    ESIZE_16_BITS() NELEM_FULL() 
OPERANDS:    REG0=ZMM_R3():rw:zf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf16 MEM0:r:vv:f16:TXT=BCASTSTR
IFORM:       VFMADD213PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512
}


# EMITTING VFMADD213SH (VFMADD213SH-128-1)
{
ICLASS:      VFMADD213SH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_SCALAR
EXCEPTIONS:     AVX512-E3
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR SIMD_SCALAR 
PATTERN:    EVV 0xA9 V66 MAP6 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn]  FIX_ROUND_LEN128() W0   
OPERANDS:    REG0=XMM_R3():rw:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 REG3=XMM_B3():r:dq:f16
IFORM:       VFMADD213SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512
}

{
ICLASS:      VFMADD213SH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_SCALAR
EXCEPTIONS:     AVX512-E3
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR SIMD_SCALAR 
PATTERN:    EVV 0xA9 V66 MAP6 MOD[0b11] MOD=3 BCRC=1 UBIT=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND()  W0   
OPERANDS:    REG0=XMM_R3():rw:dq:f16:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 REG3=XMM_B3():r:dq:f16
IFORM:       VFMADD213SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512
}

{
ICLASS:      VFMADD213SH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_SCALAR
EXCEPTIONS:     AVX512-E3
REAL_OPCODE: Y
ATTRIBUTES:  DISP8_SCALAR MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR SIMD_SCALAR 
PATTERN:    EVV 0xA9 V66 MAP6 MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn] BCRC=0 MODRM()  FIX_ROUND_LEN128() W0    ESIZE_16_BITS() NELEM_SCALAR() 
OPERANDS:    REG0=XMM_R3():rw:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 MEM0:r:wrd:f16
IFORM:       VFMADD213SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512
}


# EMITTING VFMADD231PH (VFMADD231PH-128-1)
{
ICLASS:      VFMADD231PH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_128
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR 
PATTERN:    EVV 0xB8 V66 MAP6 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn]  VL128  W0   
OPERANDS:    REG0=XMM_R3():rw:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 REG3=XMM_B3():r:dq:f16
IFORM:       VFMADD231PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512
}

{
ICLASS:      VFMADD231PH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_128
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR 
PATTERN:    EVV 0xB8 V66 MAP6 MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn]  MODRM()  VL128  W0    ESIZE_16_BITS() NELEM_FULL() 
OPERANDS:    REG0=XMM_R3():rw:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 MEM0:r:vv:f16:TXT=BCASTSTR
IFORM:       VFMADD231PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512
}


# EMITTING VFMADD231PH (VFMADD231PH-256-1)
{
ICLASS:      VFMADD231PH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_256
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR 
PATTERN:    EVV 0xB8 V66 MAP6 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn]  VL256  W0   
OPERANDS:    REG0=YMM_R3():rw:qq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f16 REG3=YMM_B3():r:qq:f16
IFORM:       VFMADD231PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512
}

{
ICLASS:      VFMADD231PH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_256
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR 
PATTERN:    EVV 0xB8 V66 MAP6 MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn]  MODRM()  VL256  W0    ESIZE_16_BITS() NELEM_FULL() 
OPERANDS:    REG0=YMM_R3():rw:qq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f16 MEM0:r:vv:f16:TXT=BCASTSTR
IFORM:       VFMADD231PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512
}


# EMITTING VFMADD231PH (VFMADD231PH-512-1)
{
ICLASS:      VFMADD231PH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR 
PATTERN:    EVV 0xB8 V66 MAP6 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn]  VL512  W0   
OPERANDS:    REG0=ZMM_R3():rw:zf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf16 REG3=ZMM_B3():r:zf16
IFORM:       VFMADD231PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512
}

{
ICLASS:      VFMADD231PH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR 
PATTERN:    EVV 0xB8 V66 MAP6 MOD[0b11] MOD=3 BCRC=1 UBIT=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND()  W0   
OPERANDS:    REG0=ZMM_R3():rw:zf16:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf16 REG3=ZMM_B3():r:zf16
IFORM:       VFMADD231PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512
}

{
ICLASS:      VFMADD231PH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR 
PATTERN:    EVV 0xB8 V66 MAP6 MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn]  MODRM()  VL512  W0    ESIZE_16_BITS() NELEM_FULL() 
OPERANDS:    REG0=ZMM_R3():rw:zf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf16 MEM0:r:vv:f16:TXT=BCASTSTR
IFORM:       VFMADD231PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512
}


# EMITTING VFMADD231SH (VFMADD231SH-128-1)
{
ICLASS:      VFMADD231SH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_SCALAR
EXCEPTIONS:     AVX512-E3
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR SIMD_SCALAR 
PATTERN:    EVV 0xB9 V66 MAP6 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn]  FIX_ROUND_LEN128() W0   
OPERANDS:    REG0=XMM_R3():rw:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 REG3=XMM_B3():r:dq:f16
IFORM:       VFMADD231SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512
}

{
ICLASS:      VFMADD231SH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_SCALAR
EXCEPTIONS:     AVX512-E3
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR SIMD_SCALAR 
PATTERN:    EVV 0xB9 V66 MAP6 MOD[0b11] MOD=3 BCRC=1 UBIT=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND()  W0   
OPERANDS:    REG0=XMM_R3():rw:dq:f16:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 REG3=XMM_B3():r:dq:f16
IFORM:       VFMADD231SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512
}

{
ICLASS:      VFMADD231SH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_SCALAR
EXCEPTIONS:     AVX512-E3
REAL_OPCODE: Y
ATTRIBUTES:  DISP8_SCALAR MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR SIMD_SCALAR 
PATTERN:    EVV 0xB9 V66 MAP6 MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn] BCRC=0 MODRM()  FIX_ROUND_LEN128() W0    ESIZE_16_BITS() NELEM_SCALAR() 
OPERANDS:    REG0=XMM_R3():rw:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 MEM0:r:wrd:f16
IFORM:       VFMADD231SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512
}


# EMITTING VFMADDCPH (VFMADDCPH-128-1)
{
ICLASS:      VFMADDCPH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_128
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR NO_SRC_DEST_MATCH 
PATTERN:    EVV 0x56 VF3 MAP6 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn]  VL128  W0   
OPERANDS:    REG0=XMM_R3():rw:dq:2f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:2f16 REG3=XMM_B3():r:dq:2f16
IFORM:       VFMADDCPH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512
}

{
ICLASS:      VFMADDCPH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_128
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR NO_SRC_DEST_MATCH 
PATTERN:    EVV 0x56 VF3 MAP6 MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn]  MODRM()  VL128  W0    ESIZE_32_BITS() NELEM_FULL() 
OPERANDS:    REG0=XMM_R3():rw:dq:2f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:2f16 MEM0:r:vv:2f16:TXT=BCASTSTR
IFORM:       VFMADDCPH_XMM2f16_MASKmskw_XMM2f16_MEM2f16_AVX512
}


# EMITTING VFMADDCPH (VFMADDCPH-256-1)
{
ICLASS:      VFMADDCPH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_256
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR NO_SRC_DEST_MATCH 
PATTERN:    EVV 0x56 VF3 MAP6 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn]  VL256  W0   
OPERANDS:    REG0=YMM_R3():rw:qq:2f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:2f16 REG3=YMM_B3():r:qq:2f16
IFORM:       VFMADDCPH_YMM2f16_MASKmskw_YMM2f16_YMM2f16_AVX512
}

{
ICLASS:      VFMADDCPH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_256
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR NO_SRC_DEST_MATCH 
PATTERN:    EVV 0x56 VF3 MAP6 MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn]  MODRM()  VL256  W0    ESIZE_32_BITS() NELEM_FULL() 
OPERANDS:    REG0=YMM_R3():rw:qq:2f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:2f16 MEM0:r:vv:2f16:TXT=BCASTSTR
IFORM:       VFMADDCPH_YMM2f16_MASKmskw_YMM2f16_MEM2f16_AVX512
}


# EMITTING VFMADDCPH (VFMADDCPH-512-1)
{
ICLASS:      VFMADDCPH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_512
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR NO_SRC_DEST_MATCH 
PATTERN:    EVV 0x56 VF3 MAP6 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn]  VL512  W0   
OPERANDS:    REG0=ZMM_R3():rw:z2f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:z2f16 REG3=ZMM_B3():r:z2f16
IFORM:       VFMADDCPH_ZMM2f16_MASKmskw_ZMM2f16_ZMM2f16_AVX512
}

{
ICLASS:      VFMADDCPH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_512
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR NO_SRC_DEST_MATCH 
PATTERN:    EVV 0x56 VF3 MAP6 MOD[0b11] MOD=3 BCRC=1 UBIT=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND()  W0   
OPERANDS:    REG0=ZMM_R3():rw:z2f16:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:z2f16 REG3=ZMM_B3():r:z2f16
IFORM:       VFMADDCPH_ZMM2f16_MASKmskw_ZMM2f16_ZMM2f16_AVX512
}

{
ICLASS:      VFMADDCPH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_512
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR NO_SRC_DEST_MATCH 
PATTERN:    EVV 0x56 VF3 MAP6 MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn]  MODRM()  VL512  W0    ESIZE_32_BITS() NELEM_FULL() 
OPERANDS:    REG0=ZMM_R3():rw:z2f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:z2f16 MEM0:r:vv:2f16:TXT=BCASTSTR
IFORM:       VFMADDCPH_ZMM2f16_MASKmskw_ZMM2f16_MEM2f16_AVX512
}


# EMITTING VFMADDCSH (VFMADDCSH-128-1)
{
ICLASS:      VFMADDCSH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_SCALAR
EXCEPTIONS:     AVX512-E10
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR NO_SRC_DEST_MATCH SIMD_SCALAR 
PATTERN:    EVV 0x57 VF3 MAP6 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn]  FIX_ROUND_LEN128() W0   
OPERANDS:    REG0=XMM_R3():rw:dq:2f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:2f16 REG3=XMM_B3():r:dq:2f16
IFORM:       VFMADDCSH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512
}

{
ICLASS:      VFMADDCSH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_SCALAR
EXCEPTIONS:     AVX512-E10
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR NO_SRC_DEST_MATCH SIMD_SCALAR 
PATTERN:    EVV 0x57 VF3 MAP6 MOD[0b11] MOD=3 BCRC=1 UBIT=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND()  W0   
OPERANDS:    REG0=XMM_R3():rw:dq:2f16:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:2f16 REG3=XMM_B3():r:dq:2f16
IFORM:       VFMADDCSH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512
}

{
ICLASS:      VFMADDCSH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_SCALAR
EXCEPTIONS:     AVX512-E10
REAL_OPCODE: Y
ATTRIBUTES:  DISP8_SCALAR MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR NO_SRC_DEST_MATCH SIMD_SCALAR 
PATTERN:    EVV 0x57 VF3 MAP6 MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn] BCRC=0 MODRM()  FIX_ROUND_LEN128() W0    ESIZE_32_BITS() NELEM_SCALAR() 
OPERANDS:    REG0=XMM_R3():rw:dq:2f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:2f16 MEM0:r:d:2f16
IFORM:       VFMADDCSH_XMM2f16_MASKmskw_XMM2f16_MEM2f16_AVX512
}


# EMITTING VFMADDSUB132PH (VFMADDSUB132PH-128-1)
{
ICLASS:      VFMADDSUB132PH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_128
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR 
PATTERN:    EVV 0x96 V66 MAP6 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn]  VL128  W0   
OPERANDS:    REG0=XMM_R3():rw:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 REG3=XMM_B3():r:dq:f16
IFORM:       VFMADDSUB132PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512
}

{
ICLASS:      VFMADDSUB132PH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_128
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR 
PATTERN:    EVV 0x96 V66 MAP6 MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn]  MODRM()  VL128  W0    ESIZE_16_BITS() NELEM_FULL() 
OPERANDS:    REG0=XMM_R3():rw:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 MEM0:r:vv:f16:TXT=BCASTSTR
IFORM:       VFMADDSUB132PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512
}


# EMITTING VFMADDSUB132PH (VFMADDSUB132PH-256-1)
{
ICLASS:      VFMADDSUB132PH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_256
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR 
PATTERN:    EVV 0x96 V66 MAP6 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn]  VL256  W0   
OPERANDS:    REG0=YMM_R3():rw:qq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f16 REG3=YMM_B3():r:qq:f16
IFORM:       VFMADDSUB132PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512
}

{
ICLASS:      VFMADDSUB132PH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_256
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR 
PATTERN:    EVV 0x96 V66 MAP6 MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn]  MODRM()  VL256  W0    ESIZE_16_BITS() NELEM_FULL() 
OPERANDS:    REG0=YMM_R3():rw:qq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f16 MEM0:r:vv:f16:TXT=BCASTSTR
IFORM:       VFMADDSUB132PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512
}


# EMITTING VFMADDSUB132PH (VFMADDSUB132PH-512-1)
{
ICLASS:      VFMADDSUB132PH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR 
PATTERN:    EVV 0x96 V66 MAP6 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn]  VL512  W0   
OPERANDS:    REG0=ZMM_R3():rw:zf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf16 REG3=ZMM_B3():r:zf16
IFORM:       VFMADDSUB132PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512
}

{
ICLASS:      VFMADDSUB132PH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR 
PATTERN:    EVV 0x96 V66 MAP6 MOD[0b11] MOD=3 BCRC=1 UBIT=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND()  W0   
OPERANDS:    REG0=ZMM_R3():rw:zf16:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf16 REG3=ZMM_B3():r:zf16
IFORM:       VFMADDSUB132PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512
}

{
ICLASS:      VFMADDSUB132PH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR 
PATTERN:    EVV 0x96 V66 MAP6 MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn]  MODRM()  VL512  W0    ESIZE_16_BITS() NELEM_FULL() 
OPERANDS:    REG0=ZMM_R3():rw:zf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf16 MEM0:r:vv:f16:TXT=BCASTSTR
IFORM:       VFMADDSUB132PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512
}


# EMITTING VFMADDSUB213PH (VFMADDSUB213PH-128-1)
{
ICLASS:      VFMADDSUB213PH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_128
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR 
PATTERN:    EVV 0xA6 V66 MAP6 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn]  VL128  W0   
OPERANDS:    REG0=XMM_R3():rw:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 REG3=XMM_B3():r:dq:f16
IFORM:       VFMADDSUB213PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512
}

{
ICLASS:      VFMADDSUB213PH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_128
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR 
PATTERN:    EVV 0xA6 V66 MAP6 MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn]  MODRM()  VL128  W0    ESIZE_16_BITS() NELEM_FULL() 
OPERANDS:    REG0=XMM_R3():rw:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 MEM0:r:vv:f16:TXT=BCASTSTR
IFORM:       VFMADDSUB213PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512
}


# EMITTING VFMADDSUB213PH (VFMADDSUB213PH-256-1)
{
ICLASS:      VFMADDSUB213PH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_256
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR 
PATTERN:    EVV 0xA6 V66 MAP6 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn]  VL256  W0   
OPERANDS:    REG0=YMM_R3():rw:qq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f16 REG3=YMM_B3():r:qq:f16
IFORM:       VFMADDSUB213PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512
}

{
ICLASS:      VFMADDSUB213PH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_256
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR 
PATTERN:    EVV 0xA6 V66 MAP6 MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn]  MODRM()  VL256  W0    ESIZE_16_BITS() NELEM_FULL() 
OPERANDS:    REG0=YMM_R3():rw:qq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f16 MEM0:r:vv:f16:TXT=BCASTSTR
IFORM:       VFMADDSUB213PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512
}


# EMITTING VFMADDSUB213PH (VFMADDSUB213PH-512-1)
{
ICLASS:      VFMADDSUB213PH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR 
PATTERN:    EVV 0xA6 V66 MAP6 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn]  VL512  W0   
OPERANDS:    REG0=ZMM_R3():rw:zf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf16 REG3=ZMM_B3():r:zf16
IFORM:       VFMADDSUB213PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512
}

{
ICLASS:      VFMADDSUB213PH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR 
PATTERN:    EVV 0xA6 V66 MAP6 MOD[0b11] MOD=3 BCRC=1 UBIT=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND()  W0   
OPERANDS:    REG0=ZMM_R3():rw:zf16:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf16 REG3=ZMM_B3():r:zf16
IFORM:       VFMADDSUB213PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512
}

{
ICLASS:      VFMADDSUB213PH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR 
PATTERN:    EVV 0xA6 V66 MAP6 MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn]  MODRM()  VL512  W0    ESIZE_16_BITS() NELEM_FULL() 
OPERANDS:    REG0=ZMM_R3():rw:zf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf16 MEM0:r:vv:f16:TXT=BCASTSTR
IFORM:       VFMADDSUB213PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512
}


# EMITTING VFMADDSUB231PH (VFMADDSUB231PH-128-1)
{
ICLASS:      VFMADDSUB231PH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_128
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR 
PATTERN:    EVV 0xB6 V66 MAP6 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn]  VL128  W0   
OPERANDS:    REG0=XMM_R3():rw:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 REG3=XMM_B3():r:dq:f16
IFORM:       VFMADDSUB231PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512
}

{
ICLASS:      VFMADDSUB231PH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_128
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR 
PATTERN:    EVV 0xB6 V66 MAP6 MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn]  MODRM()  VL128  W0    ESIZE_16_BITS() NELEM_FULL() 
OPERANDS:    REG0=XMM_R3():rw:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 MEM0:r:vv:f16:TXT=BCASTSTR
IFORM:       VFMADDSUB231PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512
}


# EMITTING VFMADDSUB231PH (VFMADDSUB231PH-256-1)
{
ICLASS:      VFMADDSUB231PH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_256
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR 
PATTERN:    EVV 0xB6 V66 MAP6 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn]  VL256  W0   
OPERANDS:    REG0=YMM_R3():rw:qq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f16 REG3=YMM_B3():r:qq:f16
IFORM:       VFMADDSUB231PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512
}

{
ICLASS:      VFMADDSUB231PH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_256
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR 
PATTERN:    EVV 0xB6 V66 MAP6 MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn]  MODRM()  VL256  W0    ESIZE_16_BITS() NELEM_FULL() 
OPERANDS:    REG0=YMM_R3():rw:qq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f16 MEM0:r:vv:f16:TXT=BCASTSTR
IFORM:       VFMADDSUB231PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512
}


# EMITTING VFMADDSUB231PH (VFMADDSUB231PH-512-1)
{
ICLASS:      VFMADDSUB231PH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR 
PATTERN:    EVV 0xB6 V66 MAP6 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn]  VL512  W0   
OPERANDS:    REG0=ZMM_R3():rw:zf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf16 REG3=ZMM_B3():r:zf16
IFORM:       VFMADDSUB231PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512
}

{
ICLASS:      VFMADDSUB231PH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR 
PATTERN:    EVV 0xB6 V66 MAP6 MOD[0b11] MOD=3 BCRC=1 UBIT=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND()  W0   
OPERANDS:    REG0=ZMM_R3():rw:zf16:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf16 REG3=ZMM_B3():r:zf16
IFORM:       VFMADDSUB231PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512
}

{
ICLASS:      VFMADDSUB231PH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR 
PATTERN:    EVV 0xB6 V66 MAP6 MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn]  MODRM()  VL512  W0    ESIZE_16_BITS() NELEM_FULL() 
OPERANDS:    REG0=ZMM_R3():rw:zf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf16 MEM0:r:vv:f16:TXT=BCASTSTR
IFORM:       VFMADDSUB231PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512
}


# EMITTING VFMSUB132PH (VFMSUB132PH-128-1)
{
ICLASS:      VFMSUB132PH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_128
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR 
PATTERN:    EVV 0x9A V66 MAP6 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn]  VL128  W0   
OPERANDS:    REG0=XMM_R3():rw:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 REG3=XMM_B3():r:dq:f16
IFORM:       VFMSUB132PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512
}

{
ICLASS:      VFMSUB132PH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_128
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR 
PATTERN:    EVV 0x9A V66 MAP6 MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn]  MODRM()  VL128  W0    ESIZE_16_BITS() NELEM_FULL() 
OPERANDS:    REG0=XMM_R3():rw:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 MEM0:r:vv:f16:TXT=BCASTSTR
IFORM:       VFMSUB132PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512
}


# EMITTING VFMSUB132PH (VFMSUB132PH-256-1)
{
ICLASS:      VFMSUB132PH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_256
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR 
PATTERN:    EVV 0x9A V66 MAP6 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn]  VL256  W0   
OPERANDS:    REG0=YMM_R3():rw:qq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f16 REG3=YMM_B3():r:qq:f16
IFORM:       VFMSUB132PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512
}

{
ICLASS:      VFMSUB132PH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_256
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR 
PATTERN:    EVV 0x9A V66 MAP6 MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn]  MODRM()  VL256  W0    ESIZE_16_BITS() NELEM_FULL() 
OPERANDS:    REG0=YMM_R3():rw:qq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f16 MEM0:r:vv:f16:TXT=BCASTSTR
IFORM:       VFMSUB132PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512
}


# EMITTING VFMSUB132PH (VFMSUB132PH-512-1)
{
ICLASS:      VFMSUB132PH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR 
PATTERN:    EVV 0x9A V66 MAP6 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn]  VL512  W0   
OPERANDS:    REG0=ZMM_R3():rw:zf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf16 REG3=ZMM_B3():r:zf16
IFORM:       VFMSUB132PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512
}

{
ICLASS:      VFMSUB132PH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR 
PATTERN:    EVV 0x9A V66 MAP6 MOD[0b11] MOD=3 BCRC=1 UBIT=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND()  W0   
OPERANDS:    REG0=ZMM_R3():rw:zf16:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf16 REG3=ZMM_B3():r:zf16
IFORM:       VFMSUB132PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512
}

{
ICLASS:      VFMSUB132PH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR 
PATTERN:    EVV 0x9A V66 MAP6 MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn]  MODRM()  VL512  W0    ESIZE_16_BITS() NELEM_FULL() 
OPERANDS:    REG0=ZMM_R3():rw:zf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf16 MEM0:r:vv:f16:TXT=BCASTSTR
IFORM:       VFMSUB132PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512
}


# EMITTING VFMSUB132SH (VFMSUB132SH-128-1)
{
ICLASS:      VFMSUB132SH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_SCALAR
EXCEPTIONS:     AVX512-E3
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR SIMD_SCALAR 
PATTERN:    EVV 0x9B V66 MAP6 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn]  FIX_ROUND_LEN128() W0   
OPERANDS:    REG0=XMM_R3():rw:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 REG3=XMM_B3():r:dq:f16
IFORM:       VFMSUB132SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512
}

{
ICLASS:      VFMSUB132SH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_SCALAR
EXCEPTIONS:     AVX512-E3
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR SIMD_SCALAR 
PATTERN:    EVV 0x9B V66 MAP6 MOD[0b11] MOD=3 BCRC=1 UBIT=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND()  W0   
OPERANDS:    REG0=XMM_R3():rw:dq:f16:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 REG3=XMM_B3():r:dq:f16
IFORM:       VFMSUB132SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512
}

{
ICLASS:      VFMSUB132SH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_SCALAR
EXCEPTIONS:     AVX512-E3
REAL_OPCODE: Y
ATTRIBUTES:  DISP8_SCALAR MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR SIMD_SCALAR 
PATTERN:    EVV 0x9B V66 MAP6 MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn] BCRC=0 MODRM()  FIX_ROUND_LEN128() W0    ESIZE_16_BITS() NELEM_SCALAR() 
OPERANDS:    REG0=XMM_R3():rw:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 MEM0:r:wrd:f16
IFORM:       VFMSUB132SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512
}


# EMITTING VFMSUB213PH (VFMSUB213PH-128-1)
{
ICLASS:      VFMSUB213PH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_128
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR 
PATTERN:    EVV 0xAA V66 MAP6 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn]  VL128  W0   
OPERANDS:    REG0=XMM_R3():rw:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 REG3=XMM_B3():r:dq:f16
IFORM:       VFMSUB213PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512
}

{
ICLASS:      VFMSUB213PH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_128
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR 
PATTERN:    EVV 0xAA V66 MAP6 MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn]  MODRM()  VL128  W0    ESIZE_16_BITS() NELEM_FULL() 
OPERANDS:    REG0=XMM_R3():rw:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 MEM0:r:vv:f16:TXT=BCASTSTR
IFORM:       VFMSUB213PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512
}


# EMITTING VFMSUB213PH (VFMSUB213PH-256-1)
{
ICLASS:      VFMSUB213PH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_256
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR 
PATTERN:    EVV 0xAA V66 MAP6 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn]  VL256  W0   
OPERANDS:    REG0=YMM_R3():rw:qq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f16 REG3=YMM_B3():r:qq:f16
IFORM:       VFMSUB213PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512
}

{
ICLASS:      VFMSUB213PH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_256
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR 
PATTERN:    EVV 0xAA V66 MAP6 MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn]  MODRM()  VL256  W0    ESIZE_16_BITS() NELEM_FULL() 
OPERANDS:    REG0=YMM_R3():rw:qq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f16 MEM0:r:vv:f16:TXT=BCASTSTR
IFORM:       VFMSUB213PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512
}


# EMITTING VFMSUB213PH (VFMSUB213PH-512-1)
{
ICLASS:      VFMSUB213PH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR 
PATTERN:    EVV 0xAA V66 MAP6 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn]  VL512  W0   
OPERANDS:    REG0=ZMM_R3():rw:zf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf16 REG3=ZMM_B3():r:zf16
IFORM:       VFMSUB213PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512
}

{
ICLASS:      VFMSUB213PH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR 
PATTERN:    EVV 0xAA V66 MAP6 MOD[0b11] MOD=3 BCRC=1 UBIT=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND()  W0   
OPERANDS:    REG0=ZMM_R3():rw:zf16:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf16 REG3=ZMM_B3():r:zf16
IFORM:       VFMSUB213PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512
}

{
ICLASS:      VFMSUB213PH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR 
PATTERN:    EVV 0xAA V66 MAP6 MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn]  MODRM()  VL512  W0    ESIZE_16_BITS() NELEM_FULL() 
OPERANDS:    REG0=ZMM_R3():rw:zf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf16 MEM0:r:vv:f16:TXT=BCASTSTR
IFORM:       VFMSUB213PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512
}


# EMITTING VFMSUB213SH (VFMSUB213SH-128-1)
{
ICLASS:      VFMSUB213SH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_SCALAR
EXCEPTIONS:     AVX512-E3
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR SIMD_SCALAR 
PATTERN:    EVV 0xAB V66 MAP6 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn]  FIX_ROUND_LEN128() W0   
OPERANDS:    REG0=XMM_R3():rw:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 REG3=XMM_B3():r:dq:f16
IFORM:       VFMSUB213SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512
}

{
ICLASS:      VFMSUB213SH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_SCALAR
EXCEPTIONS:     AVX512-E3
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR SIMD_SCALAR 
PATTERN:    EVV 0xAB V66 MAP6 MOD[0b11] MOD=3 BCRC=1 UBIT=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND()  W0   
OPERANDS:    REG0=XMM_R3():rw:dq:f16:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 REG3=XMM_B3():r:dq:f16
IFORM:       VFMSUB213SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512
}

{
ICLASS:      VFMSUB213SH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_SCALAR
EXCEPTIONS:     AVX512-E3
REAL_OPCODE: Y
ATTRIBUTES:  DISP8_SCALAR MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR SIMD_SCALAR 
PATTERN:    EVV 0xAB V66 MAP6 MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn] BCRC=0 MODRM()  FIX_ROUND_LEN128() W0    ESIZE_16_BITS() NELEM_SCALAR() 
OPERANDS:    REG0=XMM_R3():rw:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 MEM0:r:wrd:f16
IFORM:       VFMSUB213SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512
}


# EMITTING VFMSUB231PH (VFMSUB231PH-128-1)
{
ICLASS:      VFMSUB231PH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_128
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR 
PATTERN:    EVV 0xBA V66 MAP6 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn]  VL128  W0   
OPERANDS:    REG0=XMM_R3():rw:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 REG3=XMM_B3():r:dq:f16
IFORM:       VFMSUB231PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512
}

{
ICLASS:      VFMSUB231PH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_128
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR 
PATTERN:    EVV 0xBA V66 MAP6 MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn]  MODRM()  VL128  W0    ESIZE_16_BITS() NELEM_FULL() 
OPERANDS:    REG0=XMM_R3():rw:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 MEM0:r:vv:f16:TXT=BCASTSTR
IFORM:       VFMSUB231PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512
}


# EMITTING VFMSUB231PH (VFMSUB231PH-256-1)
{
ICLASS:      VFMSUB231PH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_256
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR 
PATTERN:    EVV 0xBA V66 MAP6 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn]  VL256  W0   
OPERANDS:    REG0=YMM_R3():rw:qq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f16 REG3=YMM_B3():r:qq:f16
IFORM:       VFMSUB231PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512
}

{
ICLASS:      VFMSUB231PH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_256
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR 
PATTERN:    EVV 0xBA V66 MAP6 MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn]  MODRM()  VL256  W0    ESIZE_16_BITS() NELEM_FULL() 
OPERANDS:    REG0=YMM_R3():rw:qq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f16 MEM0:r:vv:f16:TXT=BCASTSTR
IFORM:       VFMSUB231PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512
}


# EMITTING VFMSUB231PH (VFMSUB231PH-512-1)
{
ICLASS:      VFMSUB231PH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR 
PATTERN:    EVV 0xBA V66 MAP6 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn]  VL512  W0   
OPERANDS:    REG0=ZMM_R3():rw:zf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf16 REG3=ZMM_B3():r:zf16
IFORM:       VFMSUB231PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512
}

{
ICLASS:      VFMSUB231PH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR 
PATTERN:    EVV 0xBA V66 MAP6 MOD[0b11] MOD=3 BCRC=1 UBIT=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND()  W0   
OPERANDS:    REG0=ZMM_R3():rw:zf16:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf16 REG3=ZMM_B3():r:zf16
IFORM:       VFMSUB231PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512
}

{
ICLASS:      VFMSUB231PH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR 
PATTERN:    EVV 0xBA V66 MAP6 MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn]  MODRM()  VL512  W0    ESIZE_16_BITS() NELEM_FULL() 
OPERANDS:    REG0=ZMM_R3():rw:zf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf16 MEM0:r:vv:f16:TXT=BCASTSTR
IFORM:       VFMSUB231PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512
}


# EMITTING VFMSUB231SH (VFMSUB231SH-128-1)
{
ICLASS:      VFMSUB231SH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_SCALAR
EXCEPTIONS:     AVX512-E3
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR SIMD_SCALAR 
PATTERN:    EVV 0xBB V66 MAP6 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn]  FIX_ROUND_LEN128() W0   
OPERANDS:    REG0=XMM_R3():rw:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 REG3=XMM_B3():r:dq:f16
IFORM:       VFMSUB231SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512
}

{
ICLASS:      VFMSUB231SH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_SCALAR
EXCEPTIONS:     AVX512-E3
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR SIMD_SCALAR 
PATTERN:    EVV 0xBB V66 MAP6 MOD[0b11] MOD=3 BCRC=1 UBIT=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND()  W0   
OPERANDS:    REG0=XMM_R3():rw:dq:f16:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 REG3=XMM_B3():r:dq:f16
IFORM:       VFMSUB231SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512
}

{
ICLASS:      VFMSUB231SH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_SCALAR
EXCEPTIONS:     AVX512-E3
REAL_OPCODE: Y
ATTRIBUTES:  DISP8_SCALAR MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR SIMD_SCALAR 
PATTERN:    EVV 0xBB V66 MAP6 MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn] BCRC=0 MODRM()  FIX_ROUND_LEN128() W0    ESIZE_16_BITS() NELEM_SCALAR() 
OPERANDS:    REG0=XMM_R3():rw:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 MEM0:r:wrd:f16
IFORM:       VFMSUB231SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512
}


# EMITTING VFMSUBADD132PH (VFMSUBADD132PH-128-1)
{
ICLASS:      VFMSUBADD132PH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_128
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR 
PATTERN:    EVV 0x97 V66 MAP6 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn]  VL128  W0   
OPERANDS:    REG0=XMM_R3():rw:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 REG3=XMM_B3():r:dq:f16
IFORM:       VFMSUBADD132PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512
}

{
ICLASS:      VFMSUBADD132PH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_128
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR 
PATTERN:    EVV 0x97 V66 MAP6 MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn]  MODRM()  VL128  W0    ESIZE_16_BITS() NELEM_FULL() 
OPERANDS:    REG0=XMM_R3():rw:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 MEM0:r:vv:f16:TXT=BCASTSTR
IFORM:       VFMSUBADD132PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512
}


# EMITTING VFMSUBADD132PH (VFMSUBADD132PH-256-1)
{
ICLASS:      VFMSUBADD132PH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_256
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR 
PATTERN:    EVV 0x97 V66 MAP6 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn]  VL256  W0   
OPERANDS:    REG0=YMM_R3():rw:qq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f16 REG3=YMM_B3():r:qq:f16
IFORM:       VFMSUBADD132PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512
}

{
ICLASS:      VFMSUBADD132PH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_256
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR 
PATTERN:    EVV 0x97 V66 MAP6 MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn]  MODRM()  VL256  W0    ESIZE_16_BITS() NELEM_FULL() 
OPERANDS:    REG0=YMM_R3():rw:qq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f16 MEM0:r:vv:f16:TXT=BCASTSTR
IFORM:       VFMSUBADD132PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512
}


# EMITTING VFMSUBADD132PH (VFMSUBADD132PH-512-1)
{
ICLASS:      VFMSUBADD132PH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR 
PATTERN:    EVV 0x97 V66 MAP6 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn]  VL512  W0   
OPERANDS:    REG0=ZMM_R3():rw:zf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf16 REG3=ZMM_B3():r:zf16
IFORM:       VFMSUBADD132PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512
}

{
ICLASS:      VFMSUBADD132PH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR 
PATTERN:    EVV 0x97 V66 MAP6 MOD[0b11] MOD=3 BCRC=1 UBIT=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND()  W0   
OPERANDS:    REG0=ZMM_R3():rw:zf16:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf16 REG3=ZMM_B3():r:zf16
IFORM:       VFMSUBADD132PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512
}

{
ICLASS:      VFMSUBADD132PH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR 
PATTERN:    EVV 0x97 V66 MAP6 MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn]  MODRM()  VL512  W0    ESIZE_16_BITS() NELEM_FULL() 
OPERANDS:    REG0=ZMM_R3():rw:zf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf16 MEM0:r:vv:f16:TXT=BCASTSTR
IFORM:       VFMSUBADD132PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512
}


# EMITTING VFMSUBADD213PH (VFMSUBADD213PH-128-1)
{
ICLASS:      VFMSUBADD213PH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_128
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR 
PATTERN:    EVV 0xA7 V66 MAP6 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn]  VL128  W0   
OPERANDS:    REG0=XMM_R3():rw:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 REG3=XMM_B3():r:dq:f16
IFORM:       VFMSUBADD213PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512
}

{
ICLASS:      VFMSUBADD213PH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_128
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR 
PATTERN:    EVV 0xA7 V66 MAP6 MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn]  MODRM()  VL128  W0    ESIZE_16_BITS() NELEM_FULL() 
OPERANDS:    REG0=XMM_R3():rw:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 MEM0:r:vv:f16:TXT=BCASTSTR
IFORM:       VFMSUBADD213PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512
}


# EMITTING VFMSUBADD213PH (VFMSUBADD213PH-256-1)
{
ICLASS:      VFMSUBADD213PH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_256
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR 
PATTERN:    EVV 0xA7 V66 MAP6 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn]  VL256  W0   
OPERANDS:    REG0=YMM_R3():rw:qq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f16 REG3=YMM_B3():r:qq:f16
IFORM:       VFMSUBADD213PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512
}

{
ICLASS:      VFMSUBADD213PH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_256
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR 
PATTERN:    EVV 0xA7 V66 MAP6 MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn]  MODRM()  VL256  W0    ESIZE_16_BITS() NELEM_FULL() 
OPERANDS:    REG0=YMM_R3():rw:qq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f16 MEM0:r:vv:f16:TXT=BCASTSTR
IFORM:       VFMSUBADD213PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512
}


# EMITTING VFMSUBADD213PH (VFMSUBADD213PH-512-1)
{
ICLASS:      VFMSUBADD213PH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR 
PATTERN:    EVV 0xA7 V66 MAP6 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn]  VL512  W0   
OPERANDS:    REG0=ZMM_R3():rw:zf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf16 REG3=ZMM_B3():r:zf16
IFORM:       VFMSUBADD213PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512
}

{
ICLASS:      VFMSUBADD213PH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR 
PATTERN:    EVV 0xA7 V66 MAP6 MOD[0b11] MOD=3 BCRC=1 UBIT=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND()  W0   
OPERANDS:    REG0=ZMM_R3():rw:zf16:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf16 REG3=ZMM_B3():r:zf16
IFORM:       VFMSUBADD213PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512
}

{
ICLASS:      VFMSUBADD213PH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR 
PATTERN:    EVV 0xA7 V66 MAP6 MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn]  MODRM()  VL512  W0    ESIZE_16_BITS() NELEM_FULL() 
OPERANDS:    REG0=ZMM_R3():rw:zf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf16 MEM0:r:vv:f16:TXT=BCASTSTR
IFORM:       VFMSUBADD213PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512
}


# EMITTING VFMSUBADD231PH (VFMSUBADD231PH-128-1)
{
ICLASS:      VFMSUBADD231PH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_128
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR 
PATTERN:    EVV 0xB7 V66 MAP6 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn]  VL128  W0   
OPERANDS:    REG0=XMM_R3():rw:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 REG3=XMM_B3():r:dq:f16
IFORM:       VFMSUBADD231PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512
}

{
ICLASS:      VFMSUBADD231PH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_128
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR 
PATTERN:    EVV 0xB7 V66 MAP6 MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn]  MODRM()  VL128  W0    ESIZE_16_BITS() NELEM_FULL() 
OPERANDS:    REG0=XMM_R3():rw:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 MEM0:r:vv:f16:TXT=BCASTSTR
IFORM:       VFMSUBADD231PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512
}


# EMITTING VFMSUBADD231PH (VFMSUBADD231PH-256-1)
{
ICLASS:      VFMSUBADD231PH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_256
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR 
PATTERN:    EVV 0xB7 V66 MAP6 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn]  VL256  W0   
OPERANDS:    REG0=YMM_R3():rw:qq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f16 REG3=YMM_B3():r:qq:f16
IFORM:       VFMSUBADD231PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512
}

{
ICLASS:      VFMSUBADD231PH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_256
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR 
PATTERN:    EVV 0xB7 V66 MAP6 MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn]  MODRM()  VL256  W0    ESIZE_16_BITS() NELEM_FULL() 
OPERANDS:    REG0=YMM_R3():rw:qq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f16 MEM0:r:vv:f16:TXT=BCASTSTR
IFORM:       VFMSUBADD231PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512
}


# EMITTING VFMSUBADD231PH (VFMSUBADD231PH-512-1)
{
ICLASS:      VFMSUBADD231PH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR 
PATTERN:    EVV 0xB7 V66 MAP6 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn]  VL512  W0   
OPERANDS:    REG0=ZMM_R3():rw:zf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf16 REG3=ZMM_B3():r:zf16
IFORM:       VFMSUBADD231PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512
}

{
ICLASS:      VFMSUBADD231PH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR 
PATTERN:    EVV 0xB7 V66 MAP6 MOD[0b11] MOD=3 BCRC=1 UBIT=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND()  W0   
OPERANDS:    REG0=ZMM_R3():rw:zf16:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf16 REG3=ZMM_B3():r:zf16
IFORM:       VFMSUBADD231PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512
}

{
ICLASS:      VFMSUBADD231PH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR 
PATTERN:    EVV 0xB7 V66 MAP6 MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn]  MODRM()  VL512  W0    ESIZE_16_BITS() NELEM_FULL() 
OPERANDS:    REG0=ZMM_R3():rw:zf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf16 MEM0:r:vv:f16:TXT=BCASTSTR
IFORM:       VFMSUBADD231PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512
}


# EMITTING VFMULCPH (VFMULCPH-128-1)
{
ICLASS:      VFMULCPH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_128
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR NO_SRC_DEST_MATCH 
PATTERN:    EVV 0xD6 VF3 MAP6 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn]  VL128  W0   
OPERANDS:    REG0=XMM_R3():w:dq:2f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:2f16 REG3=XMM_B3():r:dq:2f16
IFORM:       VFMULCPH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512
}

{
ICLASS:      VFMULCPH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_128
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR NO_SRC_DEST_MATCH 
PATTERN:    EVV 0xD6 VF3 MAP6 MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn]  MODRM()  VL128  W0    ESIZE_32_BITS() NELEM_FULL() 
OPERANDS:    REG0=XMM_R3():w:dq:2f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:2f16 MEM0:r:vv:2f16:TXT=BCASTSTR
IFORM:       VFMULCPH_XMM2f16_MASKmskw_XMM2f16_MEM2f16_AVX512
}


# EMITTING VFMULCPH (VFMULCPH-256-1)
{
ICLASS:      VFMULCPH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_256
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR NO_SRC_DEST_MATCH 
PATTERN:    EVV 0xD6 VF3 MAP6 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn]  VL256  W0   
OPERANDS:    REG0=YMM_R3():w:qq:2f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:2f16 REG3=YMM_B3():r:qq:2f16
IFORM:       VFMULCPH_YMM2f16_MASKmskw_YMM2f16_YMM2f16_AVX512
}

{
ICLASS:      VFMULCPH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_256
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR NO_SRC_DEST_MATCH 
PATTERN:    EVV 0xD6 VF3 MAP6 MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn]  MODRM()  VL256  W0    ESIZE_32_BITS() NELEM_FULL() 
OPERANDS:    REG0=YMM_R3():w:qq:2f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:2f16 MEM0:r:vv:2f16:TXT=BCASTSTR
IFORM:       VFMULCPH_YMM2f16_MASKmskw_YMM2f16_MEM2f16_AVX512
}


# EMITTING VFMULCPH (VFMULCPH-512-1)
{
ICLASS:      VFMULCPH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_512
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR NO_SRC_DEST_MATCH 
PATTERN:    EVV 0xD6 VF3 MAP6 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn]  VL512  W0   
OPERANDS:    REG0=ZMM_R3():w:z2f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:z2f16 REG3=ZMM_B3():r:z2f16
IFORM:       VFMULCPH_ZMM2f16_MASKmskw_ZMM2f16_ZMM2f16_AVX512
}

{
ICLASS:      VFMULCPH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_512
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR NO_SRC_DEST_MATCH 
PATTERN:    EVV 0xD6 VF3 MAP6 MOD[0b11] MOD=3 BCRC=1 UBIT=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND()  W0   
OPERANDS:    REG0=ZMM_R3():w:z2f16:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:z2f16 REG3=ZMM_B3():r:z2f16
IFORM:       VFMULCPH_ZMM2f16_MASKmskw_ZMM2f16_ZMM2f16_AVX512
}

{
ICLASS:      VFMULCPH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_512
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR NO_SRC_DEST_MATCH 
PATTERN:    EVV 0xD6 VF3 MAP6 MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn]  MODRM()  VL512  W0    ESIZE_32_BITS() NELEM_FULL() 
OPERANDS:    REG0=ZMM_R3():w:z2f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:z2f16 MEM0:r:vv:2f16:TXT=BCASTSTR
IFORM:       VFMULCPH_ZMM2f16_MASKmskw_ZMM2f16_MEM2f16_AVX512
}


# EMITTING VFMULCSH (VFMULCSH-128-1)
{
ICLASS:      VFMULCSH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_SCALAR
EXCEPTIONS:     AVX512-E10
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR NO_SRC_DEST_MATCH SIMD_SCALAR 
PATTERN:    EVV 0xD7 VF3 MAP6 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn]  FIX_ROUND_LEN128() W0   
OPERANDS:    REG0=XMM_R3():w:dq:2f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:2f16 REG3=XMM_B3():r:dq:2f16
IFORM:       VFMULCSH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512
}

{
ICLASS:      VFMULCSH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_SCALAR
EXCEPTIONS:     AVX512-E10
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR NO_SRC_DEST_MATCH SIMD_SCALAR 
PATTERN:    EVV 0xD7 VF3 MAP6 MOD[0b11] MOD=3 BCRC=1 UBIT=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND()  W0   
OPERANDS:    REG0=XMM_R3():w:dq:2f16:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:2f16 REG3=XMM_B3():r:dq:2f16
IFORM:       VFMULCSH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512
}

{
ICLASS:      VFMULCSH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_SCALAR
EXCEPTIONS:     AVX512-E10
REAL_OPCODE: Y
ATTRIBUTES:  DISP8_SCALAR MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR NO_SRC_DEST_MATCH SIMD_SCALAR 
PATTERN:    EVV 0xD7 VF3 MAP6 MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn] BCRC=0 MODRM()  FIX_ROUND_LEN128() W0    ESIZE_32_BITS() NELEM_SCALAR() 
OPERANDS:    REG0=XMM_R3():w:dq:2f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:2f16 MEM0:r:d:2f16
IFORM:       VFMULCSH_XMM2f16_MASKmskw_XMM2f16_MEM2f16_AVX512
}


# EMITTING VFNMADD132PH (VFNMADD132PH-128-1)
{
ICLASS:      VFNMADD132PH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_128
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR 
PATTERN:    EVV 0x9C V66 MAP6 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn]  VL128  W0   
OPERANDS:    REG0=XMM_R3():rw:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 REG3=XMM_B3():r:dq:f16
IFORM:       VFNMADD132PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512
}

{
ICLASS:      VFNMADD132PH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_128
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR 
PATTERN:    EVV 0x9C V66 MAP6 MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn]  MODRM()  VL128  W0    ESIZE_16_BITS() NELEM_FULL() 
OPERANDS:    REG0=XMM_R3():rw:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 MEM0:r:vv:f16:TXT=BCASTSTR
IFORM:       VFNMADD132PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512
}


# EMITTING VFNMADD132PH (VFNMADD132PH-256-1)
{
ICLASS:      VFNMADD132PH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_256
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR 
PATTERN:    EVV 0x9C V66 MAP6 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn]  VL256  W0   
OPERANDS:    REG0=YMM_R3():rw:qq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f16 REG3=YMM_B3():r:qq:f16
IFORM:       VFNMADD132PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512
}

{
ICLASS:      VFNMADD132PH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_256
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR 
PATTERN:    EVV 0x9C V66 MAP6 MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn]  MODRM()  VL256  W0    ESIZE_16_BITS() NELEM_FULL() 
OPERANDS:    REG0=YMM_R3():rw:qq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f16 MEM0:r:vv:f16:TXT=BCASTSTR
IFORM:       VFNMADD132PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512
}


# EMITTING VFNMADD132PH (VFNMADD132PH-512-1)
{
ICLASS:      VFNMADD132PH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR 
PATTERN:    EVV 0x9C V66 MAP6 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn]  VL512  W0   
OPERANDS:    REG0=ZMM_R3():rw:zf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf16 REG3=ZMM_B3():r:zf16
IFORM:       VFNMADD132PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512
}

{
ICLASS:      VFNMADD132PH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR 
PATTERN:    EVV 0x9C V66 MAP6 MOD[0b11] MOD=3 BCRC=1 UBIT=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND()  W0   
OPERANDS:    REG0=ZMM_R3():rw:zf16:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf16 REG3=ZMM_B3():r:zf16
IFORM:       VFNMADD132PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512
}

{
ICLASS:      VFNMADD132PH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR 
PATTERN:    EVV 0x9C V66 MAP6 MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn]  MODRM()  VL512  W0    ESIZE_16_BITS() NELEM_FULL() 
OPERANDS:    REG0=ZMM_R3():rw:zf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf16 MEM0:r:vv:f16:TXT=BCASTSTR
IFORM:       VFNMADD132PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512
}


# EMITTING VFNMADD132SH (VFNMADD132SH-128-1)
{
ICLASS:      VFNMADD132SH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_SCALAR
EXCEPTIONS:     AVX512-E3
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR SIMD_SCALAR 
PATTERN:    EVV 0x9D V66 MAP6 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn]  FIX_ROUND_LEN128() W0   
OPERANDS:    REG0=XMM_R3():rw:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 REG3=XMM_B3():r:dq:f16
IFORM:       VFNMADD132SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512
}

{
ICLASS:      VFNMADD132SH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_SCALAR
EXCEPTIONS:     AVX512-E3
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR SIMD_SCALAR 
PATTERN:    EVV 0x9D V66 MAP6 MOD[0b11] MOD=3 BCRC=1 UBIT=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND()  W0   
OPERANDS:    REG0=XMM_R3():rw:dq:f16:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 REG3=XMM_B3():r:dq:f16
IFORM:       VFNMADD132SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512
}

{
ICLASS:      VFNMADD132SH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_SCALAR
EXCEPTIONS:     AVX512-E3
REAL_OPCODE: Y
ATTRIBUTES:  DISP8_SCALAR MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR SIMD_SCALAR 
PATTERN:    EVV 0x9D V66 MAP6 MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn] BCRC=0 MODRM()  FIX_ROUND_LEN128() W0    ESIZE_16_BITS() NELEM_SCALAR() 
OPERANDS:    REG0=XMM_R3():rw:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 MEM0:r:wrd:f16
IFORM:       VFNMADD132SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512
}


# EMITTING VFNMADD213PH (VFNMADD213PH-128-1)
{
ICLASS:      VFNMADD213PH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_128
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR 
PATTERN:    EVV 0xAC V66 MAP6 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn]  VL128  W0   
OPERANDS:    REG0=XMM_R3():rw:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 REG3=XMM_B3():r:dq:f16
IFORM:       VFNMADD213PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512
}

{
ICLASS:      VFNMADD213PH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_128
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR 
PATTERN:    EVV 0xAC V66 MAP6 MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn]  MODRM()  VL128  W0    ESIZE_16_BITS() NELEM_FULL() 
OPERANDS:    REG0=XMM_R3():rw:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 MEM0:r:vv:f16:TXT=BCASTSTR
IFORM:       VFNMADD213PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512
}


# EMITTING VFNMADD213PH (VFNMADD213PH-256-1)
{
ICLASS:      VFNMADD213PH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_256
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR 
PATTERN:    EVV 0xAC V66 MAP6 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn]  VL256  W0   
OPERANDS:    REG0=YMM_R3():rw:qq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f16 REG3=YMM_B3():r:qq:f16
IFORM:       VFNMADD213PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512
}

{
ICLASS:      VFNMADD213PH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_256
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR 
PATTERN:    EVV 0xAC V66 MAP6 MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn]  MODRM()  VL256  W0    ESIZE_16_BITS() NELEM_FULL() 
OPERANDS:    REG0=YMM_R3():rw:qq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f16 MEM0:r:vv:f16:TXT=BCASTSTR
IFORM:       VFNMADD213PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512
}


# EMITTING VFNMADD213PH (VFNMADD213PH-512-1)
{
ICLASS:      VFNMADD213PH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR 
PATTERN:    EVV 0xAC V66 MAP6 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn]  VL512  W0   
OPERANDS:    REG0=ZMM_R3():rw:zf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf16 REG3=ZMM_B3():r:zf16
IFORM:       VFNMADD213PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512
}

{
ICLASS:      VFNMADD213PH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR 
PATTERN:    EVV 0xAC V66 MAP6 MOD[0b11] MOD=3 BCRC=1 UBIT=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND()  W0   
OPERANDS:    REG0=ZMM_R3():rw:zf16:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf16 REG3=ZMM_B3():r:zf16
IFORM:       VFNMADD213PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512
}

{
ICLASS:      VFNMADD213PH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR 
PATTERN:    EVV 0xAC V66 MAP6 MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn]  MODRM()  VL512  W0    ESIZE_16_BITS() NELEM_FULL() 
OPERANDS:    REG0=ZMM_R3():rw:zf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf16 MEM0:r:vv:f16:TXT=BCASTSTR
IFORM:       VFNMADD213PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512
}


# EMITTING VFNMADD213SH (VFNMADD213SH-128-1)
{
ICLASS:      VFNMADD213SH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_SCALAR
EXCEPTIONS:     AVX512-E3
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR SIMD_SCALAR 
PATTERN:    EVV 0xAD V66 MAP6 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn]  FIX_ROUND_LEN128() W0   
OPERANDS:    REG0=XMM_R3():rw:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 REG3=XMM_B3():r:dq:f16
IFORM:       VFNMADD213SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512
}

{
ICLASS:      VFNMADD213SH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_SCALAR
EXCEPTIONS:     AVX512-E3
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR SIMD_SCALAR 
PATTERN:    EVV 0xAD V66 MAP6 MOD[0b11] MOD=3 BCRC=1 UBIT=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND()  W0   
OPERANDS:    REG0=XMM_R3():rw:dq:f16:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 REG3=XMM_B3():r:dq:f16
IFORM:       VFNMADD213SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512
}

{
ICLASS:      VFNMADD213SH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_SCALAR
EXCEPTIONS:     AVX512-E3
REAL_OPCODE: Y
ATTRIBUTES:  DISP8_SCALAR MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR SIMD_SCALAR 
PATTERN:    EVV 0xAD V66 MAP6 MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn] BCRC=0 MODRM()  FIX_ROUND_LEN128() W0    ESIZE_16_BITS() NELEM_SCALAR() 
OPERANDS:    REG0=XMM_R3():rw:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 MEM0:r:wrd:f16
IFORM:       VFNMADD213SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512
}


# EMITTING VFNMADD231PH (VFNMADD231PH-128-1)
{
ICLASS:      VFNMADD231PH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_128
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR 
PATTERN:    EVV 0xBC V66 MAP6 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn]  VL128  W0   
OPERANDS:    REG0=XMM_R3():rw:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 REG3=XMM_B3():r:dq:f16
IFORM:       VFNMADD231PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512
}

{
ICLASS:      VFNMADD231PH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_128
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR 
PATTERN:    EVV 0xBC V66 MAP6 MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn]  MODRM()  VL128  W0    ESIZE_16_BITS() NELEM_FULL() 
OPERANDS:    REG0=XMM_R3():rw:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 MEM0:r:vv:f16:TXT=BCASTSTR
IFORM:       VFNMADD231PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512
}


# EMITTING VFNMADD231PH (VFNMADD231PH-256-1)
{
ICLASS:      VFNMADD231PH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_256
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR 
PATTERN:    EVV 0xBC V66 MAP6 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn]  VL256  W0   
OPERANDS:    REG0=YMM_R3():rw:qq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f16 REG3=YMM_B3():r:qq:f16
IFORM:       VFNMADD231PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512
}

{
ICLASS:      VFNMADD231PH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_256
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR 
PATTERN:    EVV 0xBC V66 MAP6 MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn]  MODRM()  VL256  W0    ESIZE_16_BITS() NELEM_FULL() 
OPERANDS:    REG0=YMM_R3():rw:qq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f16 MEM0:r:vv:f16:TXT=BCASTSTR
IFORM:       VFNMADD231PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512
}


# EMITTING VFNMADD231PH (VFNMADD231PH-512-1)
{
ICLASS:      VFNMADD231PH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR 
PATTERN:    EVV 0xBC V66 MAP6 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn]  VL512  W0   
OPERANDS:    REG0=ZMM_R3():rw:zf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf16 REG3=ZMM_B3():r:zf16
IFORM:       VFNMADD231PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512
}

{
ICLASS:      VFNMADD231PH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR 
PATTERN:    EVV 0xBC V66 MAP6 MOD[0b11] MOD=3 BCRC=1 UBIT=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND()  W0   
OPERANDS:    REG0=ZMM_R3():rw:zf16:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf16 REG3=ZMM_B3():r:zf16
IFORM:       VFNMADD231PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512
}

{
ICLASS:      VFNMADD231PH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR 
PATTERN:    EVV 0xBC V66 MAP6 MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn]  MODRM()  VL512  W0    ESIZE_16_BITS() NELEM_FULL() 
OPERANDS:    REG0=ZMM_R3():rw:zf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf16 MEM0:r:vv:f16:TXT=BCASTSTR
IFORM:       VFNMADD231PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512
}


# EMITTING VFNMADD231SH (VFNMADD231SH-128-1)
{
ICLASS:      VFNMADD231SH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_SCALAR
EXCEPTIONS:     AVX512-E3
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR SIMD_SCALAR 
PATTERN:    EVV 0xBD V66 MAP6 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn]  FIX_ROUND_LEN128() W0   
OPERANDS:    REG0=XMM_R3():rw:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 REG3=XMM_B3():r:dq:f16
IFORM:       VFNMADD231SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512
}

{
ICLASS:      VFNMADD231SH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_SCALAR
EXCEPTIONS:     AVX512-E3
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR SIMD_SCALAR 
PATTERN:    EVV 0xBD V66 MAP6 MOD[0b11] MOD=3 BCRC=1 UBIT=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND()  W0   
OPERANDS:    REG0=XMM_R3():rw:dq:f16:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 REG3=XMM_B3():r:dq:f16
IFORM:       VFNMADD231SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512
}

{
ICLASS:      VFNMADD231SH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_SCALAR
EXCEPTIONS:     AVX512-E3
REAL_OPCODE: Y
ATTRIBUTES:  DISP8_SCALAR MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR SIMD_SCALAR 
PATTERN:    EVV 0xBD V66 MAP6 MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn] BCRC=0 MODRM()  FIX_ROUND_LEN128() W0    ESIZE_16_BITS() NELEM_SCALAR() 
OPERANDS:    REG0=XMM_R3():rw:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 MEM0:r:wrd:f16
IFORM:       VFNMADD231SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512
}


# EMITTING VFNMSUB132PH (VFNMSUB132PH-128-1)
{
ICLASS:      VFNMSUB132PH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_128
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR 
PATTERN:    EVV 0x9E V66 MAP6 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn]  VL128  W0   
OPERANDS:    REG0=XMM_R3():rw:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 REG3=XMM_B3():r:dq:f16
IFORM:       VFNMSUB132PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512
}

{
ICLASS:      VFNMSUB132PH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_128
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR 
PATTERN:    EVV 0x9E V66 MAP6 MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn]  MODRM()  VL128  W0    ESIZE_16_BITS() NELEM_FULL() 
OPERANDS:    REG0=XMM_R3():rw:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 MEM0:r:vv:f16:TXT=BCASTSTR
IFORM:       VFNMSUB132PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512
}


# EMITTING VFNMSUB132PH (VFNMSUB132PH-256-1)
{
ICLASS:      VFNMSUB132PH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_256
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR 
PATTERN:    EVV 0x9E V66 MAP6 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn]  VL256  W0   
OPERANDS:    REG0=YMM_R3():rw:qq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f16 REG3=YMM_B3():r:qq:f16
IFORM:       VFNMSUB132PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512
}

{
ICLASS:      VFNMSUB132PH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_256
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR 
PATTERN:    EVV 0x9E V66 MAP6 MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn]  MODRM()  VL256  W0    ESIZE_16_BITS() NELEM_FULL() 
OPERANDS:    REG0=YMM_R3():rw:qq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f16 MEM0:r:vv:f16:TXT=BCASTSTR
IFORM:       VFNMSUB132PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512
}


# EMITTING VFNMSUB132PH (VFNMSUB132PH-512-1)
{
ICLASS:      VFNMSUB132PH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR 
PATTERN:    EVV 0x9E V66 MAP6 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn]  VL512  W0   
OPERANDS:    REG0=ZMM_R3():rw:zf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf16 REG3=ZMM_B3():r:zf16
IFORM:       VFNMSUB132PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512
}

{
ICLASS:      VFNMSUB132PH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR 
PATTERN:    EVV 0x9E V66 MAP6 MOD[0b11] MOD=3 BCRC=1 UBIT=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND()  W0   
OPERANDS:    REG0=ZMM_R3():rw:zf16:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf16 REG3=ZMM_B3():r:zf16
IFORM:       VFNMSUB132PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512
}

{
ICLASS:      VFNMSUB132PH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR 
PATTERN:    EVV 0x9E V66 MAP6 MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn]  MODRM()  VL512  W0    ESIZE_16_BITS() NELEM_FULL() 
OPERANDS:    REG0=ZMM_R3():rw:zf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf16 MEM0:r:vv:f16:TXT=BCASTSTR
IFORM:       VFNMSUB132PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512
}


# EMITTING VFNMSUB132SH (VFNMSUB132SH-128-1)
{
ICLASS:      VFNMSUB132SH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_SCALAR
EXCEPTIONS:     AVX512-E3
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR SIMD_SCALAR 
PATTERN:    EVV 0x9F V66 MAP6 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn]  FIX_ROUND_LEN128() W0   
OPERANDS:    REG0=XMM_R3():rw:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 REG3=XMM_B3():r:dq:f16
IFORM:       VFNMSUB132SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512
}

{
ICLASS:      VFNMSUB132SH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_SCALAR
EXCEPTIONS:     AVX512-E3
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR SIMD_SCALAR 
PATTERN:    EVV 0x9F V66 MAP6 MOD[0b11] MOD=3 BCRC=1 UBIT=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND()  W0   
OPERANDS:    REG0=XMM_R3():rw:dq:f16:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 REG3=XMM_B3():r:dq:f16
IFORM:       VFNMSUB132SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512
}

{
ICLASS:      VFNMSUB132SH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_SCALAR
EXCEPTIONS:     AVX512-E3
REAL_OPCODE: Y
ATTRIBUTES:  DISP8_SCALAR MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR SIMD_SCALAR 
PATTERN:    EVV 0x9F V66 MAP6 MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn] BCRC=0 MODRM()  FIX_ROUND_LEN128() W0    ESIZE_16_BITS() NELEM_SCALAR() 
OPERANDS:    REG0=XMM_R3():rw:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 MEM0:r:wrd:f16
IFORM:       VFNMSUB132SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512
}


# EMITTING VFNMSUB213PH (VFNMSUB213PH-128-1)
{
ICLASS:      VFNMSUB213PH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_128
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR 
PATTERN:    EVV 0xAE V66 MAP6 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn]  VL128  W0   
OPERANDS:    REG0=XMM_R3():rw:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 REG3=XMM_B3():r:dq:f16
IFORM:       VFNMSUB213PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512
}

{
ICLASS:      VFNMSUB213PH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_128
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR 
PATTERN:    EVV 0xAE V66 MAP6 MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn]  MODRM()  VL128  W0    ESIZE_16_BITS() NELEM_FULL() 
OPERANDS:    REG0=XMM_R3():rw:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 MEM0:r:vv:f16:TXT=BCASTSTR
IFORM:       VFNMSUB213PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512
}


# EMITTING VFNMSUB213PH (VFNMSUB213PH-256-1)
{
ICLASS:      VFNMSUB213PH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_256
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR 
PATTERN:    EVV 0xAE V66 MAP6 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn]  VL256  W0   
OPERANDS:    REG0=YMM_R3():rw:qq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f16 REG3=YMM_B3():r:qq:f16
IFORM:       VFNMSUB213PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512
}

{
ICLASS:      VFNMSUB213PH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_256
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR 
PATTERN:    EVV 0xAE V66 MAP6 MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn]  MODRM()  VL256  W0    ESIZE_16_BITS() NELEM_FULL() 
OPERANDS:    REG0=YMM_R3():rw:qq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f16 MEM0:r:vv:f16:TXT=BCASTSTR
IFORM:       VFNMSUB213PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512
}


# EMITTING VFNMSUB213PH (VFNMSUB213PH-512-1)
{
ICLASS:      VFNMSUB213PH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR 
PATTERN:    EVV 0xAE V66 MAP6 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn]  VL512  W0   
OPERANDS:    REG0=ZMM_R3():rw:zf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf16 REG3=ZMM_B3():r:zf16
IFORM:       VFNMSUB213PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512
}

{
ICLASS:      VFNMSUB213PH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR 
PATTERN:    EVV 0xAE V66 MAP6 MOD[0b11] MOD=3 BCRC=1 UBIT=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND()  W0   
OPERANDS:    REG0=ZMM_R3():rw:zf16:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf16 REG3=ZMM_B3():r:zf16
IFORM:       VFNMSUB213PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512
}

{
ICLASS:      VFNMSUB213PH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR 
PATTERN:    EVV 0xAE V66 MAP6 MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn]  MODRM()  VL512  W0    ESIZE_16_BITS() NELEM_FULL() 
OPERANDS:    REG0=ZMM_R3():rw:zf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf16 MEM0:r:vv:f16:TXT=BCASTSTR
IFORM:       VFNMSUB213PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512
}


# EMITTING VFNMSUB213SH (VFNMSUB213SH-128-1)
{
ICLASS:      VFNMSUB213SH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_SCALAR
EXCEPTIONS:     AVX512-E3
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR SIMD_SCALAR 
PATTERN:    EVV 0xAF V66 MAP6 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn]  FIX_ROUND_LEN128() W0   
OPERANDS:    REG0=XMM_R3():rw:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 REG3=XMM_B3():r:dq:f16
IFORM:       VFNMSUB213SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512
}

{
ICLASS:      VFNMSUB213SH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_SCALAR
EXCEPTIONS:     AVX512-E3
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR SIMD_SCALAR 
PATTERN:    EVV 0xAF V66 MAP6 MOD[0b11] MOD=3 BCRC=1 UBIT=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND()  W0   
OPERANDS:    REG0=XMM_R3():rw:dq:f16:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 REG3=XMM_B3():r:dq:f16
IFORM:       VFNMSUB213SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512
}

{
ICLASS:      VFNMSUB213SH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_SCALAR
EXCEPTIONS:     AVX512-E3
REAL_OPCODE: Y
ATTRIBUTES:  DISP8_SCALAR MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR SIMD_SCALAR 
PATTERN:    EVV 0xAF V66 MAP6 MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn] BCRC=0 MODRM()  FIX_ROUND_LEN128() W0    ESIZE_16_BITS() NELEM_SCALAR() 
OPERANDS:    REG0=XMM_R3():rw:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 MEM0:r:wrd:f16
IFORM:       VFNMSUB213SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512
}


# EMITTING VFNMSUB231PH (VFNMSUB231PH-128-1)
{
ICLASS:      VFNMSUB231PH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_128
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR 
PATTERN:    EVV 0xBE V66 MAP6 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn]  VL128  W0   
OPERANDS:    REG0=XMM_R3():rw:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 REG3=XMM_B3():r:dq:f16
IFORM:       VFNMSUB231PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512
}

{
ICLASS:      VFNMSUB231PH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_128
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR 
PATTERN:    EVV 0xBE V66 MAP6 MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn]  MODRM()  VL128  W0    ESIZE_16_BITS() NELEM_FULL() 
OPERANDS:    REG0=XMM_R3():rw:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 MEM0:r:vv:f16:TXT=BCASTSTR
IFORM:       VFNMSUB231PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512
}


# EMITTING VFNMSUB231PH (VFNMSUB231PH-256-1)
{
ICLASS:      VFNMSUB231PH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_256
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR 
PATTERN:    EVV 0xBE V66 MAP6 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn]  VL256  W0   
OPERANDS:    REG0=YMM_R3():rw:qq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f16 REG3=YMM_B3():r:qq:f16
IFORM:       VFNMSUB231PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512
}

{
ICLASS:      VFNMSUB231PH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_256
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR 
PATTERN:    EVV 0xBE V66 MAP6 MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn]  MODRM()  VL256  W0    ESIZE_16_BITS() NELEM_FULL() 
OPERANDS:    REG0=YMM_R3():rw:qq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f16 MEM0:r:vv:f16:TXT=BCASTSTR
IFORM:       VFNMSUB231PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512
}


# EMITTING VFNMSUB231PH (VFNMSUB231PH-512-1)
{
ICLASS:      VFNMSUB231PH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR 
PATTERN:    EVV 0xBE V66 MAP6 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn]  VL512  W0   
OPERANDS:    REG0=ZMM_R3():rw:zf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf16 REG3=ZMM_B3():r:zf16
IFORM:       VFNMSUB231PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512
}

{
ICLASS:      VFNMSUB231PH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR 
PATTERN:    EVV 0xBE V66 MAP6 MOD[0b11] MOD=3 BCRC=1 UBIT=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND()  W0   
OPERANDS:    REG0=ZMM_R3():rw:zf16:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf16 REG3=ZMM_B3():r:zf16
IFORM:       VFNMSUB231PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512
}

{
ICLASS:      VFNMSUB231PH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR 
PATTERN:    EVV 0xBE V66 MAP6 MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn]  MODRM()  VL512  W0    ESIZE_16_BITS() NELEM_FULL() 
OPERANDS:    REG0=ZMM_R3():rw:zf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf16 MEM0:r:vv:f16:TXT=BCASTSTR
IFORM:       VFNMSUB231PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512
}


# EMITTING VFNMSUB231SH (VFNMSUB231SH-128-1)
{
ICLASS:      VFNMSUB231SH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_SCALAR
EXCEPTIONS:     AVX512-E3
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR SIMD_SCALAR 
PATTERN:    EVV 0xBF V66 MAP6 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn]  FIX_ROUND_LEN128() W0   
OPERANDS:    REG0=XMM_R3():rw:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 REG3=XMM_B3():r:dq:f16
IFORM:       VFNMSUB231SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512
}

{
ICLASS:      VFNMSUB231SH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_SCALAR
EXCEPTIONS:     AVX512-E3
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR SIMD_SCALAR 
PATTERN:    EVV 0xBF V66 MAP6 MOD[0b11] MOD=3 BCRC=1 UBIT=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND()  W0   
OPERANDS:    REG0=XMM_R3():rw:dq:f16:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 REG3=XMM_B3():r:dq:f16
IFORM:       VFNMSUB231SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512
}

{
ICLASS:      VFNMSUB231SH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_SCALAR
EXCEPTIONS:     AVX512-E3
REAL_OPCODE: Y
ATTRIBUTES:  DISP8_SCALAR MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR SIMD_SCALAR 
PATTERN:    EVV 0xBF V66 MAP6 MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn] BCRC=0 MODRM()  FIX_ROUND_LEN128() W0    ESIZE_16_BITS() NELEM_SCALAR() 
OPERANDS:    REG0=XMM_R3():rw:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 MEM0:r:wrd:f16
IFORM:       VFNMSUB231SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512
}


# EMITTING VFPCLASSPH (VFPCLASSPH-128-1)
{
ICLASS:      VFPCLASSPH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_128
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX 
PATTERN:    EVV 0x66 VNP V0F3A MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn]  VL128  W0  NOEVSR  ZEROING=0 UIMM8() 
OPERANDS:    REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_B3():r:dq:f16 IMM0:r:b
IFORM:       VFPCLASSPH_MASKmskw_MASKmskw_XMMf16_IMM8_AVX512
}

{
ICLASS:      VFPCLASSPH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_128
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION 
PATTERN:    EVV 0x66 VNP V0F3A MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn]  MODRM()  VL128  W0  NOEVSR  ZEROING=0 UIMM8()  ESIZE_16_BITS() NELEM_FULL() 
OPERANDS:    REG0=MASK_R():w:mskw REG1=MASK1():r:mskw MEM0:r:vv:f16:TXT=BCASTSTR IMM0:r:b
IFORM:       VFPCLASSPH_MASKmskw_MASKmskw_MEMf16_IMM8_AVX512_VL128
}


# EMITTING VFPCLASSPH (VFPCLASSPH-256-1)
{
ICLASS:      VFPCLASSPH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_256
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX 
PATTERN:    EVV 0x66 VNP V0F3A MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn]  VL256  W0  NOEVSR  ZEROING=0 UIMM8() 
OPERANDS:    REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_B3():r:qq:f16 IMM0:r:b
IFORM:       VFPCLASSPH_MASKmskw_MASKmskw_YMMf16_IMM8_AVX512
}

{
ICLASS:      VFPCLASSPH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_256
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION 
PATTERN:    EVV 0x66 VNP V0F3A MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn]  MODRM()  VL256  W0  NOEVSR  ZEROING=0 UIMM8()  ESIZE_16_BITS() NELEM_FULL() 
OPERANDS:    REG0=MASK_R():w:mskw REG1=MASK1():r:mskw MEM0:r:vv:f16:TXT=BCASTSTR IMM0:r:b
IFORM:       VFPCLASSPH_MASKmskw_MASKmskw_MEMf16_IMM8_AVX512_VL256
}


# EMITTING VFPCLASSPH (VFPCLASSPH-512-1)
{
ICLASS:      VFPCLASSPH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_512
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX 
PATTERN:    EVV 0x66 VNP V0F3A MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn]  VL512  W0  NOEVSR  ZEROING=0 UIMM8() 
OPERANDS:    REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_B3():r:zf16 IMM0:r:b
IFORM:       VFPCLASSPH_MASKmskw_MASKmskw_ZMMf16_IMM8_AVX512
}

{
ICLASS:      VFPCLASSPH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_512
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION 
PATTERN:    EVV 0x66 VNP V0F3A MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn]  MODRM()  VL512  W0  NOEVSR  ZEROING=0 UIMM8()  ESIZE_16_BITS() NELEM_FULL() 
OPERANDS:    REG0=MASK_R():w:mskw REG1=MASK1():r:mskw MEM0:r:vv:f16:TXT=BCASTSTR IMM0:r:b
IFORM:       VFPCLASSPH_MASKmskw_MASKmskw_MEMf16_IMM8_AVX512_VL512
}


# EMITTING VFPCLASSSH (VFPCLASSSH-128-1)
{
ICLASS:      VFPCLASSSH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_SCALAR
EXCEPTIONS:     AVX512-E10
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX SIMD_SCALAR 
PATTERN:    EVV 0x67 VNP V0F3A MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn]  FIX_ROUND_LEN128() W0  NOEVSR  ZEROING=0 UIMM8() 
OPERANDS:    REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_B3():r:dq:f16 IMM0:r:b
IFORM:       VFPCLASSSH_MASKmskw_MASKmskw_XMMf16_IMM8_AVX512
}

{
ICLASS:      VFPCLASSSH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_SCALAR
EXCEPTIONS:     AVX512-E10
REAL_OPCODE: Y
ATTRIBUTES:  DISP8_SCALAR MASKOP_EVEX MEMORY_FAULT_SUPPRESSION SIMD_SCALAR 
PATTERN:    EVV 0x67 VNP V0F3A MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn] BCRC=0 MODRM()  FIX_ROUND_LEN128() W0  NOEVSR  ZEROING=0 UIMM8()  ESIZE_16_BITS() NELEM_SCALAR() 
OPERANDS:    REG0=MASK_R():w:mskw REG1=MASK1():r:mskw MEM0:r:wrd:f16 IMM0:r:b
IFORM:       VFPCLASSSH_MASKmskw_MASKmskw_MEMf16_IMM8_AVX512
}


# EMITTING VGETEXPPH (VGETEXPPH-128-1)
{
ICLASS:      VGETEXPPH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_128
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR 
PATTERN:    EVV 0x42 V66 MAP6 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn]  VL128  W0  NOEVSR 
OPERANDS:    REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f16
IFORM:       VGETEXPPH_XMMf16_MASKmskw_XMMf16_AVX512
}

{
ICLASS:      VGETEXPPH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_128
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR 
PATTERN:    EVV 0x42 V66 MAP6 MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn]  MODRM()  VL128  W0  NOEVSR  ESIZE_16_BITS() NELEM_FULL() 
OPERANDS:    REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f16:TXT=BCASTSTR
IFORM:       VGETEXPPH_XMMf16_MASKmskw_MEMf16_AVX512
}


# EMITTING VGETEXPPH (VGETEXPPH-256-1)
{
ICLASS:      VGETEXPPH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_256
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR 
PATTERN:    EVV 0x42 V66 MAP6 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn]  VL256  W0  NOEVSR 
OPERANDS:    REG0=YMM_R3():w:qq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f16
IFORM:       VGETEXPPH_YMMf16_MASKmskw_YMMf16_AVX512
}

{
ICLASS:      VGETEXPPH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_256
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR 
PATTERN:    EVV 0x42 V66 MAP6 MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn]  MODRM()  VL256  W0  NOEVSR  ESIZE_16_BITS() NELEM_FULL() 
OPERANDS:    REG0=YMM_R3():w:qq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f16:TXT=BCASTSTR
IFORM:       VGETEXPPH_YMMf16_MASKmskw_MEMf16_AVX512
}


# EMITTING VGETEXPPH (VGETEXPPH-512-1)
{
ICLASS:      VGETEXPPH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR 
PATTERN:    EVV 0x42 V66 MAP6 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn]  VL512  W0  NOEVSR 
OPERANDS:    REG0=ZMM_R3():w:zf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf16
IFORM:       VGETEXPPH_ZMMf16_MASKmskw_ZMMf16_AVX512
}

{
ICLASS:      VGETEXPPH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR 
PATTERN:    EVV 0x42 V66 MAP6 MOD[0b11] MOD=3 BCRC=1 UBIT=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE()  W0  NOEVSR 
OPERANDS:    REG0=ZMM_R3():w:zf16:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf16
IFORM:       VGETEXPPH_ZMMf16_MASKmskw_ZMMf16_AVX512
}

{
ICLASS:      VGETEXPPH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR 
PATTERN:    EVV 0x42 V66 MAP6 MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn]  MODRM()  VL512  W0  NOEVSR  ESIZE_16_BITS() NELEM_FULL() 
OPERANDS:    REG0=ZMM_R3():w:zf16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f16:TXT=BCASTSTR
IFORM:       VGETEXPPH_ZMMf16_MASKmskw_MEMf16_AVX512
}


# EMITTING VGETEXPSH (VGETEXPSH-128-1)
{
ICLASS:      VGETEXPSH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_SCALAR
EXCEPTIONS:     AVX512-E3
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR SIMD_SCALAR 
PATTERN:    EVV 0x43 V66 MAP6 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn]  FIX_ROUND_LEN128() W0   
OPERANDS:    REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 REG3=XMM_B3():r:dq:f16
IFORM:       VGETEXPSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512
}

{
ICLASS:      VGETEXPSH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_SCALAR
EXCEPTIONS:     AVX512-E3
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR SIMD_SCALAR 
PATTERN:    EVV 0x43 V66 MAP6 MOD[0b11] MOD=3 BCRC=1 UBIT=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE()  W0   
OPERANDS:    REG0=XMM_R3():w:dq:f16:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 REG3=XMM_B3():r:dq:f16
IFORM:       VGETEXPSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512
}

{
ICLASS:      VGETEXPSH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_SCALAR
EXCEPTIONS:     AVX512-E3
REAL_OPCODE: Y
ATTRIBUTES:  DISP8_SCALAR MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR SIMD_SCALAR 
PATTERN:    EVV 0x43 V66 MAP6 MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn] BCRC=0 MODRM()  FIX_ROUND_LEN128() W0    ESIZE_16_BITS() NELEM_SCALAR() 
OPERANDS:    REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 MEM0:r:wrd:f16
IFORM:       VGETEXPSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512
}


# EMITTING VGETMANTPH (VGETMANTPH-128-1)
{
ICLASS:      VGETMANTPH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_128
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR 
PATTERN:    EVV 0x26 VNP V0F3A MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn]  VL128  W0  NOEVSR UIMM8() 
OPERANDS:    REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f16 IMM0:r:b
IFORM:       VGETMANTPH_XMMf16_MASKmskw_XMMf16_IMM8_AVX512
}

{
ICLASS:      VGETMANTPH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_128
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR 
PATTERN:    EVV 0x26 VNP V0F3A MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn]  MODRM()  VL128  W0  NOEVSR UIMM8()  ESIZE_16_BITS() NELEM_FULL() 
OPERANDS:    REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f16:TXT=BCASTSTR IMM0:r:b
IFORM:       VGETMANTPH_XMMf16_MASKmskw_MEMf16_IMM8_AVX512
}


# EMITTING VGETMANTPH (VGETMANTPH-256-1)
{
ICLASS:      VGETMANTPH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_256
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR 
PATTERN:    EVV 0x26 VNP V0F3A MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn]  VL256  W0  NOEVSR UIMM8() 
OPERANDS:    REG0=YMM_R3():w:qq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f16 IMM0:r:b
IFORM:       VGETMANTPH_YMMf16_MASKmskw_YMMf16_IMM8_AVX512
}

{
ICLASS:      VGETMANTPH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_256
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR 
PATTERN:    EVV 0x26 VNP V0F3A MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn]  MODRM()  VL256  W0  NOEVSR UIMM8()  ESIZE_16_BITS() NELEM_FULL() 
OPERANDS:    REG0=YMM_R3():w:qq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f16:TXT=BCASTSTR IMM0:r:b
IFORM:       VGETMANTPH_YMMf16_MASKmskw_MEMf16_IMM8_AVX512
}


# EMITTING VGETMANTPH (VGETMANTPH-512-1)
{
ICLASS:      VGETMANTPH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR 
PATTERN:    EVV 0x26 VNP V0F3A MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn]  VL512  W0  NOEVSR UIMM8() 
OPERANDS:    REG0=ZMM_R3():w:zf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf16 IMM0:r:b
IFORM:       VGETMANTPH_ZMMf16_MASKmskw_ZMMf16_IMM8_AVX512
}

{
ICLASS:      VGETMANTPH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR 
PATTERN:    EVV 0x26 VNP V0F3A MOD[0b11] MOD=3 BCRC=1 UBIT=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE()  W0  NOEVSR UIMM8() 
OPERANDS:    REG0=ZMM_R3():w:zf16:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf16 IMM0:r:b
IFORM:       VGETMANTPH_ZMMf16_MASKmskw_ZMMf16_IMM8_AVX512
}

{
ICLASS:      VGETMANTPH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR 
PATTERN:    EVV 0x26 VNP V0F3A MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn]  MODRM()  VL512  W0  NOEVSR UIMM8()  ESIZE_16_BITS() NELEM_FULL() 
OPERANDS:    REG0=ZMM_R3():w:zf16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f16:TXT=BCASTSTR IMM0:r:b
IFORM:       VGETMANTPH_ZMMf16_MASKmskw_MEMf16_IMM8_AVX512
}


# EMITTING VGETMANTSH (VGETMANTSH-128-1)
{
ICLASS:      VGETMANTSH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_SCALAR
EXCEPTIONS:     AVX512-E3
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR SIMD_SCALAR 
PATTERN:    EVV 0x27 VNP V0F3A MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn]  FIX_ROUND_LEN128() W0   UIMM8() 
OPERANDS:    REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 REG3=XMM_B3():r:dq:f16 IMM0:r:b
IFORM:       VGETMANTSH_XMMf16_MASKmskw_XMMf16_XMMf16_IMM8_AVX512
}

{
ICLASS:      VGETMANTSH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_SCALAR
EXCEPTIONS:     AVX512-E3
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR SIMD_SCALAR 
PATTERN:    EVV 0x27 VNP V0F3A MOD[0b11] MOD=3 BCRC=1 UBIT=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE()  W0   UIMM8() 
OPERANDS:    REG0=XMM_R3():w:dq:f16:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 REG3=XMM_B3():r:dq:f16 IMM0:r:b
IFORM:       VGETMANTSH_XMMf16_MASKmskw_XMMf16_XMMf16_IMM8_AVX512
}

{
ICLASS:      VGETMANTSH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_SCALAR
EXCEPTIONS:     AVX512-E3
REAL_OPCODE: Y
ATTRIBUTES:  DISP8_SCALAR MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR SIMD_SCALAR 
PATTERN:    EVV 0x27 VNP V0F3A MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn] BCRC=0 MODRM()  FIX_ROUND_LEN128() W0   UIMM8()  ESIZE_16_BITS() NELEM_SCALAR() 
OPERANDS:    REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 MEM0:r:wrd:f16 IMM0:r:b
IFORM:       VGETMANTSH_XMMf16_MASKmskw_XMMf16_MEMf16_IMM8_AVX512
}


# EMITTING VMAXPH (VMAXPH-128-1)
{
ICLASS:      VMAXPH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_128
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR 
PATTERN:    EVV 0x5F VNP MAP5 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn]  VL128  W0   
OPERANDS:    REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 REG3=XMM_B3():r:dq:f16
IFORM:       VMAXPH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512
}

{
ICLASS:      VMAXPH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_128
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR 
PATTERN:    EVV 0x5F VNP MAP5 MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn]  MODRM()  VL128  W0    ESIZE_16_BITS() NELEM_FULL() 
OPERANDS:    REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 MEM0:r:vv:f16:TXT=BCASTSTR
IFORM:       VMAXPH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512
}


# EMITTING VMAXPH (VMAXPH-256-1)
{
ICLASS:      VMAXPH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_256
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR 
PATTERN:    EVV 0x5F VNP MAP5 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn]  VL256  W0   
OPERANDS:    REG0=YMM_R3():w:qq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f16 REG3=YMM_B3():r:qq:f16
IFORM:       VMAXPH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512
}

{
ICLASS:      VMAXPH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_256
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR 
PATTERN:    EVV 0x5F VNP MAP5 MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn]  MODRM()  VL256  W0    ESIZE_16_BITS() NELEM_FULL() 
OPERANDS:    REG0=YMM_R3():w:qq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f16 MEM0:r:vv:f16:TXT=BCASTSTR
IFORM:       VMAXPH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512
}


# EMITTING VMAXPH (VMAXPH-512-1)
{
ICLASS:      VMAXPH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR 
PATTERN:    EVV 0x5F VNP MAP5 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn]  VL512  W0   
OPERANDS:    REG0=ZMM_R3():w:zf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf16 REG3=ZMM_B3():r:zf16
IFORM:       VMAXPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512
}

{
ICLASS:      VMAXPH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR 
PATTERN:    EVV 0x5F VNP MAP5 MOD[0b11] MOD=3 BCRC=1 UBIT=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE()  W0   
OPERANDS:    REG0=ZMM_R3():w:zf16:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf16 REG3=ZMM_B3():r:zf16
IFORM:       VMAXPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512
}

{
ICLASS:      VMAXPH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR 
PATTERN:    EVV 0x5F VNP MAP5 MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn]  MODRM()  VL512  W0    ESIZE_16_BITS() NELEM_FULL() 
OPERANDS:    REG0=ZMM_R3():w:zf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf16 MEM0:r:vv:f16:TXT=BCASTSTR
IFORM:       VMAXPH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512
}


# EMITTING VMAXSH (VMAXSH-128-1)
{
ICLASS:      VMAXSH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_SCALAR
EXCEPTIONS:     AVX512-E3
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR SIMD_SCALAR 
PATTERN:    EVV 0x5F VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn]  FIX_ROUND_LEN128() W0   
OPERANDS:    REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 REG3=XMM_B3():r:dq:f16
IFORM:       VMAXSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512
}

{
ICLASS:      VMAXSH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_SCALAR
EXCEPTIONS:     AVX512-E3
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR SIMD_SCALAR 
PATTERN:    EVV 0x5F VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 UBIT=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE()  W0   
OPERANDS:    REG0=XMM_R3():w:dq:f16:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 REG3=XMM_B3():r:dq:f16
IFORM:       VMAXSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512
}

{
ICLASS:      VMAXSH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_SCALAR
EXCEPTIONS:     AVX512-E3
REAL_OPCODE: Y
ATTRIBUTES:  DISP8_SCALAR MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR SIMD_SCALAR 
PATTERN:    EVV 0x5F VF3 MAP5 MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn] BCRC=0 MODRM()  FIX_ROUND_LEN128() W0    ESIZE_16_BITS() NELEM_SCALAR() 
OPERANDS:    REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 MEM0:r:wrd:f16
IFORM:       VMAXSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512
}


# EMITTING VMINPH (VMINPH-128-1)
{
ICLASS:      VMINPH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_128
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR 
PATTERN:    EVV 0x5D VNP MAP5 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn]  VL128  W0   
OPERANDS:    REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 REG3=XMM_B3():r:dq:f16
IFORM:       VMINPH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512
}

{
ICLASS:      VMINPH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_128
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR 
PATTERN:    EVV 0x5D VNP MAP5 MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn]  MODRM()  VL128  W0    ESIZE_16_BITS() NELEM_FULL() 
OPERANDS:    REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 MEM0:r:vv:f16:TXT=BCASTSTR
IFORM:       VMINPH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512
}


# EMITTING VMINPH (VMINPH-256-1)
{
ICLASS:      VMINPH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_256
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR 
PATTERN:    EVV 0x5D VNP MAP5 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn]  VL256  W0   
OPERANDS:    REG0=YMM_R3():w:qq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f16 REG3=YMM_B3():r:qq:f16
IFORM:       VMINPH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512
}

{
ICLASS:      VMINPH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_256
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR 
PATTERN:    EVV 0x5D VNP MAP5 MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn]  MODRM()  VL256  W0    ESIZE_16_BITS() NELEM_FULL() 
OPERANDS:    REG0=YMM_R3():w:qq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f16 MEM0:r:vv:f16:TXT=BCASTSTR
IFORM:       VMINPH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512
}


# EMITTING VMINPH (VMINPH-512-1)
{
ICLASS:      VMINPH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR 
PATTERN:    EVV 0x5D VNP MAP5 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn]  VL512  W0   
OPERANDS:    REG0=ZMM_R3():w:zf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf16 REG3=ZMM_B3():r:zf16
IFORM:       VMINPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512
}

{
ICLASS:      VMINPH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR 
PATTERN:    EVV 0x5D VNP MAP5 MOD[0b11] MOD=3 BCRC=1 UBIT=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE()  W0   
OPERANDS:    REG0=ZMM_R3():w:zf16:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf16 REG3=ZMM_B3():r:zf16
IFORM:       VMINPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512
}

{
ICLASS:      VMINPH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR 
PATTERN:    EVV 0x5D VNP MAP5 MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn]  MODRM()  VL512  W0    ESIZE_16_BITS() NELEM_FULL() 
OPERANDS:    REG0=ZMM_R3():w:zf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf16 MEM0:r:vv:f16:TXT=BCASTSTR
IFORM:       VMINPH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512
}


# EMITTING VMINSH (VMINSH-128-1)
{
ICLASS:      VMINSH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_SCALAR
EXCEPTIONS:     AVX512-E3
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR SIMD_SCALAR 
PATTERN:    EVV 0x5D VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn]  FIX_ROUND_LEN128() W0   
OPERANDS:    REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 REG3=XMM_B3():r:dq:f16
IFORM:       VMINSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512
}

{
ICLASS:      VMINSH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_SCALAR
EXCEPTIONS:     AVX512-E3
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR SIMD_SCALAR 
PATTERN:    EVV 0x5D VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 UBIT=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE()  W0   
OPERANDS:    REG0=XMM_R3():w:dq:f16:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 REG3=XMM_B3():r:dq:f16
IFORM:       VMINSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512
}

{
ICLASS:      VMINSH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_SCALAR
EXCEPTIONS:     AVX512-E3
REAL_OPCODE: Y
ATTRIBUTES:  DISP8_SCALAR MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR SIMD_SCALAR 
PATTERN:    EVV 0x5D VF3 MAP5 MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn] BCRC=0 MODRM()  FIX_ROUND_LEN128() W0    ESIZE_16_BITS() NELEM_SCALAR() 
OPERANDS:    REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 MEM0:r:wrd:f16
IFORM:       VMINSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512
}


# EMITTING VMOVSH (VMOVSH-128-1)
{
ICLASS:      VMOVSH
CPL:         3
CATEGORY:    DATAXFER
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_SCALAR
EXCEPTIONS:     AVX512-E5
REAL_OPCODE: Y
ATTRIBUTES:  DISP8_SCALAR MASKOP_EVEX MEMORY_FAULT_SUPPRESSION SIMD_SCALAR 
PATTERN:    EVV 0x10 VF3 MAP5 MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn] BCRC=0 MODRM()  FIX_ROUND_LEN128() W0  NOEVSR  ESIZE_16_BITS() NELEM_SCALAR() 
OPERANDS:    REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:wrd:f16
IFORM:       VMOVSH_XMMf16_MASKmskw_MEMf16_AVX512
}


# EMITTING VMOVSH (VMOVSH-128-5)
{
ICLASS:      VMOVSH
CPL:         3
CATEGORY:    DATAXFER
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_SCALAR
EXCEPTIONS:     AVX512-E5
REAL_OPCODE: Y
ATTRIBUTES:  DISP8_SCALAR MASKOP_EVEX MEMORY_FAULT_SUPPRESSION SIMD_SCALAR 
PATTERN:    EVV 0x11 VF3 MAP5 MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn] BCRC=0 MODRM()  FIX_ROUND_LEN128() W0  NOEVSR  ZEROING=0  ESIZE_16_BITS() NELEM_SCALAR() 
OPERANDS:    MEM0:w:wrd:f16 REG0=MASK1():r:mskw REG1=XMM_R3():r:dq:f16
IFORM:       VMOVSH_MEMf16_MASKmskw_XMMf16_AVX512
}


# EMITTING VMOVSH (VMOVSH-128-6)
{
ICLASS:      VMOVSH
CPL:         3
CATEGORY:    DATAXFER
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_SCALAR
EXCEPTIONS:     AVX512-E5
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX SIMD_SCALAR 
PATTERN:    EVV 0x10 VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn]  FIX_ROUND_LEN128() W0   
OPERANDS:    REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 REG3=XMM_B3():r:dq:f16
IFORM:       VMOVSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512
}


# EMITTING VMOVSH (VMOVSH-128-7)
{
ICLASS:      VMOVSH
CPL:         3
CATEGORY:    DATAXFER
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_SCALAR
EXCEPTIONS:     AVX512-E5
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX SIMD_SCALAR 
PATTERN:    EVV 0x11 VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn]  FIX_ROUND_LEN128() W0   
OPERANDS:    REG0=XMM_B3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 REG3=XMM_R3():r:dq:f16
IFORM:       VMOVSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512
}


# EMITTING VMOVW (VMOVW-128-1)
{
ICLASS:      VMOVW
CPL:         3
CATEGORY:    DATAXFER
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_128N
EXCEPTIONS:     AVX512-E9NF
REAL_OPCODE: Y
PATTERN:    EVV 0x6E V66 MAP5 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn]  VL128    NOEVSR  ZEROING=0 MASK=0 
OPERANDS:    REG0=XMM_R3():w:dq:f16 REG1=GPR32_B():r:d:f16
IFORM:       VMOVW_XMMf16_GPR32f16_AVX512
}

{
ICLASS:      VMOVW
CPL:         3
CATEGORY:    DATAXFER
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_128N
EXCEPTIONS:     AVX512-E9NF
REAL_OPCODE: Y
ATTRIBUTES:  DISP8_GPR_READER 
PATTERN:    EVV 0x6E V66 MAP5 MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn] BCRC=0 MODRM()  VL128    NOEVSR  ZEROING=0 MASK=0  ESIZE_16_BITS() NELEM_GPR_READER() 
OPERANDS:    REG0=XMM_R3():w:dq:f16 MEM0:r:wrd:f16
IFORM:       VMOVW_XMMf16_MEMf16_AVX512
}


# EMITTING VMOVW (VMOVW-128-2)
{
ICLASS:      VMOVW
CPL:         3
CATEGORY:    DATAXFER
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_128N
EXCEPTIONS:     AVX512-E9NF
REAL_OPCODE: Y
PATTERN:    EVV 0x7E V66 MAP5 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn]  VL128    NOEVSR  ZEROING=0 MASK=0 
OPERANDS:    REG0=GPR32_B():w:d:f16 REG1=XMM_R3():r:dq:f16
IFORM:       VMOVW_GPR32f16_XMMf16_AVX512
}

{
ICLASS:      VMOVW
CPL:         3
CATEGORY:    DATAXFER
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_128N
EXCEPTIONS:     AVX512-E9NF
REAL_OPCODE: Y
ATTRIBUTES:  DISP8_GPR_WRITER_STORE 
PATTERN:    EVV 0x7E V66 MAP5 MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn] BCRC=0 MODRM()  VL128    NOEVSR  ZEROING=0 MASK=0  ESIZE_16_BITS() NELEM_GPR_WRITER_STORE() 
OPERANDS:    MEM0:w:wrd:f16 REG0=XMM_R3():r:dq:f16
IFORM:       VMOVW_MEMf16_XMMf16_AVX512
}


# EMITTING VMULPH (VMULPH-128-1)
{
ICLASS:      VMULPH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_128
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR 
PATTERN:    EVV 0x59 VNP MAP5 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn]  VL128  W0   
OPERANDS:    REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 REG3=XMM_B3():r:dq:f16
IFORM:       VMULPH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512
}

{
ICLASS:      VMULPH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_128
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR 
PATTERN:    EVV 0x59 VNP MAP5 MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn]  MODRM()  VL128  W0    ESIZE_16_BITS() NELEM_FULL() 
OPERANDS:    REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 MEM0:r:vv:f16:TXT=BCASTSTR
IFORM:       VMULPH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512
}


# EMITTING VMULPH (VMULPH-256-1)
{
ICLASS:      VMULPH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_256
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR 
PATTERN:    EVV 0x59 VNP MAP5 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn]  VL256  W0   
OPERANDS:    REG0=YMM_R3():w:qq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f16 REG3=YMM_B3():r:qq:f16
IFORM:       VMULPH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512
}

{
ICLASS:      VMULPH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_256
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR 
PATTERN:    EVV 0x59 VNP MAP5 MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn]  MODRM()  VL256  W0    ESIZE_16_BITS() NELEM_FULL() 
OPERANDS:    REG0=YMM_R3():w:qq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f16 MEM0:r:vv:f16:TXT=BCASTSTR
IFORM:       VMULPH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512
}


# EMITTING VMULPH (VMULPH-512-1)
{
ICLASS:      VMULPH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR 
PATTERN:    EVV 0x59 VNP MAP5 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn]  VL512  W0   
OPERANDS:    REG0=ZMM_R3():w:zf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf16 REG3=ZMM_B3():r:zf16
IFORM:       VMULPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512
}

{
ICLASS:      VMULPH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR 
PATTERN:    EVV 0x59 VNP MAP5 MOD[0b11] MOD=3 BCRC=1 UBIT=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND()  W0   
OPERANDS:    REG0=ZMM_R3():w:zf16:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf16 REG3=ZMM_B3():r:zf16
IFORM:       VMULPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512
}

{
ICLASS:      VMULPH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR 
PATTERN:    EVV 0x59 VNP MAP5 MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn]  MODRM()  VL512  W0    ESIZE_16_BITS() NELEM_FULL() 
OPERANDS:    REG0=ZMM_R3():w:zf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf16 MEM0:r:vv:f16:TXT=BCASTSTR
IFORM:       VMULPH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512
}


# EMITTING VMULSH (VMULSH-128-1)
{
ICLASS:      VMULSH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_SCALAR
EXCEPTIONS:     AVX512-E3
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR SIMD_SCALAR 
PATTERN:    EVV 0x59 VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn]  FIX_ROUND_LEN128() W0   
OPERANDS:    REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 REG3=XMM_B3():r:dq:f16
IFORM:       VMULSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512
}

{
ICLASS:      VMULSH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_SCALAR
EXCEPTIONS:     AVX512-E3
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR SIMD_SCALAR 
PATTERN:    EVV 0x59 VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 UBIT=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND()  W0   
OPERANDS:    REG0=XMM_R3():w:dq:f16:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 REG3=XMM_B3():r:dq:f16
IFORM:       VMULSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512
}

{
ICLASS:      VMULSH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_SCALAR
EXCEPTIONS:     AVX512-E3
REAL_OPCODE: Y
ATTRIBUTES:  DISP8_SCALAR MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR SIMD_SCALAR 
PATTERN:    EVV 0x59 VF3 MAP5 MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn] BCRC=0 MODRM()  FIX_ROUND_LEN128() W0    ESIZE_16_BITS() NELEM_SCALAR() 
OPERANDS:    REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 MEM0:r:wrd:f16
IFORM:       VMULSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512
}


# EMITTING VRCPPH (VRCPPH-128-1)
{
ICLASS:      VRCPPH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_128
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX 
PATTERN:    EVV 0x4C V66 MAP6 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn]  VL128  W0  NOEVSR 
OPERANDS:    REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f16
IFORM:       VRCPPH_XMMf16_MASKmskw_XMMf16_AVX512
}

{
ICLASS:      VRCPPH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_128
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION 
PATTERN:    EVV 0x4C V66 MAP6 MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn]  MODRM()  VL128  W0  NOEVSR  ESIZE_16_BITS() NELEM_FULL() 
OPERANDS:    REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f16:TXT=BCASTSTR
IFORM:       VRCPPH_XMMf16_MASKmskw_MEMf16_AVX512
}


# EMITTING VRCPPH (VRCPPH-256-1)
{
ICLASS:      VRCPPH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_256
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX 
PATTERN:    EVV 0x4C V66 MAP6 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn]  VL256  W0  NOEVSR 
OPERANDS:    REG0=YMM_R3():w:qq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f16
IFORM:       VRCPPH_YMMf16_MASKmskw_YMMf16_AVX512
}

{
ICLASS:      VRCPPH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_256
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION 
PATTERN:    EVV 0x4C V66 MAP6 MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn]  MODRM()  VL256  W0  NOEVSR  ESIZE_16_BITS() NELEM_FULL() 
OPERANDS:    REG0=YMM_R3():w:qq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f16:TXT=BCASTSTR
IFORM:       VRCPPH_YMMf16_MASKmskw_MEMf16_AVX512
}


# EMITTING VRCPPH (VRCPPH-512-1)
{
ICLASS:      VRCPPH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_512
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX 
PATTERN:    EVV 0x4C V66 MAP6 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn]  VL512  W0  NOEVSR 
OPERANDS:    REG0=ZMM_R3():w:zf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf16
IFORM:       VRCPPH_ZMMf16_MASKmskw_ZMMf16_AVX512
}

{
ICLASS:      VRCPPH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_512
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION 
PATTERN:    EVV 0x4C V66 MAP6 MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn]  MODRM()  VL512  W0  NOEVSR  ESIZE_16_BITS() NELEM_FULL() 
OPERANDS:    REG0=ZMM_R3():w:zf16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f16:TXT=BCASTSTR
IFORM:       VRCPPH_ZMMf16_MASKmskw_MEMf16_AVX512
}


# EMITTING VRCPSH (VRCPSH-128-1)
{
ICLASS:      VRCPSH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_SCALAR
EXCEPTIONS:     AVX512-E10
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX SIMD_SCALAR 
PATTERN:    EVV 0x4D V66 MAP6 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn]  FIX_ROUND_LEN128() W0   
OPERANDS:    REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 REG3=XMM_B3():r:dq:f16
IFORM:       VRCPSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512
}

{
ICLASS:      VRCPSH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_SCALAR
EXCEPTIONS:     AVX512-E10
REAL_OPCODE: Y
ATTRIBUTES:  DISP8_SCALAR MASKOP_EVEX MEMORY_FAULT_SUPPRESSION SIMD_SCALAR 
PATTERN:    EVV 0x4D V66 MAP6 MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn] BCRC=0 MODRM()  FIX_ROUND_LEN128() W0    ESIZE_16_BITS() NELEM_SCALAR() 
OPERANDS:    REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 MEM0:r:wrd:f16
IFORM:       VRCPSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512
}


# EMITTING VREDUCEPH (VREDUCEPH-128-1)
{
ICLASS:      VREDUCEPH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_128
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR 
PATTERN:    EVV 0x56 VNP V0F3A MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn]  VL128  W0  NOEVSR UIMM8() 
OPERANDS:    REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f16 IMM0:r:b
IFORM:       VREDUCEPH_XMMf16_MASKmskw_XMMf16_IMM8_AVX512
}

{
ICLASS:      VREDUCEPH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_128
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR 
PATTERN:    EVV 0x56 VNP V0F3A MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn]  MODRM()  VL128  W0  NOEVSR UIMM8()  ESIZE_16_BITS() NELEM_FULL() 
OPERANDS:    REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f16:TXT=BCASTSTR IMM0:r:b
IFORM:       VREDUCEPH_XMMf16_MASKmskw_MEMf16_IMM8_AVX512
}


# EMITTING VREDUCEPH (VREDUCEPH-256-1)
{
ICLASS:      VREDUCEPH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_256
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR 
PATTERN:    EVV 0x56 VNP V0F3A MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn]  VL256  W0  NOEVSR UIMM8() 
OPERANDS:    REG0=YMM_R3():w:qq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f16 IMM0:r:b
IFORM:       VREDUCEPH_YMMf16_MASKmskw_YMMf16_IMM8_AVX512
}

{
ICLASS:      VREDUCEPH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_256
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR 
PATTERN:    EVV 0x56 VNP V0F3A MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn]  MODRM()  VL256  W0  NOEVSR UIMM8()  ESIZE_16_BITS() NELEM_FULL() 
OPERANDS:    REG0=YMM_R3():w:qq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f16:TXT=BCASTSTR IMM0:r:b
IFORM:       VREDUCEPH_YMMf16_MASKmskw_MEMf16_IMM8_AVX512
}


# EMITTING VREDUCEPH (VREDUCEPH-512-1)
{
ICLASS:      VREDUCEPH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR 
PATTERN:    EVV 0x56 VNP V0F3A MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn]  VL512  W0  NOEVSR UIMM8() 
OPERANDS:    REG0=ZMM_R3():w:zf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf16 IMM0:r:b
IFORM:       VREDUCEPH_ZMMf16_MASKmskw_ZMMf16_IMM8_AVX512
}

{
ICLASS:      VREDUCEPH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR 
PATTERN:    EVV 0x56 VNP V0F3A MOD[0b11] MOD=3 BCRC=1 UBIT=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE()  W0  NOEVSR UIMM8() 
OPERANDS:    REG0=ZMM_R3():w:zf16:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf16 IMM0:r:b
IFORM:       VREDUCEPH_ZMMf16_MASKmskw_ZMMf16_IMM8_AVX512
}

{
ICLASS:      VREDUCEPH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR 
PATTERN:    EVV 0x56 VNP V0F3A MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn]  MODRM()  VL512  W0  NOEVSR UIMM8()  ESIZE_16_BITS() NELEM_FULL() 
OPERANDS:    REG0=ZMM_R3():w:zf16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f16:TXT=BCASTSTR IMM0:r:b
IFORM:       VREDUCEPH_ZMMf16_MASKmskw_MEMf16_IMM8_AVX512
}


# EMITTING VREDUCESH (VREDUCESH-128-1)
{
ICLASS:      VREDUCESH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_SCALAR
EXCEPTIONS:     AVX512-E3
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR SIMD_SCALAR 
PATTERN:    EVV 0x57 VNP V0F3A MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn]  FIX_ROUND_LEN128() W0   UIMM8() 
OPERANDS:    REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 REG3=XMM_B3():r:dq:f16 IMM0:r:b
IFORM:       VREDUCESH_XMMf16_MASKmskw_XMMf16_XMMf16_IMM8_AVX512
}

{
ICLASS:      VREDUCESH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_SCALAR
EXCEPTIONS:     AVX512-E3
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR SIMD_SCALAR 
PATTERN:    EVV 0x57 VNP V0F3A MOD[0b11] MOD=3 BCRC=1 UBIT=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE()  W0   UIMM8() 
OPERANDS:    REG0=XMM_R3():w:dq:f16:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 REG3=XMM_B3():r:dq:f16 IMM0:r:b
IFORM:       VREDUCESH_XMMf16_MASKmskw_XMMf16_XMMf16_IMM8_AVX512
}

{
ICLASS:      VREDUCESH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_SCALAR
EXCEPTIONS:     AVX512-E3
REAL_OPCODE: Y
ATTRIBUTES:  DISP8_SCALAR MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR SIMD_SCALAR 
PATTERN:    EVV 0x57 VNP V0F3A MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn] BCRC=0 MODRM()  FIX_ROUND_LEN128() W0   UIMM8()  ESIZE_16_BITS() NELEM_SCALAR() 
OPERANDS:    REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 MEM0:r:wrd:f16 IMM0:r:b
IFORM:       VREDUCESH_XMMf16_MASKmskw_XMMf16_MEMf16_IMM8_AVX512
}


# EMITTING VRNDSCALEPH (VRNDSCALEPH-128-1)
{
ICLASS:      VRNDSCALEPH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_128
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR 
PATTERN:    EVV 0x08 VNP V0F3A MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn]  VL128  W0  NOEVSR UIMM8() 
OPERANDS:    REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f16 IMM0:r:b
IFORM:       VRNDSCALEPH_XMMf16_MASKmskw_XMMf16_IMM8_AVX512
}

{
ICLASS:      VRNDSCALEPH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_128
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR 
PATTERN:    EVV 0x08 VNP V0F3A MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn]  MODRM()  VL128  W0  NOEVSR UIMM8()  ESIZE_16_BITS() NELEM_FULL() 
OPERANDS:    REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f16:TXT=BCASTSTR IMM0:r:b
IFORM:       VRNDSCALEPH_XMMf16_MASKmskw_MEMf16_IMM8_AVX512
}


# EMITTING VRNDSCALEPH (VRNDSCALEPH-256-1)
{
ICLASS:      VRNDSCALEPH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_256
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR 
PATTERN:    EVV 0x08 VNP V0F3A MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn]  VL256  W0  NOEVSR UIMM8() 
OPERANDS:    REG0=YMM_R3():w:qq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f16 IMM0:r:b
IFORM:       VRNDSCALEPH_YMMf16_MASKmskw_YMMf16_IMM8_AVX512
}

{
ICLASS:      VRNDSCALEPH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_256
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR 
PATTERN:    EVV 0x08 VNP V0F3A MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn]  MODRM()  VL256  W0  NOEVSR UIMM8()  ESIZE_16_BITS() NELEM_FULL() 
OPERANDS:    REG0=YMM_R3():w:qq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f16:TXT=BCASTSTR IMM0:r:b
IFORM:       VRNDSCALEPH_YMMf16_MASKmskw_MEMf16_IMM8_AVX512
}


# EMITTING VRNDSCALEPH (VRNDSCALEPH-512-1)
{
ICLASS:      VRNDSCALEPH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR 
PATTERN:    EVV 0x08 VNP V0F3A MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn]  VL512  W0  NOEVSR UIMM8() 
OPERANDS:    REG0=ZMM_R3():w:zf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf16 IMM0:r:b
IFORM:       VRNDSCALEPH_ZMMf16_MASKmskw_ZMMf16_IMM8_AVX512
}

{
ICLASS:      VRNDSCALEPH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR 
PATTERN:    EVV 0x08 VNP V0F3A MOD[0b11] MOD=3 BCRC=1 UBIT=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE()  W0  NOEVSR UIMM8() 
OPERANDS:    REG0=ZMM_R3():w:zf16:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf16 IMM0:r:b
IFORM:       VRNDSCALEPH_ZMMf16_MASKmskw_ZMMf16_IMM8_AVX512
}

{
ICLASS:      VRNDSCALEPH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR 
PATTERN:    EVV 0x08 VNP V0F3A MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn]  MODRM()  VL512  W0  NOEVSR UIMM8()  ESIZE_16_BITS() NELEM_FULL() 
OPERANDS:    REG0=ZMM_R3():w:zf16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f16:TXT=BCASTSTR IMM0:r:b
IFORM:       VRNDSCALEPH_ZMMf16_MASKmskw_MEMf16_IMM8_AVX512
}


# EMITTING VRNDSCALESH (VRNDSCALESH-128-1)
{
ICLASS:      VRNDSCALESH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_SCALAR
EXCEPTIONS:     AVX512-E3
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR SIMD_SCALAR 
PATTERN:    EVV 0x0A VNP V0F3A MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn]  FIX_ROUND_LEN128() W0   UIMM8() 
OPERANDS:    REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 REG3=XMM_B3():r:dq:f16 IMM0:r:b
IFORM:       VRNDSCALESH_XMMf16_MASKmskw_XMMf16_XMMf16_IMM8_AVX512
}

{
ICLASS:      VRNDSCALESH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_SCALAR
EXCEPTIONS:     AVX512-E3
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR SIMD_SCALAR 
PATTERN:    EVV 0x0A VNP V0F3A MOD[0b11] MOD=3 BCRC=1 UBIT=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE()  W0   UIMM8() 
OPERANDS:    REG0=XMM_R3():w:dq:f16:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 REG3=XMM_B3():r:dq:f16 IMM0:r:b
IFORM:       VRNDSCALESH_XMMf16_MASKmskw_XMMf16_XMMf16_IMM8_AVX512
}

{
ICLASS:      VRNDSCALESH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_SCALAR
EXCEPTIONS:     AVX512-E3
REAL_OPCODE: Y
ATTRIBUTES:  DISP8_SCALAR MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR SIMD_SCALAR 
PATTERN:    EVV 0x0A VNP V0F3A MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn] BCRC=0 MODRM()  FIX_ROUND_LEN128() W0   UIMM8()  ESIZE_16_BITS() NELEM_SCALAR() 
OPERANDS:    REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 MEM0:r:wrd:f16 IMM0:r:b
IFORM:       VRNDSCALESH_XMMf16_MASKmskw_XMMf16_MEMf16_IMM8_AVX512
}


# EMITTING VRSQRTPH (VRSQRTPH-128-1)
{
ICLASS:      VRSQRTPH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_128
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX 
PATTERN:    EVV 0x4E V66 MAP6 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn]  VL128  W0  NOEVSR 
OPERANDS:    REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f16
IFORM:       VRSQRTPH_XMMf16_MASKmskw_XMMf16_AVX512
}

{
ICLASS:      VRSQRTPH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_128
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION 
PATTERN:    EVV 0x4E V66 MAP6 MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn]  MODRM()  VL128  W0  NOEVSR  ESIZE_16_BITS() NELEM_FULL() 
OPERANDS:    REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f16:TXT=BCASTSTR
IFORM:       VRSQRTPH_XMMf16_MASKmskw_MEMf16_AVX512
}


# EMITTING VRSQRTPH (VRSQRTPH-256-1)
{
ICLASS:      VRSQRTPH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_256
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX 
PATTERN:    EVV 0x4E V66 MAP6 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn]  VL256  W0  NOEVSR 
OPERANDS:    REG0=YMM_R3():w:qq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f16
IFORM:       VRSQRTPH_YMMf16_MASKmskw_YMMf16_AVX512
}

{
ICLASS:      VRSQRTPH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_256
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION 
PATTERN:    EVV 0x4E V66 MAP6 MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn]  MODRM()  VL256  W0  NOEVSR  ESIZE_16_BITS() NELEM_FULL() 
OPERANDS:    REG0=YMM_R3():w:qq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f16:TXT=BCASTSTR
IFORM:       VRSQRTPH_YMMf16_MASKmskw_MEMf16_AVX512
}


# EMITTING VRSQRTPH (VRSQRTPH-512-1)
{
ICLASS:      VRSQRTPH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_512
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX 
PATTERN:    EVV 0x4E V66 MAP6 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn]  VL512  W0  NOEVSR 
OPERANDS:    REG0=ZMM_R3():w:zf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf16
IFORM:       VRSQRTPH_ZMMf16_MASKmskw_ZMMf16_AVX512
}

{
ICLASS:      VRSQRTPH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_512
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION 
PATTERN:    EVV 0x4E V66 MAP6 MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn]  MODRM()  VL512  W0  NOEVSR  ESIZE_16_BITS() NELEM_FULL() 
OPERANDS:    REG0=ZMM_R3():w:zf16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f16:TXT=BCASTSTR
IFORM:       VRSQRTPH_ZMMf16_MASKmskw_MEMf16_AVX512
}


# EMITTING VRSQRTSH (VRSQRTSH-128-1)
{
ICLASS:      VRSQRTSH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_SCALAR
EXCEPTIONS:     AVX512-E10
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX SIMD_SCALAR 
PATTERN:    EVV 0x4F V66 MAP6 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn]  FIX_ROUND_LEN128() W0   
OPERANDS:    REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 REG3=XMM_B3():r:dq:f16
IFORM:       VRSQRTSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512
}

{
ICLASS:      VRSQRTSH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_SCALAR
EXCEPTIONS:     AVX512-E10
REAL_OPCODE: Y
ATTRIBUTES:  DISP8_SCALAR MASKOP_EVEX MEMORY_FAULT_SUPPRESSION SIMD_SCALAR 
PATTERN:    EVV 0x4F V66 MAP6 MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn] BCRC=0 MODRM()  FIX_ROUND_LEN128() W0    ESIZE_16_BITS() NELEM_SCALAR() 
OPERANDS:    REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 MEM0:r:wrd:f16
IFORM:       VRSQRTSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512
}


# EMITTING VSCALEFPH (VSCALEFPH-128-1)
{
ICLASS:      VSCALEFPH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_128
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR 
PATTERN:    EVV 0x2C V66 MAP6 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn]  VL128  W0   
OPERANDS:    REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 REG3=XMM_B3():r:dq:f16
IFORM:       VSCALEFPH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512
}

{
ICLASS:      VSCALEFPH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_128
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR 
PATTERN:    EVV 0x2C V66 MAP6 MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn]  MODRM()  VL128  W0    ESIZE_16_BITS() NELEM_FULL() 
OPERANDS:    REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 MEM0:r:vv:f16:TXT=BCASTSTR
IFORM:       VSCALEFPH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512
}


# EMITTING VSCALEFPH (VSCALEFPH-256-1)
{
ICLASS:      VSCALEFPH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_256
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR 
PATTERN:    EVV 0x2C V66 MAP6 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn]  VL256  W0   
OPERANDS:    REG0=YMM_R3():w:qq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f16 REG3=YMM_B3():r:qq:f16
IFORM:       VSCALEFPH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512
}

{
ICLASS:      VSCALEFPH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_256
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR 
PATTERN:    EVV 0x2C V66 MAP6 MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn]  MODRM()  VL256  W0    ESIZE_16_BITS() NELEM_FULL() 
OPERANDS:    REG0=YMM_R3():w:qq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f16 MEM0:r:vv:f16:TXT=BCASTSTR
IFORM:       VSCALEFPH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512
}


# EMITTING VSCALEFPH (VSCALEFPH-512-1)
{
ICLASS:      VSCALEFPH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR 
PATTERN:    EVV 0x2C V66 MAP6 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn]  VL512  W0   
OPERANDS:    REG0=ZMM_R3():w:zf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf16 REG3=ZMM_B3():r:zf16
IFORM:       VSCALEFPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512
}

{
ICLASS:      VSCALEFPH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR 
PATTERN:    EVV 0x2C V66 MAP6 MOD[0b11] MOD=3 BCRC=1 UBIT=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND()  W0   
OPERANDS:    REG0=ZMM_R3():w:zf16:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf16 REG3=ZMM_B3():r:zf16
IFORM:       VSCALEFPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512
}

{
ICLASS:      VSCALEFPH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR 
PATTERN:    EVV 0x2C V66 MAP6 MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn]  MODRM()  VL512  W0    ESIZE_16_BITS() NELEM_FULL() 
OPERANDS:    REG0=ZMM_R3():w:zf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf16 MEM0:r:vv:f16:TXT=BCASTSTR
IFORM:       VSCALEFPH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512
}


# EMITTING VSCALEFSH (VSCALEFSH-128-1)
{
ICLASS:      VSCALEFSH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_SCALAR
EXCEPTIONS:     AVX512-E3
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR SIMD_SCALAR 
PATTERN:    EVV 0x2D V66 MAP6 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn]  FIX_ROUND_LEN128() W0   
OPERANDS:    REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 REG3=XMM_B3():r:dq:f16
IFORM:       VSCALEFSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512
}

{
ICLASS:      VSCALEFSH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_SCALAR
EXCEPTIONS:     AVX512-E3
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR SIMD_SCALAR 
PATTERN:    EVV 0x2D V66 MAP6 MOD[0b11] MOD=3 BCRC=1 UBIT=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND()  W0   
OPERANDS:    REG0=XMM_R3():w:dq:f16:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 REG3=XMM_B3():r:dq:f16
IFORM:       VSCALEFSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512
}

{
ICLASS:      VSCALEFSH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_SCALAR
EXCEPTIONS:     AVX512-E3
REAL_OPCODE: Y
ATTRIBUTES:  DISP8_SCALAR MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR SIMD_SCALAR 
PATTERN:    EVV 0x2D V66 MAP6 MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn] BCRC=0 MODRM()  FIX_ROUND_LEN128() W0    ESIZE_16_BITS() NELEM_SCALAR() 
OPERANDS:    REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 MEM0:r:wrd:f16
IFORM:       VSCALEFSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512
}


# EMITTING VSQRTPH (VSQRTPH-128-1)
{
ICLASS:      VSQRTPH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_128
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR 
PATTERN:    EVV 0x51 VNP MAP5 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn]  VL128  W0  NOEVSR 
OPERANDS:    REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f16
IFORM:       VSQRTPH_XMMf16_MASKmskw_XMMf16_AVX512
}

{
ICLASS:      VSQRTPH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_128
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR 
PATTERN:    EVV 0x51 VNP MAP5 MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn]  MODRM()  VL128  W0  NOEVSR  ESIZE_16_BITS() NELEM_FULL() 
OPERANDS:    REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f16:TXT=BCASTSTR
IFORM:       VSQRTPH_XMMf16_MASKmskw_MEMf16_AVX512
}


# EMITTING VSQRTPH (VSQRTPH-256-1)
{
ICLASS:      VSQRTPH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_256
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR 
PATTERN:    EVV 0x51 VNP MAP5 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn]  VL256  W0  NOEVSR 
OPERANDS:    REG0=YMM_R3():w:qq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f16
IFORM:       VSQRTPH_YMMf16_MASKmskw_YMMf16_AVX512
}

{
ICLASS:      VSQRTPH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_256
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR 
PATTERN:    EVV 0x51 VNP MAP5 MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn]  MODRM()  VL256  W0  NOEVSR  ESIZE_16_BITS() NELEM_FULL() 
OPERANDS:    REG0=YMM_R3():w:qq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f16:TXT=BCASTSTR
IFORM:       VSQRTPH_YMMf16_MASKmskw_MEMf16_AVX512
}


# EMITTING VSQRTPH (VSQRTPH-512-1)
{
ICLASS:      VSQRTPH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR 
PATTERN:    EVV 0x51 VNP MAP5 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn]  VL512  W0  NOEVSR 
OPERANDS:    REG0=ZMM_R3():w:zf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf16
IFORM:       VSQRTPH_ZMMf16_MASKmskw_ZMMf16_AVX512
}

{
ICLASS:      VSQRTPH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR 
PATTERN:    EVV 0x51 VNP MAP5 MOD[0b11] MOD=3 BCRC=1 UBIT=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND()  W0  NOEVSR 
OPERANDS:    REG0=ZMM_R3():w:zf16:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf16
IFORM:       VSQRTPH_ZMMf16_MASKmskw_ZMMf16_AVX512
}

{
ICLASS:      VSQRTPH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR 
PATTERN:    EVV 0x51 VNP MAP5 MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn]  MODRM()  VL512  W0  NOEVSR  ESIZE_16_BITS() NELEM_FULL() 
OPERANDS:    REG0=ZMM_R3():w:zf16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f16:TXT=BCASTSTR
IFORM:       VSQRTPH_ZMMf16_MASKmskw_MEMf16_AVX512
}


# EMITTING VSQRTSH (VSQRTSH-128-1)
{
ICLASS:      VSQRTSH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_SCALAR
EXCEPTIONS:     AVX512-E3
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR SIMD_SCALAR 
PATTERN:    EVV 0x51 VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn]  FIX_ROUND_LEN128() W0   
OPERANDS:    REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 REG3=XMM_B3():r:dq:f16
IFORM:       VSQRTSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512
}

{
ICLASS:      VSQRTSH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_SCALAR
EXCEPTIONS:     AVX512-E3
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR SIMD_SCALAR 
PATTERN:    EVV 0x51 VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 UBIT=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND()  W0   
OPERANDS:    REG0=XMM_R3():w:dq:f16:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 REG3=XMM_B3():r:dq:f16
IFORM:       VSQRTSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512
}

{
ICLASS:      VSQRTSH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_SCALAR
EXCEPTIONS:     AVX512-E3
REAL_OPCODE: Y
ATTRIBUTES:  DISP8_SCALAR MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR SIMD_SCALAR 
PATTERN:    EVV 0x51 VF3 MAP5 MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn] BCRC=0 MODRM()  FIX_ROUND_LEN128() W0    ESIZE_16_BITS() NELEM_SCALAR() 
OPERANDS:    REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 MEM0:r:wrd:f16
IFORM:       VSQRTSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512
}


# EMITTING VSUBPH (VSUBPH-128-1)
{
ICLASS:      VSUBPH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_128
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR 
PATTERN:    EVV 0x5C VNP MAP5 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn]  VL128  W0   
OPERANDS:    REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 REG3=XMM_B3():r:dq:f16
IFORM:       VSUBPH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512
}

{
ICLASS:      VSUBPH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_128
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR 
PATTERN:    EVV 0x5C VNP MAP5 MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn]  MODRM()  VL128  W0    ESIZE_16_BITS() NELEM_FULL() 
OPERANDS:    REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 MEM0:r:vv:f16:TXT=BCASTSTR
IFORM:       VSUBPH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512
}


# EMITTING VSUBPH (VSUBPH-256-1)
{
ICLASS:      VSUBPH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_256
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR 
PATTERN:    EVV 0x5C VNP MAP5 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn]  VL256  W0   
OPERANDS:    REG0=YMM_R3():w:qq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f16 REG3=YMM_B3():r:qq:f16
IFORM:       VSUBPH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512
}

{
ICLASS:      VSUBPH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_256
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR 
PATTERN:    EVV 0x5C VNP MAP5 MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn]  MODRM()  VL256  W0    ESIZE_16_BITS() NELEM_FULL() 
OPERANDS:    REG0=YMM_R3():w:qq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f16 MEM0:r:vv:f16:TXT=BCASTSTR
IFORM:       VSUBPH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512
}


# EMITTING VSUBPH (VSUBPH-512-1)
{
ICLASS:      VSUBPH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR 
PATTERN:    EVV 0x5C VNP MAP5 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn]  VL512  W0   
OPERANDS:    REG0=ZMM_R3():w:zf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf16 REG3=ZMM_B3():r:zf16
IFORM:       VSUBPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512
}

{
ICLASS:      VSUBPH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR 
PATTERN:    EVV 0x5C VNP MAP5 MOD[0b11] MOD=3 BCRC=1 UBIT=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND()  W0   
OPERANDS:    REG0=ZMM_R3():w:zf16:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf16 REG3=ZMM_B3():r:zf16
IFORM:       VSUBPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512
}

{
ICLASS:      VSUBPH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_512
EXCEPTIONS:     AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR 
PATTERN:    EVV 0x5C VNP MAP5 MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn]  MODRM()  VL512  W0    ESIZE_16_BITS() NELEM_FULL() 
OPERANDS:    REG0=ZMM_R3():w:zf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf16 MEM0:r:vv:f16:TXT=BCASTSTR
IFORM:       VSUBPH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512
}


# EMITTING VSUBSH (VSUBSH-128-1)
{
ICLASS:      VSUBSH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_SCALAR
EXCEPTIONS:     AVX512-E3
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR SIMD_SCALAR 
PATTERN:    EVV 0x5C VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn]  FIX_ROUND_LEN128() W0   
OPERANDS:    REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 REG3=XMM_B3():r:dq:f16
IFORM:       VSUBSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512
}

{
ICLASS:      VSUBSH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_SCALAR
EXCEPTIONS:     AVX512-E3
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR SIMD_SCALAR 
PATTERN:    EVV 0x5C VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 UBIT=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND()  W0   
OPERANDS:    REG0=XMM_R3():w:dq:f16:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 REG3=XMM_B3():r:dq:f16
IFORM:       VSUBSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512
}

{
ICLASS:      VSUBSH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_SCALAR
EXCEPTIONS:     AVX512-E3
REAL_OPCODE: Y
ATTRIBUTES:  DISP8_SCALAR MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR SIMD_SCALAR 
PATTERN:    EVV 0x5C VF3 MAP5 MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn] BCRC=0 MODRM()  FIX_ROUND_LEN128() W0    ESIZE_16_BITS() NELEM_SCALAR() 
OPERANDS:    REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 MEM0:r:wrd:f16
IFORM:       VSUBSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512
}


# EMITTING VUCOMISH (VUCOMISH-128-1)
{
ICLASS:      VUCOMISH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_SCALAR
EXCEPTIONS:     AVX512-E3NF
REAL_OPCODE: Y
FLAGS:       MUST [  zf-mod pf-mod cf-mod of-0 sf-0 af-0  ]
ATTRIBUTES:  MXCSR SIMD_SCALAR 
PATTERN:    EVV 0x2E VNP MAP5 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn]  FIX_ROUND_LEN128() W0  NOEVSR  ZEROING=0 MASK=0 
OPERANDS:    REG0=XMM_R3():r:dq:f16 REG1=XMM_B3():r:dq:f16
IFORM:       VUCOMISH_XMMf16_XMMf16_AVX512
}

{
ICLASS:      VUCOMISH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_SCALAR
EXCEPTIONS:     AVX512-E3NF
REAL_OPCODE: Y
FLAGS:       MUST [  zf-mod pf-mod cf-mod of-0 sf-0 af-0  ]
ATTRIBUTES:  MXCSR SIMD_SCALAR 
PATTERN:    EVV 0x2E VNP MAP5 MOD[0b11] MOD=3 BCRC=1 UBIT=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE()  W0  NOEVSR  ZEROING=0 MASK=0 
OPERANDS:    REG0=XMM_R3():r:dq:f16:TXT=SAESTR REG1=XMM_B3():r:dq:f16
IFORM:       VUCOMISH_XMMf16_XMMf16_AVX512
}

{
ICLASS:      VUCOMISH
CPL:         3
CATEGORY:    FP16
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_SCALAR
EXCEPTIONS:     AVX512-E3NF
REAL_OPCODE: Y
FLAGS:       MUST [  zf-mod pf-mod cf-mod of-0 sf-0 af-0  ]
ATTRIBUTES:  DISP8_SCALAR MXCSR SIMD_SCALAR 
PATTERN:    EVV 0x2E VNP MAP5 MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn] BCRC=0 MODRM()  FIX_ROUND_LEN128() W0  NOEVSR  ZEROING=0 MASK=0  ESIZE_16_BITS() NELEM_SCALAR() 
OPERANDS:    REG0=XMM_R3():r:dq:f16 MEM0:r:wrd:f16
IFORM:       VUCOMISH_XMMf16_MEMf16_AVX512
}


