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########################################################################
## file: xed-reg-tables.txt
########################################################################

xed_reg_enum_t GPR8_R()::

REXR4=0 REXR=0 REG=0x0  | OUTREG=XED_REG_AL
REXR4=0 REXR=0 REG=0x1  | OUTREG=XED_REG_CL
REXR4=0 REXR=0 REG=0x2  | OUTREG=XED_REG_DL
REXR4=0 REXR=0 REG=0x3  | OUTREG=XED_REG_BL

REXR4=0 REXR=0 REG=0x4  REX=0  REX2=0  VEXVALID!=2 | OUTREG=XED_REG_AH
REXR4=0 REXR=0 REG=0x5  REX=0  REX2=0  VEXVALID!=2 | OUTREG=XED_REG_CH
REXR4=0 REXR=0 REG=0x6  REX=0  REX2=0  VEXVALID!=2 | OUTREG=XED_REG_DH 
REXR4=0 REXR=0 REG=0x7  REX=0  REX2=0  VEXVALID!=2 | OUTREG=XED_REG_BH

REXR4=0 REXR=0 REG=0x4  REX=1  REX2=0 | OUTREG=XED_REG_SPL
REXR4=0 REXR=0 REG=0x5  REX=1  REX2=0 | OUTREG=XED_REG_BPL
REXR4=0 REXR=0 REG=0x6  REX=1  REX2=0 | OUTREG=XED_REG_SIL
REXR4=0 REXR=0 REG=0x7  REX=1  REX2=0 | OUTREG=XED_REG_DIL

# REX2 prefix (REX prefix is "don't care"):
REXR4=0 REXR=0 REG=0x4         REX2=1 | OUTREG=XED_REG_SPL
REXR4=0 REXR=0 REG=0x5         REX2=1 | OUTREG=XED_REG_BPL
REXR4=0 REXR=0 REG=0x6         REX2=1 | OUTREG=XED_REG_SIL
REXR4=0 REXR=0 REG=0x7         REX2=1 | OUTREG=XED_REG_DIL

# EVEX implies REX
REXR4=0 REXR=0 REG=0x4  REX=0  REX2=0  EVV | OUTREG=XED_REG_SPL
REXR4=0 REXR=0 REG=0x5  REX=0  REX2=0  EVV | OUTREG=XED_REG_BPL
REXR4=0 REXR=0 REG=0x6  REX=0  REX2=0  EVV | OUTREG=XED_REG_SIL
REXR4=0 REXR=0 REG=0x7  REX=0  REX2=0  EVV | OUTREG=XED_REG_DIL

REXR4=0 REXR=1 REG=0x0  | OUTREG=XED_REG_R8B
REXR4=0 REXR=1 REG=0x1  | OUTREG=XED_REG_R9B
REXR4=0 REXR=1 REG=0x2  | OUTREG=XED_REG_R10B
REXR4=0 REXR=1 REG=0x3  | OUTREG=XED_REG_R11B
REXR4=0 REXR=1 REG=0x4  | OUTREG=XED_REG_R12B
REXR4=0 REXR=1 REG=0x5  | OUTREG=XED_REG_R13B
REXR4=0 REXR=1 REG=0x6  | OUTREG=XED_REG_R14B
REXR4=0 REXR=1 REG=0x7  | OUTREG=XED_REG_R15B


REXR4=1 REXR=0 REG=0x0  | OUTREG=XED_REG_R16B HAS_EGPR=1
REXR4=1 REXR=0 REG=0x1  | OUTREG=XED_REG_R17B HAS_EGPR=1
REXR4=1 REXR=0 REG=0x2  | OUTREG=XED_REG_R18B HAS_EGPR=1
REXR4=1 REXR=0 REG=0x3  | OUTREG=XED_REG_R19B HAS_EGPR=1
REXR4=1 REXR=0 REG=0x4  | OUTREG=XED_REG_R20B HAS_EGPR=1
REXR4=1 REXR=0 REG=0x5  | OUTREG=XED_REG_R21B HAS_EGPR=1
REXR4=1 REXR=0 REG=0x6  | OUTREG=XED_REG_R22B HAS_EGPR=1
REXR4=1 REXR=0 REG=0x7  | OUTREG=XED_REG_R23B HAS_EGPR=1

REXR4=1 REXR=1 REG=0x0  | OUTREG=XED_REG_R24B HAS_EGPR=1
REXR4=1 REXR=1 REG=0x1  | OUTREG=XED_REG_R25B HAS_EGPR=1
REXR4=1 REXR=1 REG=0x2  | OUTREG=XED_REG_R26B HAS_EGPR=1
REXR4=1 REXR=1 REG=0x3  | OUTREG=XED_REG_R27B HAS_EGPR=1
REXR4=1 REXR=1 REG=0x4  | OUTREG=XED_REG_R28B HAS_EGPR=1
REXR4=1 REXR=1 REG=0x5  | OUTREG=XED_REG_R29B HAS_EGPR=1
REXR4=1 REXR=1 REG=0x6  | OUTREG=XED_REG_R30B HAS_EGPR=1
REXR4=1 REXR=1 REG=0x7  | OUTREG=XED_REG_R31B HAS_EGPR=1


xed_reg_enum_t GPR8_B()::
REXB4=0 REXB=0 RM=0x0  | OUTREG=XED_REG_AL 
REXB4=0 REXB=0 RM=0x1  | OUTREG=XED_REG_CL
REXB4=0 REXB=0 RM=0x2  | OUTREG=XED_REG_DL
REXB4=0 REXB=0 RM=0x3  | OUTREG=XED_REG_BL

REXB4=0 REXB=0 RM=0x4  REX=0  REX2=0  VEXVALID!=2 | OUTREG=XED_REG_AH
REXB4=0 REXB=0 RM=0x5  REX=0  REX2=0  VEXVALID!=2 | OUTREG=XED_REG_CH
REXB4=0 REXB=0 RM=0x6  REX=0  REX2=0  VEXVALID!=2 | OUTREG=XED_REG_DH 
REXB4=0 REXB=0 RM=0x7  REX=0  REX2=0  VEXVALID!=2 | OUTREG=XED_REG_BH

REXB4=0 REXB=0 RM=0x4  REX=1  REX2=0 | OUTREG=XED_REG_SPL
REXB4=0 REXB=0 RM=0x5  REX=1  REX2=0 | OUTREG=XED_REG_BPL
REXB4=0 REXB=0 RM=0x6  REX=1  REX2=0 | OUTREG=XED_REG_SIL
REXB4=0 REXB=0 RM=0x7  REX=1  REX2=0 | OUTREG=XED_REG_DIL

# REX2 prefix (REX prefix is "don't care"):
REXB4=0 REXB=0 RM=0x4         REX2=1 | OUTREG=XED_REG_SPL
REXB4=0 REXB=0 RM=0x5         REX2=1 | OUTREG=XED_REG_BPL
REXB4=0 REXB=0 RM=0x6         REX2=1 | OUTREG=XED_REG_SIL
REXB4=0 REXB=0 RM=0x7         REX2=1 | OUTREG=XED_REG_DIL

# EVEX implies REX
REXB4=0 REXB=0 RM=0x4  REX=0  REX2=0  EVV | OUTREG=XED_REG_SPL
REXB4=0 REXB=0 RM=0x5  REX=0  REX2=0  EVV | OUTREG=XED_REG_BPL
REXB4=0 REXB=0 RM=0x6  REX=0  REX2=0  EVV | OUTREG=XED_REG_SIL
REXB4=0 REXB=0 RM=0x7  REX=0  REX2=0  EVV | OUTREG=XED_REG_DIL

REXB4=0 REXB=1 RM=0x0  | OUTREG=XED_REG_R8B
REXB4=0 REXB=1 RM=0x1  | OUTREG=XED_REG_R9B
REXB4=0 REXB=1 RM=0x2  | OUTREG=XED_REG_R10B
REXB4=0 REXB=1 RM=0x3  | OUTREG=XED_REG_R11B
REXB4=0 REXB=1 RM=0x4  | OUTREG=XED_REG_R12B
REXB4=0 REXB=1 RM=0x5  | OUTREG=XED_REG_R13B
REXB4=0 REXB=1 RM=0x6  | OUTREG=XED_REG_R14B
REXB4=0 REXB=1 RM=0x7  | OUTREG=XED_REG_R15B


REXB4=1 REXB=0 RM=0x0  | OUTREG=XED_REG_R16B HAS_EGPR=1
REXB4=1 REXB=0 RM=0x1  | OUTREG=XED_REG_R17B HAS_EGPR=1
REXB4=1 REXB=0 RM=0x2  | OUTREG=XED_REG_R18B HAS_EGPR=1
REXB4=1 REXB=0 RM=0x3  | OUTREG=XED_REG_R19B HAS_EGPR=1
REXB4=1 REXB=0 RM=0x4  | OUTREG=XED_REG_R20B HAS_EGPR=1
REXB4=1 REXB=0 RM=0x5  | OUTREG=XED_REG_R21B HAS_EGPR=1
REXB4=1 REXB=0 RM=0x6  | OUTREG=XED_REG_R22B HAS_EGPR=1
REXB4=1 REXB=0 RM=0x7  | OUTREG=XED_REG_R23B HAS_EGPR=1

REXB4=1 REXB=1 RM=0x0  | OUTREG=XED_REG_R24B HAS_EGPR=1
REXB4=1 REXB=1 RM=0x1  | OUTREG=XED_REG_R25B HAS_EGPR=1
REXB4=1 REXB=1 RM=0x2  | OUTREG=XED_REG_R26B HAS_EGPR=1
REXB4=1 REXB=1 RM=0x3  | OUTREG=XED_REG_R27B HAS_EGPR=1
REXB4=1 REXB=1 RM=0x4  | OUTREG=XED_REG_R28B HAS_EGPR=1
REXB4=1 REXB=1 RM=0x5  | OUTREG=XED_REG_R29B HAS_EGPR=1
REXB4=1 REXB=1 RM=0x6  | OUTREG=XED_REG_R30B HAS_EGPR=1
REXB4=1 REXB=1 RM=0x7  | OUTREG=XED_REG_R31B HAS_EGPR=1


xed_reg_enum_t GPR8_SB()::
REXB4=0 REXB=0 SRM=0x0  | OUTREG=XED_REG_AL 
REXB4=0 REXB=0 SRM=0x1  | OUTREG=XED_REG_CL
REXB4=0 REXB=0 SRM=0x2  | OUTREG=XED_REG_DL
REXB4=0 REXB=0 SRM=0x3  | OUTREG=XED_REG_BL

REXB4=0 REXB=0 SRM=0x4  REX=0  REX2=0  VEXVALID!=2 | OUTREG=XED_REG_AH
REXB4=0 REXB=0 SRM=0x5  REX=0  REX2=0  VEXVALID!=2 | OUTREG=XED_REG_CH
REXB4=0 REXB=0 SRM=0x6  REX=0  REX2=0  VEXVALID!=2 | OUTREG=XED_REG_DH 
REXB4=0 REXB=0 SRM=0x7  REX=0  REX2=0  VEXVALID!=2 | OUTREG=XED_REG_BH

REXB4=0 REXB=0 SRM=0x4  REX=1  REX2=0 | OUTREG=XED_REG_SPL
REXB4=0 REXB=0 SRM=0x5  REX=1  REX2=0 | OUTREG=XED_REG_BPL
REXB4=0 REXB=0 SRM=0x6  REX=1  REX2=0 | OUTREG=XED_REG_SIL
REXB4=0 REXB=0 SRM=0x7  REX=1  REX2=0 | OUTREG=XED_REG_DIL

# REX2 prefix (REX prefix is "don't care"):
REXB4=0 REXB=0 SRM=0x4         REX2=1 | OUTREG=XED_REG_SPL
REXB4=0 REXB=0 SRM=0x5         REX2=1 | OUTREG=XED_REG_BPL
REXB4=0 REXB=0 SRM=0x6         REX2=1 | OUTREG=XED_REG_SIL
REXB4=0 REXB=0 SRM=0x7         REX2=1 | OUTREG=XED_REG_DIL

# EVEX implies REX
REXB4=0 REXB=0 SRM=0x4  REX=0  REX2=0  EVV | OUTREG=XED_REG_SPL
REXB4=0 REXB=0 SRM=0x5  REX=0  REX2=0  EVV | OUTREG=XED_REG_BPL
REXB4=0 REXB=0 SRM=0x6  REX=0  REX2=0  EVV | OUTREG=XED_REG_SIL
REXB4=0 REXB=0 SRM=0x7  REX=0  REX2=0  EVV | OUTREG=XED_REG_DIL

REXB4=0 REXB=1 SRM=0x0  | OUTREG=XED_REG_R8B
REXB4=0 REXB=1 SRM=0x1  | OUTREG=XED_REG_R9B
REXB4=0 REXB=1 SRM=0x2  | OUTREG=XED_REG_R10B
REXB4=0 REXB=1 SRM=0x3  | OUTREG=XED_REG_R11B
REXB4=0 REXB=1 SRM=0x4  | OUTREG=XED_REG_R12B
REXB4=0 REXB=1 SRM=0x5  | OUTREG=XED_REG_R13B
REXB4=0 REXB=1 SRM=0x6  | OUTREG=XED_REG_R14B
REXB4=0 REXB=1 SRM=0x7  | OUTREG=XED_REG_R15B


REXB4=1 REXB=0 SRM=0x0  | OUTREG=XED_REG_R16B HAS_EGPR=1
REXB4=1 REXB=0 SRM=0x1  | OUTREG=XED_REG_R17B HAS_EGPR=1
REXB4=1 REXB=0 SRM=0x2  | OUTREG=XED_REG_R18B HAS_EGPR=1
REXB4=1 REXB=0 SRM=0x3  | OUTREG=XED_REG_R19B HAS_EGPR=1
REXB4=1 REXB=0 SRM=0x4  | OUTREG=XED_REG_R20B HAS_EGPR=1
REXB4=1 REXB=0 SRM=0x5  | OUTREG=XED_REG_R21B HAS_EGPR=1
REXB4=1 REXB=0 SRM=0x6  | OUTREG=XED_REG_R22B HAS_EGPR=1
REXB4=1 REXB=0 SRM=0x7  | OUTREG=XED_REG_R23B HAS_EGPR=1

REXB4=1 REXB=1 SRM=0x0  | OUTREG=XED_REG_R24B HAS_EGPR=1
REXB4=1 REXB=1 SRM=0x1  | OUTREG=XED_REG_R25B HAS_EGPR=1
REXB4=1 REXB=1 SRM=0x2  | OUTREG=XED_REG_R26B HAS_EGPR=1
REXB4=1 REXB=1 SRM=0x3  | OUTREG=XED_REG_R27B HAS_EGPR=1
REXB4=1 REXB=1 SRM=0x4  | OUTREG=XED_REG_R28B HAS_EGPR=1
REXB4=1 REXB=1 SRM=0x5  | OUTREG=XED_REG_R29B HAS_EGPR=1
REXB4=1 REXB=1 SRM=0x6  | OUTREG=XED_REG_R30B HAS_EGPR=1
REXB4=1 REXB=1 SRM=0x7  | OUTREG=XED_REG_R31B HAS_EGPR=1
