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EVEX_INSTRUCTIONS()::
# EMITTING VCVT2PS2PHX (VCVT2PS2PHX-128-1)
{
ICLASS:      VCVT2PS2PHX
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_CONVERT_128
EXCEPTIONS:  AVX512-E4NF
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR USES_DAZ 
PATTERN:     EVV 0x67 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn] W0 VL128
OPERANDS:    REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32
IFORM:       VCVT2PS2PHX_XMMf16_MASKmskw_XMMf32_XMMf32_AVX512
}

{
ICLASS:      VCVT2PS2PHX
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_CONVERT_128
EXCEPTIONS:  AVX512-E4NF
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MXCSR USES_DAZ 
PATTERN:     EVV 0x67 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UBIT=1 W0 VL128 ESIZE_32_BITS() NELEM_FULL()
OPERANDS:    REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR
IFORM:       VCVT2PS2PHX_XMMf16_MASKmskw_XMMf32_MEMf32_AVX512
}


# EMITTING VCVT2PS2PHX (VCVT2PS2PHX-256-1)
{
ICLASS:      VCVT2PS2PHX
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_CONVERT_256
EXCEPTIONS:  AVX512-E4NF
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR USES_DAZ 
PATTERN:     EVV 0x67 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn] W0 VL256
OPERANDS:    REG0=YMM_R3():w:qq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32
IFORM:       VCVT2PS2PHX_YMMf16_MASKmskw_YMMf32_YMMf32_AVX512
}

{
ICLASS:      VCVT2PS2PHX
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_CONVERT_256
EXCEPTIONS:  AVX512-E4NF
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR USES_DAZ 
PATTERN:     EVV 0x67 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 UBIT=0 REG[rrr] RM[nnn] W0 FIX_ROUND_LEN256() AVX256_ROUND()
OPERANDS:    REG0=YMM_R3():w:qq:f16:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32
IFORM:       VCVT2PS2PHX_YMMf16_MASKmskw_YMMf32_YMMf32_AVX512
}

{
ICLASS:      VCVT2PS2PHX
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_CONVERT_256
EXCEPTIONS:  AVX512-E4NF
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MXCSR USES_DAZ 
PATTERN:     EVV 0x67 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UBIT=1 W0 VL256 ESIZE_32_BITS() NELEM_FULL()
OPERANDS:    REG0=YMM_R3():w:qq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR
IFORM:       VCVT2PS2PHX_YMMf16_MASKmskw_YMMf32_MEMf32_AVX512
}


# EMITTING VCVT2PS2PHX (VCVT2PS2PHX-512-1)
{
ICLASS:      VCVT2PS2PHX
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_CONVERT_512
EXCEPTIONS:  AVX512-E4NF
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR USES_DAZ 
PATTERN:     EVV 0x67 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn] W0 VL512
OPERANDS:    REG0=ZMM_R3():w:zf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32
IFORM:       VCVT2PS2PHX_ZMMf16_MASKmskw_ZMMf32_ZMMf32_AVX512
}

{
ICLASS:      VCVT2PS2PHX
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_CONVERT_512
EXCEPTIONS:  AVX512-E4NF
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR USES_DAZ 
PATTERN:     EVV 0x67 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 UBIT=1 REG[rrr] RM[nnn] W0 FIX_ROUND_LEN512() AVX512_ROUND()
OPERANDS:    REG0=ZMM_R3():w:zf16:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32
IFORM:       VCVT2PS2PHX_ZMMf16_MASKmskw_ZMMf32_ZMMf32_AVX512
}

{
ICLASS:      VCVT2PS2PHX
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_FP16_CONVERT_512
EXCEPTIONS:  AVX512-E4NF
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MXCSR USES_DAZ 
PATTERN:     EVV 0x67 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UBIT=1 W0 VL512 ESIZE_32_BITS() NELEM_FULL()
OPERANDS:    REG0=ZMM_R3():w:zf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR
IFORM:       VCVT2PS2PHX_ZMMf16_MASKmskw_ZMMf32_MEMf32_AVX512
}


# EMITTING VCVTBIASPH2BF8 (VCVTBIASPH2BF8-128-1)
{
ICLASS:      VCVTBIASPH2BF8
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_NE_CONVERT_FP8_128
EXCEPTIONS:  AVX512-E4NF
REAL_OPCODE: Y
ATTRIBUTES:  FIXED_ROUNDING_RNE MASKOP_EVEX MXCSR 
PATTERN:     EVV 0x74 VNP V0F38 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn] W0 VL128
OPERANDS:    REG0=XMM_R3():w:dq:bf8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:2i8 REG3=XMM_B3():r:dq:f16
IFORM:       VCVTBIASPH2BF8_XMMbf8_MASKmskw_XMM2i8_XMMf16_AVX512
}

{
ICLASS:      VCVTBIASPH2BF8
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_NE_CONVERT_FP8_128
EXCEPTIONS:  AVX512-E4NF
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL FIXED_ROUNDING_RNE MASKOP_EVEX MXCSR 
PATTERN:     EVV 0x74 VNP V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UBIT=1 W0 VL128 ESIZE_16_BITS() NELEM_FULL()
OPERANDS:    REG0=XMM_R3():w:dq:bf8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:2i8 MEM0:r:vv:f16:TXT=BCASTSTR
IFORM:       VCVTBIASPH2BF8_XMMbf8_MASKmskw_XMM2i8_MEMf16_AVX512_VL128
}


# EMITTING VCVTBIASPH2BF8 (VCVTBIASPH2BF8-256-1)
{
ICLASS:      VCVTBIASPH2BF8
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_NE_CONVERT_FP8_256
EXCEPTIONS:  AVX512-E4NF
REAL_OPCODE: Y
ATTRIBUTES:  FIXED_ROUNDING_RNE MASKOP_EVEX MXCSR 
PATTERN:     EVV 0x74 VNP V0F38 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn] W0 VL256
OPERANDS:    REG0=XMM_R3():w:dq:bf8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:2i8 REG3=YMM_B3():r:qq:f16
IFORM:       VCVTBIASPH2BF8_XMMbf8_MASKmskw_YMM2i8_YMMf16_AVX512
}

{
ICLASS:      VCVTBIASPH2BF8
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_NE_CONVERT_FP8_256
EXCEPTIONS:  AVX512-E4NF
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL FIXED_ROUNDING_RNE MASKOP_EVEX MXCSR 
PATTERN:     EVV 0x74 VNP V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UBIT=1 W0 VL256 ESIZE_16_BITS() NELEM_FULL()
OPERANDS:    REG0=XMM_R3():w:dq:bf8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:2i8 MEM0:r:vv:f16:TXT=BCASTSTR
IFORM:       VCVTBIASPH2BF8_XMMbf8_MASKmskw_YMM2i8_MEMf16_AVX512_VL256
}


# EMITTING VCVTBIASPH2BF8 (VCVTBIASPH2BF8-512-1)
{
ICLASS:      VCVTBIASPH2BF8
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_NE_CONVERT_FP8_512
EXCEPTIONS:  AVX512-E4NF
REAL_OPCODE: Y
ATTRIBUTES:  FIXED_ROUNDING_RNE MASKOP_EVEX MXCSR 
PATTERN:     EVV 0x74 VNP V0F38 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn] W0 VL512
OPERANDS:    REG0=YMM_R3():w:qq:bf8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:z2i8 REG3=ZMM_B3():r:zf16
IFORM:       VCVTBIASPH2BF8_YMMbf8_MASKmskw_ZMM2i8_ZMMf16_AVX512
}

{
ICLASS:      VCVTBIASPH2BF8
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_NE_CONVERT_FP8_512
EXCEPTIONS:  AVX512-E4NF
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL FIXED_ROUNDING_RNE MASKOP_EVEX MXCSR 
PATTERN:     EVV 0x74 VNP V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UBIT=1 W0 VL512 ESIZE_16_BITS() NELEM_FULL()
OPERANDS:    REG0=YMM_R3():w:qq:bf8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:z2i8 MEM0:r:vv:f16:TXT=BCASTSTR
IFORM:       VCVTBIASPH2BF8_YMMbf8_MASKmskw_ZMM2i8_MEMf16_AVX512_VL512
}


# EMITTING VCVTBIASPH2BF8S (VCVTBIASPH2BF8S-128-1)
{
ICLASS:      VCVTBIASPH2BF8S
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_NE_CONVERT_FP8_128
EXCEPTIONS:  AVX512-E4NF
REAL_OPCODE: Y
ATTRIBUTES:  FIXED_ROUNDING_RNE MASKOP_EVEX MXCSR 
PATTERN:     EVV 0x74 VNP MAP5 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn] W0 VL128
OPERANDS:    REG0=XMM_R3():w:dq:bf8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:2i8 REG3=XMM_B3():r:dq:f16
IFORM:       VCVTBIASPH2BF8S_XMMbf8_MASKmskw_XMM2i8_XMMf16_AVX512
}

{
ICLASS:      VCVTBIASPH2BF8S
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_NE_CONVERT_FP8_128
EXCEPTIONS:  AVX512-E4NF
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL FIXED_ROUNDING_RNE MASKOP_EVEX MXCSR 
PATTERN:     EVV 0x74 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UBIT=1 W0 VL128 ESIZE_16_BITS() NELEM_FULL()
OPERANDS:    REG0=XMM_R3():w:dq:bf8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:2i8 MEM0:r:vv:f16:TXT=BCASTSTR
IFORM:       VCVTBIASPH2BF8S_XMMbf8_MASKmskw_XMM2i8_MEMf16_AVX512_VL128
}


# EMITTING VCVTBIASPH2BF8S (VCVTBIASPH2BF8S-256-1)
{
ICLASS:      VCVTBIASPH2BF8S
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_NE_CONVERT_FP8_256
EXCEPTIONS:  AVX512-E4NF
REAL_OPCODE: Y
ATTRIBUTES:  FIXED_ROUNDING_RNE MASKOP_EVEX MXCSR 
PATTERN:     EVV 0x74 VNP MAP5 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn] W0 VL256
OPERANDS:    REG0=XMM_R3():w:dq:bf8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:2i8 REG3=YMM_B3():r:qq:f16
IFORM:       VCVTBIASPH2BF8S_XMMbf8_MASKmskw_YMM2i8_YMMf16_AVX512
}

{
ICLASS:      VCVTBIASPH2BF8S
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_NE_CONVERT_FP8_256
EXCEPTIONS:  AVX512-E4NF
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL FIXED_ROUNDING_RNE MASKOP_EVEX MXCSR 
PATTERN:     EVV 0x74 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UBIT=1 W0 VL256 ESIZE_16_BITS() NELEM_FULL()
OPERANDS:    REG0=XMM_R3():w:dq:bf8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:2i8 MEM0:r:vv:f16:TXT=BCASTSTR
IFORM:       VCVTBIASPH2BF8S_XMMbf8_MASKmskw_YMM2i8_MEMf16_AVX512_VL256
}


# EMITTING VCVTBIASPH2BF8S (VCVTBIASPH2BF8S-512-1)
{
ICLASS:      VCVTBIASPH2BF8S
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_NE_CONVERT_FP8_512
EXCEPTIONS:  AVX512-E4NF
REAL_OPCODE: Y
ATTRIBUTES:  FIXED_ROUNDING_RNE MASKOP_EVEX MXCSR 
PATTERN:     EVV 0x74 VNP MAP5 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn] W0 VL512
OPERANDS:    REG0=YMM_R3():w:qq:bf8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:z2i8 REG3=ZMM_B3():r:zf16
IFORM:       VCVTBIASPH2BF8S_YMMbf8_MASKmskw_ZMM2i8_ZMMf16_AVX512
}

{
ICLASS:      VCVTBIASPH2BF8S
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_NE_CONVERT_FP8_512
EXCEPTIONS:  AVX512-E4NF
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL FIXED_ROUNDING_RNE MASKOP_EVEX MXCSR 
PATTERN:     EVV 0x74 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UBIT=1 W0 VL512 ESIZE_16_BITS() NELEM_FULL()
OPERANDS:    REG0=YMM_R3():w:qq:bf8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:z2i8 MEM0:r:vv:f16:TXT=BCASTSTR
IFORM:       VCVTBIASPH2BF8S_YMMbf8_MASKmskw_ZMM2i8_MEMf16_AVX512_VL512
}


# EMITTING VCVTBIASPH2HF8 (VCVTBIASPH2HF8-128-1)
{
ICLASS:      VCVTBIASPH2HF8
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_NE_CONVERT_FP8_128
EXCEPTIONS:  AVX512-E4NF
REAL_OPCODE: Y
ATTRIBUTES:  FIXED_ROUNDING_RNE MASKOP_EVEX MXCSR 
PATTERN:     EVV 0x18 VNP MAP5 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn] W0 VL128
OPERANDS:    REG0=XMM_R3():w:dq:hf8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:2i8 REG3=XMM_B3():r:dq:f16
IFORM:       VCVTBIASPH2HF8_XMMhf8_MASKmskw_XMM2i8_XMMf16_AVX512
}

{
ICLASS:      VCVTBIASPH2HF8
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_NE_CONVERT_FP8_128
EXCEPTIONS:  AVX512-E4NF
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL FIXED_ROUNDING_RNE MASKOP_EVEX MXCSR 
PATTERN:     EVV 0x18 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UBIT=1 W0 VL128 ESIZE_16_BITS() NELEM_FULL()
OPERANDS:    REG0=XMM_R3():w:dq:hf8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:2i8 MEM0:r:vv:f16:TXT=BCASTSTR
IFORM:       VCVTBIASPH2HF8_XMMhf8_MASKmskw_XMM2i8_MEMf16_AVX512_VL128
}


# EMITTING VCVTBIASPH2HF8 (VCVTBIASPH2HF8-256-1)
{
ICLASS:      VCVTBIASPH2HF8
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_NE_CONVERT_FP8_256
EXCEPTIONS:  AVX512-E4NF
REAL_OPCODE: Y
ATTRIBUTES:  FIXED_ROUNDING_RNE MASKOP_EVEX MXCSR 
PATTERN:     EVV 0x18 VNP MAP5 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn] W0 VL256
OPERANDS:    REG0=XMM_R3():w:dq:hf8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:2i8 REG3=YMM_B3():r:qq:f16
IFORM:       VCVTBIASPH2HF8_XMMhf8_MASKmskw_YMM2i8_YMMf16_AVX512
}

{
ICLASS:      VCVTBIASPH2HF8
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_NE_CONVERT_FP8_256
EXCEPTIONS:  AVX512-E4NF
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL FIXED_ROUNDING_RNE MASKOP_EVEX MXCSR 
PATTERN:     EVV 0x18 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UBIT=1 W0 VL256 ESIZE_16_BITS() NELEM_FULL()
OPERANDS:    REG0=XMM_R3():w:dq:hf8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:2i8 MEM0:r:vv:f16:TXT=BCASTSTR
IFORM:       VCVTBIASPH2HF8_XMMhf8_MASKmskw_YMM2i8_MEMf16_AVX512_VL256
}


# EMITTING VCVTBIASPH2HF8 (VCVTBIASPH2HF8-512-1)
{
ICLASS:      VCVTBIASPH2HF8
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_NE_CONVERT_FP8_512
EXCEPTIONS:  AVX512-E4NF
REAL_OPCODE: Y
ATTRIBUTES:  FIXED_ROUNDING_RNE MASKOP_EVEX MXCSR 
PATTERN:     EVV 0x18 VNP MAP5 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn] W0 VL512
OPERANDS:    REG0=YMM_R3():w:qq:hf8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:z2i8 REG3=ZMM_B3():r:zf16
IFORM:       VCVTBIASPH2HF8_YMMhf8_MASKmskw_ZMM2i8_ZMMf16_AVX512
}

{
ICLASS:      VCVTBIASPH2HF8
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_NE_CONVERT_FP8_512
EXCEPTIONS:  AVX512-E4NF
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL FIXED_ROUNDING_RNE MASKOP_EVEX MXCSR 
PATTERN:     EVV 0x18 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UBIT=1 W0 VL512 ESIZE_16_BITS() NELEM_FULL()
OPERANDS:    REG0=YMM_R3():w:qq:hf8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:z2i8 MEM0:r:vv:f16:TXT=BCASTSTR
IFORM:       VCVTBIASPH2HF8_YMMhf8_MASKmskw_ZMM2i8_MEMf16_AVX512_VL512
}


# EMITTING VCVTBIASPH2HF8S (VCVTBIASPH2HF8S-128-1)
{
ICLASS:      VCVTBIASPH2HF8S
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_NE_CONVERT_FP8_128
EXCEPTIONS:  AVX512-E4NF
REAL_OPCODE: Y
ATTRIBUTES:  FIXED_ROUNDING_RNE MASKOP_EVEX MXCSR 
PATTERN:     EVV 0x1B VNP MAP5 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn] W0 VL128
OPERANDS:    REG0=XMM_R3():w:dq:hf8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:2i8 REG3=XMM_B3():r:dq:f16
IFORM:       VCVTBIASPH2HF8S_XMMhf8_MASKmskw_XMM2i8_XMMf16_AVX512
}

{
ICLASS:      VCVTBIASPH2HF8S
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_NE_CONVERT_FP8_128
EXCEPTIONS:  AVX512-E4NF
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL FIXED_ROUNDING_RNE MASKOP_EVEX MXCSR 
PATTERN:     EVV 0x1B VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UBIT=1 W0 VL128 ESIZE_16_BITS() NELEM_FULL()
OPERANDS:    REG0=XMM_R3():w:dq:hf8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:2i8 MEM0:r:vv:f16:TXT=BCASTSTR
IFORM:       VCVTBIASPH2HF8S_XMMhf8_MASKmskw_XMM2i8_MEMf16_AVX512_VL128
}


# EMITTING VCVTBIASPH2HF8S (VCVTBIASPH2HF8S-256-1)
{
ICLASS:      VCVTBIASPH2HF8S
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_NE_CONVERT_FP8_256
EXCEPTIONS:  AVX512-E4NF
REAL_OPCODE: Y
ATTRIBUTES:  FIXED_ROUNDING_RNE MASKOP_EVEX MXCSR 
PATTERN:     EVV 0x1B VNP MAP5 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn] W0 VL256
OPERANDS:    REG0=XMM_R3():w:dq:hf8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:2i8 REG3=YMM_B3():r:qq:f16
IFORM:       VCVTBIASPH2HF8S_XMMhf8_MASKmskw_YMM2i8_YMMf16_AVX512
}

{
ICLASS:      VCVTBIASPH2HF8S
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_NE_CONVERT_FP8_256
EXCEPTIONS:  AVX512-E4NF
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL FIXED_ROUNDING_RNE MASKOP_EVEX MXCSR 
PATTERN:     EVV 0x1B VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UBIT=1 W0 VL256 ESIZE_16_BITS() NELEM_FULL()
OPERANDS:    REG0=XMM_R3():w:dq:hf8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:2i8 MEM0:r:vv:f16:TXT=BCASTSTR
IFORM:       VCVTBIASPH2HF8S_XMMhf8_MASKmskw_YMM2i8_MEMf16_AVX512_VL256
}


# EMITTING VCVTBIASPH2HF8S (VCVTBIASPH2HF8S-512-1)
{
ICLASS:      VCVTBIASPH2HF8S
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_NE_CONVERT_FP8_512
EXCEPTIONS:  AVX512-E4NF
REAL_OPCODE: Y
ATTRIBUTES:  FIXED_ROUNDING_RNE MASKOP_EVEX MXCSR 
PATTERN:     EVV 0x1B VNP MAP5 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn] W0 VL512
OPERANDS:    REG0=YMM_R3():w:qq:hf8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:z2i8 REG3=ZMM_B3():r:zf16
IFORM:       VCVTBIASPH2HF8S_YMMhf8_MASKmskw_ZMM2i8_ZMMf16_AVX512
}

{
ICLASS:      VCVTBIASPH2HF8S
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_NE_CONVERT_FP8_512
EXCEPTIONS:  AVX512-E4NF
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL FIXED_ROUNDING_RNE MASKOP_EVEX MXCSR 
PATTERN:     EVV 0x1B VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UBIT=1 W0 VL512 ESIZE_16_BITS() NELEM_FULL()
OPERANDS:    REG0=YMM_R3():w:qq:hf8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:z2i8 MEM0:r:vv:f16:TXT=BCASTSTR
IFORM:       VCVTBIASPH2HF8S_YMMhf8_MASKmskw_ZMM2i8_MEMf16_AVX512_VL512
}


# EMITTING VCVTHF82PH (VCVTHF82PH-128-1)
{
ICLASS:      VCVTHF82PH
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_NE_CONVERT_FP8_128
EXCEPTIONS:  AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  FIXED_ROUNDING_RNE FLUSH_OUTPUT_DENORM MASKOP_EVEX MXCSR 
PATTERN:     EVV 0x1E VF2 MAP5 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn] W0 VL128 NOEVSR
OPERANDS:    REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:hf8
IFORM:       VCVTHF82PH_XMMf16_MASKmskw_XMMhf8_AVX512
}

{
ICLASS:      VCVTHF82PH
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_NE_CONVERT_FP8_128
EXCEPTIONS:  AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  DISP8_HALF FIXED_ROUNDING_RNE FLUSH_OUTPUT_DENORM MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR 
PATTERN:     EVV 0x1E VF2 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() BCRC=0 UBIT=1 W0 VL128 NOEVSR ESIZE_8_BITS() NELEM_HALF()
OPERANDS:    REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:q:hf8
IFORM:       VCVTHF82PH_XMMf16_MASKmskw_MEMhf8_AVX512
}


# EMITTING VCVTHF82PH (VCVTHF82PH-256-1)
{
ICLASS:      VCVTHF82PH
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_NE_CONVERT_FP8_256
EXCEPTIONS:  AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  FIXED_ROUNDING_RNE FLUSH_OUTPUT_DENORM MASKOP_EVEX MXCSR 
PATTERN:     EVV 0x1E VF2 MAP5 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn] W0 VL256 NOEVSR
OPERANDS:    REG0=YMM_R3():w:qq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:hf8
IFORM:       VCVTHF82PH_YMMf16_MASKmskw_XMMhf8_AVX512
}

{
ICLASS:      VCVTHF82PH
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_NE_CONVERT_FP8_256
EXCEPTIONS:  AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  DISP8_HALF FIXED_ROUNDING_RNE FLUSH_OUTPUT_DENORM MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR 
PATTERN:     EVV 0x1E VF2 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() BCRC=0 UBIT=1 W0 VL256 NOEVSR ESIZE_8_BITS() NELEM_HALF()
OPERANDS:    REG0=YMM_R3():w:qq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:hf8
IFORM:       VCVTHF82PH_YMMf16_MASKmskw_MEMhf8_AVX512
}


# EMITTING VCVTHF82PH (VCVTHF82PH-512-1)
{
ICLASS:      VCVTHF82PH
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_NE_CONVERT_FP8_512
EXCEPTIONS:  AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  FIXED_ROUNDING_RNE FLUSH_OUTPUT_DENORM MASKOP_EVEX MXCSR 
PATTERN:     EVV 0x1E VF2 MAP5 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn] W0 VL512 NOEVSR
OPERANDS:    REG0=ZMM_R3():w:zf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:hf8
IFORM:       VCVTHF82PH_ZMMf16_MASKmskw_YMMhf8_AVX512
}

{
ICLASS:      VCVTHF82PH
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_NE_CONVERT_FP8_512
EXCEPTIONS:  AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  DISP8_HALF FIXED_ROUNDING_RNE FLUSH_OUTPUT_DENORM MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR 
PATTERN:     EVV 0x1E VF2 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() BCRC=0 UBIT=1 W0 VL512 NOEVSR ESIZE_8_BITS() NELEM_HALF()
OPERANDS:    REG0=ZMM_R3():w:zf16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:hf8
IFORM:       VCVTHF82PH_ZMMf16_MASKmskw_MEMhf8_AVX512
}


# EMITTING VCVTNE2PH2BF8 (VCVTNE2PH2BF8-128-1)
{
ICLASS:      VCVTNE2PH2BF8
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_NE_CONVERT_FP8_128
EXCEPTIONS:  AVX512-E4NF
REAL_OPCODE: Y
ATTRIBUTES:  FIXED_ROUNDING_RNE MASKOP_EVEX MXCSR 
PATTERN:     EVV 0x74 VF2 V0F38 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn] W0 VL128
OPERANDS:    REG0=XMM_R3():w:dq:bf8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 REG3=XMM_B3():r:dq:f16
IFORM:       VCVTNE2PH2BF8_XMMbf8_MASKmskw_XMMf16_XMMf16_AVX512
}

{
ICLASS:      VCVTNE2PH2BF8
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_NE_CONVERT_FP8_128
EXCEPTIONS:  AVX512-E4NF
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL FIXED_ROUNDING_RNE MASKOP_EVEX MXCSR 
PATTERN:     EVV 0x74 VF2 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UBIT=1 W0 VL128 ESIZE_16_BITS() NELEM_FULL()
OPERANDS:    REG0=XMM_R3():w:dq:bf8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 MEM0:r:vv:f16:TXT=BCASTSTR
IFORM:       VCVTNE2PH2BF8_XMMbf8_MASKmskw_XMMf16_MEMf16_AVX512
}


# EMITTING VCVTNE2PH2BF8 (VCVTNE2PH2BF8-256-1)
{
ICLASS:      VCVTNE2PH2BF8
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_NE_CONVERT_FP8_256
EXCEPTIONS:  AVX512-E4NF
REAL_OPCODE: Y
ATTRIBUTES:  FIXED_ROUNDING_RNE MASKOP_EVEX MXCSR 
PATTERN:     EVV 0x74 VF2 V0F38 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn] W0 VL256
OPERANDS:    REG0=YMM_R3():w:qq:bf8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f16 REG3=YMM_B3():r:qq:f16
IFORM:       VCVTNE2PH2BF8_YMMbf8_MASKmskw_YMMf16_YMMf16_AVX512
}

{
ICLASS:      VCVTNE2PH2BF8
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_NE_CONVERT_FP8_256
EXCEPTIONS:  AVX512-E4NF
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL FIXED_ROUNDING_RNE MASKOP_EVEX MXCSR 
PATTERN:     EVV 0x74 VF2 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UBIT=1 W0 VL256 ESIZE_16_BITS() NELEM_FULL()
OPERANDS:    REG0=YMM_R3():w:qq:bf8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f16 MEM0:r:vv:f16:TXT=BCASTSTR
IFORM:       VCVTNE2PH2BF8_YMMbf8_MASKmskw_YMMf16_MEMf16_AVX512
}


# EMITTING VCVTNE2PH2BF8 (VCVTNE2PH2BF8-512-1)
{
ICLASS:      VCVTNE2PH2BF8
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_NE_CONVERT_FP8_512
EXCEPTIONS:  AVX512-E4NF
REAL_OPCODE: Y
ATTRIBUTES:  FIXED_ROUNDING_RNE MASKOP_EVEX MXCSR 
PATTERN:     EVV 0x74 VF2 V0F38 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn] W0 VL512
OPERANDS:    REG0=ZMM_R3():w:zbf8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf16 REG3=ZMM_B3():r:zf16
IFORM:       VCVTNE2PH2BF8_ZMMbf8_MASKmskw_ZMMf16_ZMMf16_AVX512
}

{
ICLASS:      VCVTNE2PH2BF8
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_NE_CONVERT_FP8_512
EXCEPTIONS:  AVX512-E4NF
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL FIXED_ROUNDING_RNE MASKOP_EVEX MXCSR 
PATTERN:     EVV 0x74 VF2 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UBIT=1 W0 VL512 ESIZE_16_BITS() NELEM_FULL()
OPERANDS:    REG0=ZMM_R3():w:zbf8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf16 MEM0:r:vv:f16:TXT=BCASTSTR
IFORM:       VCVTNE2PH2BF8_ZMMbf8_MASKmskw_ZMMf16_MEMf16_AVX512
}


# EMITTING VCVTNE2PH2BF8S (VCVTNE2PH2BF8S-128-1)
{
ICLASS:      VCVTNE2PH2BF8S
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_NE_CONVERT_FP8_128
EXCEPTIONS:  AVX512-E4NF
REAL_OPCODE: Y
ATTRIBUTES:  FIXED_ROUNDING_RNE MASKOP_EVEX MXCSR 
PATTERN:     EVV 0x74 VF2 MAP5 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn] W0 VL128
OPERANDS:    REG0=XMM_R3():w:dq:bf8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 REG3=XMM_B3():r:dq:f16
IFORM:       VCVTNE2PH2BF8S_XMMbf8_MASKmskw_XMMf16_XMMf16_AVX512
}

{
ICLASS:      VCVTNE2PH2BF8S
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_NE_CONVERT_FP8_128
EXCEPTIONS:  AVX512-E4NF
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL FIXED_ROUNDING_RNE MASKOP_EVEX MXCSR 
PATTERN:     EVV 0x74 VF2 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UBIT=1 W0 VL128 ESIZE_16_BITS() NELEM_FULL()
OPERANDS:    REG0=XMM_R3():w:dq:bf8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 MEM0:r:vv:f16:TXT=BCASTSTR
IFORM:       VCVTNE2PH2BF8S_XMMbf8_MASKmskw_XMMf16_MEMf16_AVX512
}


# EMITTING VCVTNE2PH2BF8S (VCVTNE2PH2BF8S-256-1)
{
ICLASS:      VCVTNE2PH2BF8S
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_NE_CONVERT_FP8_256
EXCEPTIONS:  AVX512-E4NF
REAL_OPCODE: Y
ATTRIBUTES:  FIXED_ROUNDING_RNE MASKOP_EVEX MXCSR 
PATTERN:     EVV 0x74 VF2 MAP5 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn] W0 VL256
OPERANDS:    REG0=YMM_R3():w:qq:bf8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f16 REG3=YMM_B3():r:qq:f16
IFORM:       VCVTNE2PH2BF8S_YMMbf8_MASKmskw_YMMf16_YMMf16_AVX512
}

{
ICLASS:      VCVTNE2PH2BF8S
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_NE_CONVERT_FP8_256
EXCEPTIONS:  AVX512-E4NF
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL FIXED_ROUNDING_RNE MASKOP_EVEX MXCSR 
PATTERN:     EVV 0x74 VF2 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UBIT=1 W0 VL256 ESIZE_16_BITS() NELEM_FULL()
OPERANDS:    REG0=YMM_R3():w:qq:bf8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f16 MEM0:r:vv:f16:TXT=BCASTSTR
IFORM:       VCVTNE2PH2BF8S_YMMbf8_MASKmskw_YMMf16_MEMf16_AVX512
}


# EMITTING VCVTNE2PH2BF8S (VCVTNE2PH2BF8S-512-1)
{
ICLASS:      VCVTNE2PH2BF8S
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_NE_CONVERT_FP8_512
EXCEPTIONS:  AVX512-E4NF
REAL_OPCODE: Y
ATTRIBUTES:  FIXED_ROUNDING_RNE MASKOP_EVEX MXCSR 
PATTERN:     EVV 0x74 VF2 MAP5 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn] W0 VL512
OPERANDS:    REG0=ZMM_R3():w:zbf8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf16 REG3=ZMM_B3():r:zf16
IFORM:       VCVTNE2PH2BF8S_ZMMbf8_MASKmskw_ZMMf16_ZMMf16_AVX512
}

{
ICLASS:      VCVTNE2PH2BF8S
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_NE_CONVERT_FP8_512
EXCEPTIONS:  AVX512-E4NF
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL FIXED_ROUNDING_RNE MASKOP_EVEX MXCSR 
PATTERN:     EVV 0x74 VF2 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UBIT=1 W0 VL512 ESIZE_16_BITS() NELEM_FULL()
OPERANDS:    REG0=ZMM_R3():w:zbf8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf16 MEM0:r:vv:f16:TXT=BCASTSTR
IFORM:       VCVTNE2PH2BF8S_ZMMbf8_MASKmskw_ZMMf16_MEMf16_AVX512
}


# EMITTING VCVTNE2PH2HF8 (VCVTNE2PH2HF8-128-1)
{
ICLASS:      VCVTNE2PH2HF8
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_NE_CONVERT_FP8_128
EXCEPTIONS:  AVX512-E4NF
REAL_OPCODE: Y
ATTRIBUTES:  FIXED_ROUNDING_RNE MASKOP_EVEX MXCSR 
PATTERN:     EVV 0x18 VF2 MAP5 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn] W0 VL128
OPERANDS:    REG0=XMM_R3():w:dq:hf8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 REG3=XMM_B3():r:dq:f16
IFORM:       VCVTNE2PH2HF8_XMMhf8_MASKmskw_XMMf16_XMMf16_AVX512
}

{
ICLASS:      VCVTNE2PH2HF8
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_NE_CONVERT_FP8_128
EXCEPTIONS:  AVX512-E4NF
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL FIXED_ROUNDING_RNE MASKOP_EVEX MXCSR 
PATTERN:     EVV 0x18 VF2 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UBIT=1 W0 VL128 ESIZE_16_BITS() NELEM_FULL()
OPERANDS:    REG0=XMM_R3():w:dq:hf8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 MEM0:r:vv:f16:TXT=BCASTSTR
IFORM:       VCVTNE2PH2HF8_XMMhf8_MASKmskw_XMMf16_MEMf16_AVX512
}


# EMITTING VCVTNE2PH2HF8 (VCVTNE2PH2HF8-256-1)
{
ICLASS:      VCVTNE2PH2HF8
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_NE_CONVERT_FP8_256
EXCEPTIONS:  AVX512-E4NF
REAL_OPCODE: Y
ATTRIBUTES:  FIXED_ROUNDING_RNE MASKOP_EVEX MXCSR 
PATTERN:     EVV 0x18 VF2 MAP5 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn] W0 VL256
OPERANDS:    REG0=YMM_R3():w:qq:hf8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f16 REG3=YMM_B3():r:qq:f16
IFORM:       VCVTNE2PH2HF8_YMMhf8_MASKmskw_YMMf16_YMMf16_AVX512
}

{
ICLASS:      VCVTNE2PH2HF8
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_NE_CONVERT_FP8_256
EXCEPTIONS:  AVX512-E4NF
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL FIXED_ROUNDING_RNE MASKOP_EVEX MXCSR 
PATTERN:     EVV 0x18 VF2 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UBIT=1 W0 VL256 ESIZE_16_BITS() NELEM_FULL()
OPERANDS:    REG0=YMM_R3():w:qq:hf8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f16 MEM0:r:vv:f16:TXT=BCASTSTR
IFORM:       VCVTNE2PH2HF8_YMMhf8_MASKmskw_YMMf16_MEMf16_AVX512
}


# EMITTING VCVTNE2PH2HF8 (VCVTNE2PH2HF8-512-1)
{
ICLASS:      VCVTNE2PH2HF8
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_NE_CONVERT_FP8_512
EXCEPTIONS:  AVX512-E4NF
REAL_OPCODE: Y
ATTRIBUTES:  FIXED_ROUNDING_RNE MASKOP_EVEX MXCSR 
PATTERN:     EVV 0x18 VF2 MAP5 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn] W0 VL512
OPERANDS:    REG0=ZMM_R3():w:zhf8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf16 REG3=ZMM_B3():r:zf16
IFORM:       VCVTNE2PH2HF8_ZMMhf8_MASKmskw_ZMMf16_ZMMf16_AVX512
}

{
ICLASS:      VCVTNE2PH2HF8
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_NE_CONVERT_FP8_512
EXCEPTIONS:  AVX512-E4NF
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL FIXED_ROUNDING_RNE MASKOP_EVEX MXCSR 
PATTERN:     EVV 0x18 VF2 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UBIT=1 W0 VL512 ESIZE_16_BITS() NELEM_FULL()
OPERANDS:    REG0=ZMM_R3():w:zhf8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf16 MEM0:r:vv:f16:TXT=BCASTSTR
IFORM:       VCVTNE2PH2HF8_ZMMhf8_MASKmskw_ZMMf16_MEMf16_AVX512
}


# EMITTING VCVTNE2PH2HF8S (VCVTNE2PH2HF8S-128-1)
{
ICLASS:      VCVTNE2PH2HF8S
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_NE_CONVERT_FP8_128
EXCEPTIONS:  AVX512-E4NF
REAL_OPCODE: Y
ATTRIBUTES:  FIXED_ROUNDING_RNE MASKOP_EVEX MXCSR 
PATTERN:     EVV 0x1B VF2 MAP5 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn] W0 VL128
OPERANDS:    REG0=XMM_R3():w:dq:hf8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 REG3=XMM_B3():r:dq:f16
IFORM:       VCVTNE2PH2HF8S_XMMhf8_MASKmskw_XMMf16_XMMf16_AVX512
}

{
ICLASS:      VCVTNE2PH2HF8S
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_NE_CONVERT_FP8_128
EXCEPTIONS:  AVX512-E4NF
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL FIXED_ROUNDING_RNE MASKOP_EVEX MXCSR 
PATTERN:     EVV 0x1B VF2 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UBIT=1 W0 VL128 ESIZE_16_BITS() NELEM_FULL()
OPERANDS:    REG0=XMM_R3():w:dq:hf8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 MEM0:r:vv:f16:TXT=BCASTSTR
IFORM:       VCVTNE2PH2HF8S_XMMhf8_MASKmskw_XMMf16_MEMf16_AVX512
}


# EMITTING VCVTNE2PH2HF8S (VCVTNE2PH2HF8S-256-1)
{
ICLASS:      VCVTNE2PH2HF8S
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_NE_CONVERT_FP8_256
EXCEPTIONS:  AVX512-E4NF
REAL_OPCODE: Y
ATTRIBUTES:  FIXED_ROUNDING_RNE MASKOP_EVEX MXCSR 
PATTERN:     EVV 0x1B VF2 MAP5 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn] W0 VL256
OPERANDS:    REG0=YMM_R3():w:qq:hf8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f16 REG3=YMM_B3():r:qq:f16
IFORM:       VCVTNE2PH2HF8S_YMMhf8_MASKmskw_YMMf16_YMMf16_AVX512
}

{
ICLASS:      VCVTNE2PH2HF8S
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_NE_CONVERT_FP8_256
EXCEPTIONS:  AVX512-E4NF
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL FIXED_ROUNDING_RNE MASKOP_EVEX MXCSR 
PATTERN:     EVV 0x1B VF2 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UBIT=1 W0 VL256 ESIZE_16_BITS() NELEM_FULL()
OPERANDS:    REG0=YMM_R3():w:qq:hf8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f16 MEM0:r:vv:f16:TXT=BCASTSTR
IFORM:       VCVTNE2PH2HF8S_YMMhf8_MASKmskw_YMMf16_MEMf16_AVX512
}


# EMITTING VCVTNE2PH2HF8S (VCVTNE2PH2HF8S-512-1)
{
ICLASS:      VCVTNE2PH2HF8S
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_NE_CONVERT_FP8_512
EXCEPTIONS:  AVX512-E4NF
REAL_OPCODE: Y
ATTRIBUTES:  FIXED_ROUNDING_RNE MASKOP_EVEX MXCSR 
PATTERN:     EVV 0x1B VF2 MAP5 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn] W0 VL512
OPERANDS:    REG0=ZMM_R3():w:zhf8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf16 REG3=ZMM_B3():r:zf16
IFORM:       VCVTNE2PH2HF8S_ZMMhf8_MASKmskw_ZMMf16_ZMMf16_AVX512
}

{
ICLASS:      VCVTNE2PH2HF8S
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_NE_CONVERT_FP8_512
EXCEPTIONS:  AVX512-E4NF
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL FIXED_ROUNDING_RNE MASKOP_EVEX MXCSR 
PATTERN:     EVV 0x1B VF2 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UBIT=1 W0 VL512 ESIZE_16_BITS() NELEM_FULL()
OPERANDS:    REG0=ZMM_R3():w:zhf8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf16 MEM0:r:vv:f16:TXT=BCASTSTR
IFORM:       VCVTNE2PH2HF8S_ZMMhf8_MASKmskw_ZMMf16_MEMf16_AVX512
}


# EMITTING VCVTNEBF162IBS (VCVTNEBF162IBS-128-1)
{
ICLASS:      VCVTNEBF162IBS
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_SAT_CVT_128
EXCEPTIONS:  AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  FIXED_ROUNDING_RNE FLUSH_INPUT_DENORM MASKOP_EVEX 
PATTERN:     EVV 0x69 VF2 MAP5 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn] W0 VL128 NOEVSR
OPERANDS:    REG0=XMM_R3():w:dq:i8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:bf16
IFORM:       VCVTNEBF162IBS_XMMi8_MASKmskw_XMMbf16_AVX512
}

{
ICLASS:      VCVTNEBF162IBS
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_SAT_CVT_128
EXCEPTIONS:  AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL FIXED_ROUNDING_RNE FLUSH_INPUT_DENORM MASKOP_EVEX MEMORY_FAULT_SUPPRESSION 
PATTERN:     EVV 0x69 VF2 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UBIT=1 W0 VL128 NOEVSR ESIZE_16_BITS() NELEM_FULL()
OPERANDS:    REG0=XMM_R3():w:dq:i8 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:bf16:TXT=BCASTSTR
IFORM:       VCVTNEBF162IBS_XMMi8_MASKmskw_MEMbf16_AVX512
}


# EMITTING VCVTNEBF162IBS (VCVTNEBF162IBS-256-1)
{
ICLASS:      VCVTNEBF162IBS
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_SAT_CVT_256
EXCEPTIONS:  AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  FIXED_ROUNDING_RNE FLUSH_INPUT_DENORM MASKOP_EVEX 
PATTERN:     EVV 0x69 VF2 MAP5 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn] W0 VL256 NOEVSR
OPERANDS:    REG0=YMM_R3():w:qq:i8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:bf16
IFORM:       VCVTNEBF162IBS_YMMi8_MASKmskw_YMMbf16_AVX512
}

{
ICLASS:      VCVTNEBF162IBS
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_SAT_CVT_256
EXCEPTIONS:  AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL FIXED_ROUNDING_RNE FLUSH_INPUT_DENORM MASKOP_EVEX MEMORY_FAULT_SUPPRESSION 
PATTERN:     EVV 0x69 VF2 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UBIT=1 W0 VL256 NOEVSR ESIZE_16_BITS() NELEM_FULL()
OPERANDS:    REG0=YMM_R3():w:qq:i8 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:bf16:TXT=BCASTSTR
IFORM:       VCVTNEBF162IBS_YMMi8_MASKmskw_MEMbf16_AVX512
}


# EMITTING VCVTNEBF162IBS (VCVTNEBF162IBS-512-1)
{
ICLASS:      VCVTNEBF162IBS
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_SAT_CVT_512
EXCEPTIONS:  AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  FIXED_ROUNDING_RNE FLUSH_INPUT_DENORM MASKOP_EVEX 
PATTERN:     EVV 0x69 VF2 MAP5 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn] W0 VL512 NOEVSR
OPERANDS:    REG0=ZMM_R3():w:zi8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zbf16
IFORM:       VCVTNEBF162IBS_ZMMi8_MASKmskw_ZMMbf16_AVX512
}

{
ICLASS:      VCVTNEBF162IBS
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_SAT_CVT_512
EXCEPTIONS:  AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL FIXED_ROUNDING_RNE FLUSH_INPUT_DENORM MASKOP_EVEX MEMORY_FAULT_SUPPRESSION 
PATTERN:     EVV 0x69 VF2 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UBIT=1 W0 VL512 NOEVSR ESIZE_16_BITS() NELEM_FULL()
OPERANDS:    REG0=ZMM_R3():w:zi8 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:bf16:TXT=BCASTSTR
IFORM:       VCVTNEBF162IBS_ZMMi8_MASKmskw_MEMbf16_AVX512
}


# EMITTING VCVTNEBF162IUBS (VCVTNEBF162IUBS-128-1)
{
ICLASS:      VCVTNEBF162IUBS
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_SAT_CVT_128
EXCEPTIONS:  AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  FIXED_ROUNDING_RNE FLUSH_INPUT_DENORM MASKOP_EVEX 
PATTERN:     EVV 0x6B VF2 MAP5 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn] W0 VL128 NOEVSR
OPERANDS:    REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:bf16
IFORM:       VCVTNEBF162IUBS_XMMu8_MASKmskw_XMMbf16_AVX512
}

{
ICLASS:      VCVTNEBF162IUBS
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_SAT_CVT_128
EXCEPTIONS:  AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL FIXED_ROUNDING_RNE FLUSH_INPUT_DENORM MASKOP_EVEX MEMORY_FAULT_SUPPRESSION 
PATTERN:     EVV 0x6B VF2 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UBIT=1 W0 VL128 NOEVSR ESIZE_16_BITS() NELEM_FULL()
OPERANDS:    REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:bf16:TXT=BCASTSTR
IFORM:       VCVTNEBF162IUBS_XMMu8_MASKmskw_MEMbf16_AVX512
}


# EMITTING VCVTNEBF162IUBS (VCVTNEBF162IUBS-256-1)
{
ICLASS:      VCVTNEBF162IUBS
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_SAT_CVT_256
EXCEPTIONS:  AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  FIXED_ROUNDING_RNE FLUSH_INPUT_DENORM MASKOP_EVEX 
PATTERN:     EVV 0x6B VF2 MAP5 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn] W0 VL256 NOEVSR
OPERANDS:    REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:bf16
IFORM:       VCVTNEBF162IUBS_YMMu8_MASKmskw_YMMbf16_AVX512
}

{
ICLASS:      VCVTNEBF162IUBS
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_SAT_CVT_256
EXCEPTIONS:  AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL FIXED_ROUNDING_RNE FLUSH_INPUT_DENORM MASKOP_EVEX MEMORY_FAULT_SUPPRESSION 
PATTERN:     EVV 0x6B VF2 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UBIT=1 W0 VL256 NOEVSR ESIZE_16_BITS() NELEM_FULL()
OPERANDS:    REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:bf16:TXT=BCASTSTR
IFORM:       VCVTNEBF162IUBS_YMMu8_MASKmskw_MEMbf16_AVX512
}


# EMITTING VCVTNEBF162IUBS (VCVTNEBF162IUBS-512-1)
{
ICLASS:      VCVTNEBF162IUBS
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_SAT_CVT_512
EXCEPTIONS:  AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  FIXED_ROUNDING_RNE FLUSH_INPUT_DENORM MASKOP_EVEX 
PATTERN:     EVV 0x6B VF2 MAP5 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn] W0 VL512 NOEVSR
OPERANDS:    REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zbf16
IFORM:       VCVTNEBF162IUBS_ZMMu8_MASKmskw_ZMMbf16_AVX512
}

{
ICLASS:      VCVTNEBF162IUBS
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_SAT_CVT_512
EXCEPTIONS:  AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL FIXED_ROUNDING_RNE FLUSH_INPUT_DENORM MASKOP_EVEX MEMORY_FAULT_SUPPRESSION 
PATTERN:     EVV 0x6B VF2 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UBIT=1 W0 VL512 NOEVSR ESIZE_16_BITS() NELEM_FULL()
OPERANDS:    REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:bf16:TXT=BCASTSTR
IFORM:       VCVTNEBF162IUBS_ZMMu8_MASKmskw_MEMbf16_AVX512
}


# EMITTING VCVTNEPH2BF8 (VCVTNEPH2BF8-128-1)
{
ICLASS:      VCVTNEPH2BF8
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_NE_CONVERT_FP8_128
EXCEPTIONS:  AVX512-E4NF
REAL_OPCODE: Y
ATTRIBUTES:  FIXED_ROUNDING_RNE MASKOP_EVEX MXCSR 
PATTERN:     EVV 0x74 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn] W0 VL128 NOEVSR
OPERANDS:    REG0=XMM_R3():w:dq:bf8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f16
IFORM:       VCVTNEPH2BF8_XMMbf8_MASKmskw_XMMf16_AVX512
}

{
ICLASS:      VCVTNEPH2BF8
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_NE_CONVERT_FP8_128
EXCEPTIONS:  AVX512-E4NF
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL FIXED_ROUNDING_RNE MASKOP_EVEX MXCSR 
PATTERN:     EVV 0x74 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UBIT=1 W0 VL128 NOEVSR ESIZE_16_BITS() NELEM_FULL()
OPERANDS:    REG0=XMM_R3():w:dq:bf8 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f16:TXT=BCASTSTR
IFORM:       VCVTNEPH2BF8_XMMbf8_MASKmskw_MEMf16_AVX512_VL128
}


# EMITTING VCVTNEPH2BF8 (VCVTNEPH2BF8-256-1)
{
ICLASS:      VCVTNEPH2BF8
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_NE_CONVERT_FP8_256
EXCEPTIONS:  AVX512-E4NF
REAL_OPCODE: Y
ATTRIBUTES:  FIXED_ROUNDING_RNE MASKOP_EVEX MXCSR 
PATTERN:     EVV 0x74 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn] W0 VL256 NOEVSR
OPERANDS:    REG0=XMM_R3():w:dq:bf8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f16
IFORM:       VCVTNEPH2BF8_XMMbf8_MASKmskw_YMMf16_AVX512
}

{
ICLASS:      VCVTNEPH2BF8
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_NE_CONVERT_FP8_256
EXCEPTIONS:  AVX512-E4NF
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL FIXED_ROUNDING_RNE MASKOP_EVEX MXCSR 
PATTERN:     EVV 0x74 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UBIT=1 W0 VL256 NOEVSR ESIZE_16_BITS() NELEM_FULL()
OPERANDS:    REG0=XMM_R3():w:dq:bf8 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f16:TXT=BCASTSTR
IFORM:       VCVTNEPH2BF8_XMMbf8_MASKmskw_MEMf16_AVX512_VL256
}


# EMITTING VCVTNEPH2BF8 (VCVTNEPH2BF8-512-1)
{
ICLASS:      VCVTNEPH2BF8
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_NE_CONVERT_FP8_512
EXCEPTIONS:  AVX512-E4NF
REAL_OPCODE: Y
ATTRIBUTES:  FIXED_ROUNDING_RNE MASKOP_EVEX MXCSR 
PATTERN:     EVV 0x74 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn] W0 VL512 NOEVSR
OPERANDS:    REG0=YMM_R3():w:qq:bf8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf16
IFORM:       VCVTNEPH2BF8_YMMbf8_MASKmskw_ZMMf16_AVX512
}

{
ICLASS:      VCVTNEPH2BF8
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_NE_CONVERT_FP8_512
EXCEPTIONS:  AVX512-E4NF
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL FIXED_ROUNDING_RNE MASKOP_EVEX MXCSR 
PATTERN:     EVV 0x74 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UBIT=1 W0 VL512 NOEVSR ESIZE_16_BITS() NELEM_FULL()
OPERANDS:    REG0=YMM_R3():w:qq:bf8 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f16:TXT=BCASTSTR
IFORM:       VCVTNEPH2BF8_YMMbf8_MASKmskw_MEMf16_AVX512_VL512
}


# EMITTING VCVTNEPH2BF8S (VCVTNEPH2BF8S-128-1)
{
ICLASS:      VCVTNEPH2BF8S
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_NE_CONVERT_FP8_128
EXCEPTIONS:  AVX512-E4NF
REAL_OPCODE: Y
ATTRIBUTES:  FIXED_ROUNDING_RNE MASKOP_EVEX MXCSR 
PATTERN:     EVV 0x74 VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn] W0 VL128 NOEVSR
OPERANDS:    REG0=XMM_R3():w:dq:bf8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f16
IFORM:       VCVTNEPH2BF8S_XMMbf8_MASKmskw_XMMf16_AVX512
}

{
ICLASS:      VCVTNEPH2BF8S
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_NE_CONVERT_FP8_128
EXCEPTIONS:  AVX512-E4NF
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL FIXED_ROUNDING_RNE MASKOP_EVEX MXCSR 
PATTERN:     EVV 0x74 VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UBIT=1 W0 VL128 NOEVSR ESIZE_16_BITS() NELEM_FULL()
OPERANDS:    REG0=XMM_R3():w:dq:bf8 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f16:TXT=BCASTSTR
IFORM:       VCVTNEPH2BF8S_XMMbf8_MASKmskw_MEMf16_AVX512_VL128
}


# EMITTING VCVTNEPH2BF8S (VCVTNEPH2BF8S-256-1)
{
ICLASS:      VCVTNEPH2BF8S
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_NE_CONVERT_FP8_256
EXCEPTIONS:  AVX512-E4NF
REAL_OPCODE: Y
ATTRIBUTES:  FIXED_ROUNDING_RNE MASKOP_EVEX MXCSR 
PATTERN:     EVV 0x74 VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn] W0 VL256 NOEVSR
OPERANDS:    REG0=XMM_R3():w:dq:bf8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f16
IFORM:       VCVTNEPH2BF8S_XMMbf8_MASKmskw_YMMf16_AVX512
}

{
ICLASS:      VCVTNEPH2BF8S
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_NE_CONVERT_FP8_256
EXCEPTIONS:  AVX512-E4NF
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL FIXED_ROUNDING_RNE MASKOP_EVEX MXCSR 
PATTERN:     EVV 0x74 VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UBIT=1 W0 VL256 NOEVSR ESIZE_16_BITS() NELEM_FULL()
OPERANDS:    REG0=XMM_R3():w:dq:bf8 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f16:TXT=BCASTSTR
IFORM:       VCVTNEPH2BF8S_XMMbf8_MASKmskw_MEMf16_AVX512_VL256
}


# EMITTING VCVTNEPH2BF8S (VCVTNEPH2BF8S-512-1)
{
ICLASS:      VCVTNEPH2BF8S
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_NE_CONVERT_FP8_512
EXCEPTIONS:  AVX512-E4NF
REAL_OPCODE: Y
ATTRIBUTES:  FIXED_ROUNDING_RNE MASKOP_EVEX MXCSR 
PATTERN:     EVV 0x74 VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn] W0 VL512 NOEVSR
OPERANDS:    REG0=YMM_R3():w:qq:bf8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf16
IFORM:       VCVTNEPH2BF8S_YMMbf8_MASKmskw_ZMMf16_AVX512
}

{
ICLASS:      VCVTNEPH2BF8S
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_NE_CONVERT_FP8_512
EXCEPTIONS:  AVX512-E4NF
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL FIXED_ROUNDING_RNE MASKOP_EVEX MXCSR 
PATTERN:     EVV 0x74 VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UBIT=1 W0 VL512 NOEVSR ESIZE_16_BITS() NELEM_FULL()
OPERANDS:    REG0=YMM_R3():w:qq:bf8 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f16:TXT=BCASTSTR
IFORM:       VCVTNEPH2BF8S_YMMbf8_MASKmskw_MEMf16_AVX512_VL512
}


# EMITTING VCVTNEPH2HF8 (VCVTNEPH2HF8-128-1)
{
ICLASS:      VCVTNEPH2HF8
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_NE_CONVERT_FP8_128
EXCEPTIONS:  AVX512-E4NF
REAL_OPCODE: Y
ATTRIBUTES:  FIXED_ROUNDING_RNE MASKOP_EVEX MXCSR 
PATTERN:     EVV 0x18 VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn] W0 VL128 NOEVSR
OPERANDS:    REG0=XMM_R3():w:dq:hf8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f16
IFORM:       VCVTNEPH2HF8_XMMhf8_MASKmskw_XMMf16_AVX512
}

{
ICLASS:      VCVTNEPH2HF8
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_NE_CONVERT_FP8_128
EXCEPTIONS:  AVX512-E4NF
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL FIXED_ROUNDING_RNE MASKOP_EVEX MXCSR 
PATTERN:     EVV 0x18 VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UBIT=1 W0 VL128 NOEVSR ESIZE_16_BITS() NELEM_FULL()
OPERANDS:    REG0=XMM_R3():w:dq:hf8 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f16:TXT=BCASTSTR
IFORM:       VCVTNEPH2HF8_XMMhf8_MASKmskw_MEMf16_AVX512_VL128
}


# EMITTING VCVTNEPH2HF8 (VCVTNEPH2HF8-256-1)
{
ICLASS:      VCVTNEPH2HF8
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_NE_CONVERT_FP8_256
EXCEPTIONS:  AVX512-E4NF
REAL_OPCODE: Y
ATTRIBUTES:  FIXED_ROUNDING_RNE MASKOP_EVEX MXCSR 
PATTERN:     EVV 0x18 VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn] W0 VL256 NOEVSR
OPERANDS:    REG0=XMM_R3():w:dq:hf8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f16
IFORM:       VCVTNEPH2HF8_XMMhf8_MASKmskw_YMMf16_AVX512
}

{
ICLASS:      VCVTNEPH2HF8
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_NE_CONVERT_FP8_256
EXCEPTIONS:  AVX512-E4NF
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL FIXED_ROUNDING_RNE MASKOP_EVEX MXCSR 
PATTERN:     EVV 0x18 VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UBIT=1 W0 VL256 NOEVSR ESIZE_16_BITS() NELEM_FULL()
OPERANDS:    REG0=XMM_R3():w:dq:hf8 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f16:TXT=BCASTSTR
IFORM:       VCVTNEPH2HF8_XMMhf8_MASKmskw_MEMf16_AVX512_VL256
}


# EMITTING VCVTNEPH2HF8 (VCVTNEPH2HF8-512-1)
{
ICLASS:      VCVTNEPH2HF8
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_NE_CONVERT_FP8_512
EXCEPTIONS:  AVX512-E4NF
REAL_OPCODE: Y
ATTRIBUTES:  FIXED_ROUNDING_RNE MASKOP_EVEX MXCSR 
PATTERN:     EVV 0x18 VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn] W0 VL512 NOEVSR
OPERANDS:    REG0=YMM_R3():w:qq:hf8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf16
IFORM:       VCVTNEPH2HF8_YMMhf8_MASKmskw_ZMMf16_AVX512
}

{
ICLASS:      VCVTNEPH2HF8
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_NE_CONVERT_FP8_512
EXCEPTIONS:  AVX512-E4NF
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL FIXED_ROUNDING_RNE MASKOP_EVEX MXCSR 
PATTERN:     EVV 0x18 VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UBIT=1 W0 VL512 NOEVSR ESIZE_16_BITS() NELEM_FULL()
OPERANDS:    REG0=YMM_R3():w:qq:hf8 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f16:TXT=BCASTSTR
IFORM:       VCVTNEPH2HF8_YMMhf8_MASKmskw_MEMf16_AVX512_VL512
}


# EMITTING VCVTNEPH2HF8S (VCVTNEPH2HF8S-128-1)
{
ICLASS:      VCVTNEPH2HF8S
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_NE_CONVERT_FP8_128
EXCEPTIONS:  AVX512-E4NF
REAL_OPCODE: Y
ATTRIBUTES:  FIXED_ROUNDING_RNE MASKOP_EVEX MXCSR 
PATTERN:     EVV 0x1B VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn] W0 VL128 NOEVSR
OPERANDS:    REG0=XMM_R3():w:dq:hf8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f16
IFORM:       VCVTNEPH2HF8S_XMMhf8_MASKmskw_XMMf16_AVX512
}

{
ICLASS:      VCVTNEPH2HF8S
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_NE_CONVERT_FP8_128
EXCEPTIONS:  AVX512-E4NF
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL FIXED_ROUNDING_RNE MASKOP_EVEX MXCSR 
PATTERN:     EVV 0x1B VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UBIT=1 W0 VL128 NOEVSR ESIZE_16_BITS() NELEM_FULL()
OPERANDS:    REG0=XMM_R3():w:dq:hf8 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f16:TXT=BCASTSTR
IFORM:       VCVTNEPH2HF8S_XMMhf8_MASKmskw_MEMf16_AVX512_VL128
}


# EMITTING VCVTNEPH2HF8S (VCVTNEPH2HF8S-256-1)
{
ICLASS:      VCVTNEPH2HF8S
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_NE_CONVERT_FP8_256
EXCEPTIONS:  AVX512-E4NF
REAL_OPCODE: Y
ATTRIBUTES:  FIXED_ROUNDING_RNE MASKOP_EVEX MXCSR 
PATTERN:     EVV 0x1B VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn] W0 VL256 NOEVSR
OPERANDS:    REG0=XMM_R3():w:dq:hf8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f16
IFORM:       VCVTNEPH2HF8S_XMMhf8_MASKmskw_YMMf16_AVX512
}

{
ICLASS:      VCVTNEPH2HF8S
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_NE_CONVERT_FP8_256
EXCEPTIONS:  AVX512-E4NF
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL FIXED_ROUNDING_RNE MASKOP_EVEX MXCSR 
PATTERN:     EVV 0x1B VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UBIT=1 W0 VL256 NOEVSR ESIZE_16_BITS() NELEM_FULL()
OPERANDS:    REG0=XMM_R3():w:dq:hf8 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f16:TXT=BCASTSTR
IFORM:       VCVTNEPH2HF8S_XMMhf8_MASKmskw_MEMf16_AVX512_VL256
}


# EMITTING VCVTNEPH2HF8S (VCVTNEPH2HF8S-512-1)
{
ICLASS:      VCVTNEPH2HF8S
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_NE_CONVERT_FP8_512
EXCEPTIONS:  AVX512-E4NF
REAL_OPCODE: Y
ATTRIBUTES:  FIXED_ROUNDING_RNE MASKOP_EVEX MXCSR 
PATTERN:     EVV 0x1B VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn] W0 VL512 NOEVSR
OPERANDS:    REG0=YMM_R3():w:qq:hf8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf16
IFORM:       VCVTNEPH2HF8S_YMMhf8_MASKmskw_ZMMf16_AVX512
}

{
ICLASS:      VCVTNEPH2HF8S
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_NE_CONVERT_FP8_512
EXCEPTIONS:  AVX512-E4NF
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL FIXED_ROUNDING_RNE MASKOP_EVEX MXCSR 
PATTERN:     EVV 0x1B VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UBIT=1 W0 VL512 NOEVSR ESIZE_16_BITS() NELEM_FULL()
OPERANDS:    REG0=YMM_R3():w:qq:hf8 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f16:TXT=BCASTSTR
IFORM:       VCVTNEPH2HF8S_YMMhf8_MASKmskw_MEMf16_AVX512_VL512
}


# EMITTING VCVTPH2IBS (VCVTPH2IBS-128-1)
{
ICLASS:      VCVTPH2IBS
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_SAT_CVT_128
EXCEPTIONS:  AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR 
PATTERN:     EVV 0x69 VNP MAP5 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn] W0 VL128 NOEVSR
OPERANDS:    REG0=XMM_R3():w:dq:i8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f16
IFORM:       VCVTPH2IBS_XMMi8_MASKmskw_XMMf16_AVX512
}

{
ICLASS:      VCVTPH2IBS
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_SAT_CVT_128
EXCEPTIONS:  AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR 
PATTERN:     EVV 0x69 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UBIT=1 W0 VL128 NOEVSR ESIZE_16_BITS() NELEM_FULL()
OPERANDS:    REG0=XMM_R3():w:dq:i8 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f16:TXT=BCASTSTR
IFORM:       VCVTPH2IBS_XMMi8_MASKmskw_MEMf16_AVX512
}


# EMITTING VCVTPH2IBS (VCVTPH2IBS-256-1)
{
ICLASS:      VCVTPH2IBS
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_SAT_CVT_256
EXCEPTIONS:  AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR 
PATTERN:     EVV 0x69 VNP MAP5 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn] W0 VL256 NOEVSR
OPERANDS:    REG0=YMM_R3():w:qq:i8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f16
IFORM:       VCVTPH2IBS_YMMi8_MASKmskw_YMMf16_AVX512
}

{
ICLASS:      VCVTPH2IBS
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_SAT_CVT_256
EXCEPTIONS:  AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR 
PATTERN:     EVV 0x69 VNP MAP5 MOD[0b11] MOD=3 BCRC=1 UBIT=0 REG[rrr] RM[nnn] W0 FIX_ROUND_LEN256() AVX256_ROUND() NOEVSR
OPERANDS:    REG0=YMM_R3():w:qq:i8:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f16
IFORM:       VCVTPH2IBS_YMMi8_MASKmskw_YMMf16_AVX512
}

{
ICLASS:      VCVTPH2IBS
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_SAT_CVT_256
EXCEPTIONS:  AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR 
PATTERN:     EVV 0x69 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UBIT=1 W0 VL256 NOEVSR ESIZE_16_BITS() NELEM_FULL()
OPERANDS:    REG0=YMM_R3():w:qq:i8 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f16:TXT=BCASTSTR
IFORM:       VCVTPH2IBS_YMMi8_MASKmskw_MEMf16_AVX512
}


# EMITTING VCVTPH2IBS (VCVTPH2IBS-512-1)
{
ICLASS:      VCVTPH2IBS
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_SAT_CVT_512
EXCEPTIONS:  AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR 
PATTERN:     EVV 0x69 VNP MAP5 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn] W0 VL512 NOEVSR
OPERANDS:    REG0=ZMM_R3():w:zi8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf16
IFORM:       VCVTPH2IBS_ZMMi8_MASKmskw_ZMMf16_AVX512
}

{
ICLASS:      VCVTPH2IBS
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_SAT_CVT_512
EXCEPTIONS:  AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR 
PATTERN:     EVV 0x69 VNP MAP5 MOD[0b11] MOD=3 BCRC=1 UBIT=1 REG[rrr] RM[nnn] W0 FIX_ROUND_LEN512() AVX512_ROUND() NOEVSR
OPERANDS:    REG0=ZMM_R3():w:zi8:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf16
IFORM:       VCVTPH2IBS_ZMMi8_MASKmskw_ZMMf16_AVX512
}

{
ICLASS:      VCVTPH2IBS
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_SAT_CVT_512
EXCEPTIONS:  AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR 
PATTERN:     EVV 0x69 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UBIT=1 W0 VL512 NOEVSR ESIZE_16_BITS() NELEM_FULL()
OPERANDS:    REG0=ZMM_R3():w:zi8 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f16:TXT=BCASTSTR
IFORM:       VCVTPH2IBS_ZMMi8_MASKmskw_MEMf16_AVX512
}


# EMITTING VCVTPH2IUBS (VCVTPH2IUBS-128-1)
{
ICLASS:      VCVTPH2IUBS
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_SAT_CVT_128
EXCEPTIONS:  AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR 
PATTERN:     EVV 0x6B VNP MAP5 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn] W0 VL128 NOEVSR
OPERANDS:    REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f16
IFORM:       VCVTPH2IUBS_XMMu8_MASKmskw_XMMf16_AVX512
}

{
ICLASS:      VCVTPH2IUBS
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_SAT_CVT_128
EXCEPTIONS:  AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR 
PATTERN:     EVV 0x6B VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UBIT=1 W0 VL128 NOEVSR ESIZE_16_BITS() NELEM_FULL()
OPERANDS:    REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f16:TXT=BCASTSTR
IFORM:       VCVTPH2IUBS_XMMu8_MASKmskw_MEMf16_AVX512
}


# EMITTING VCVTPH2IUBS (VCVTPH2IUBS-256-1)
{
ICLASS:      VCVTPH2IUBS
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_SAT_CVT_256
EXCEPTIONS:  AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR 
PATTERN:     EVV 0x6B VNP MAP5 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn] W0 VL256 NOEVSR
OPERANDS:    REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f16
IFORM:       VCVTPH2IUBS_YMMu8_MASKmskw_YMMf16_AVX512
}

{
ICLASS:      VCVTPH2IUBS
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_SAT_CVT_256
EXCEPTIONS:  AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR 
PATTERN:     EVV 0x6B VNP MAP5 MOD[0b11] MOD=3 BCRC=1 UBIT=0 REG[rrr] RM[nnn] W0 FIX_ROUND_LEN256() AVX256_ROUND() NOEVSR
OPERANDS:    REG0=YMM_R3():w:qq:u8:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f16
IFORM:       VCVTPH2IUBS_YMMu8_MASKmskw_YMMf16_AVX512
}

{
ICLASS:      VCVTPH2IUBS
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_SAT_CVT_256
EXCEPTIONS:  AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR 
PATTERN:     EVV 0x6B VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UBIT=1 W0 VL256 NOEVSR ESIZE_16_BITS() NELEM_FULL()
OPERANDS:    REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f16:TXT=BCASTSTR
IFORM:       VCVTPH2IUBS_YMMu8_MASKmskw_MEMf16_AVX512
}


# EMITTING VCVTPH2IUBS (VCVTPH2IUBS-512-1)
{
ICLASS:      VCVTPH2IUBS
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_SAT_CVT_512
EXCEPTIONS:  AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR 
PATTERN:     EVV 0x6B VNP MAP5 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn] W0 VL512 NOEVSR
OPERANDS:    REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf16
IFORM:       VCVTPH2IUBS_ZMMu8_MASKmskw_ZMMf16_AVX512
}

{
ICLASS:      VCVTPH2IUBS
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_SAT_CVT_512
EXCEPTIONS:  AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR 
PATTERN:     EVV 0x6B VNP MAP5 MOD[0b11] MOD=3 BCRC=1 UBIT=1 REG[rrr] RM[nnn] W0 FIX_ROUND_LEN512() AVX512_ROUND() NOEVSR
OPERANDS:    REG0=ZMM_R3():w:zu8:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf16
IFORM:       VCVTPH2IUBS_ZMMu8_MASKmskw_ZMMf16_AVX512
}

{
ICLASS:      VCVTPH2IUBS
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_SAT_CVT_512
EXCEPTIONS:  AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR 
PATTERN:     EVV 0x6B VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UBIT=1 W0 VL512 NOEVSR ESIZE_16_BITS() NELEM_FULL()
OPERANDS:    REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f16:TXT=BCASTSTR
IFORM:       VCVTPH2IUBS_ZMMu8_MASKmskw_MEMf16_AVX512
}


# EMITTING VCVTPS2IBS (VCVTPS2IBS-128-1)
{
ICLASS:      VCVTPS2IBS
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_SAT_CVT_128
EXCEPTIONS:  AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR USES_DAZ 
PATTERN:     EVV 0x69 V66 MAP5 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn] W0 VL128 NOEVSR
OPERANDS:    REG0=XMM_R3():w:dq:i8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f32
IFORM:       VCVTPS2IBS_XMMi8_MASKmskw_XMMf32_AVX512
}

{
ICLASS:      VCVTPS2IBS
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_SAT_CVT_128
EXCEPTIONS:  AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR USES_DAZ 
PATTERN:     EVV 0x69 V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UBIT=1 W0 VL128 NOEVSR ESIZE_32_BITS() NELEM_FULL()
OPERANDS:    REG0=XMM_R3():w:dq:i8 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR
IFORM:       VCVTPS2IBS_XMMi8_MASKmskw_MEMf32_AVX512
}


# EMITTING VCVTPS2IBS (VCVTPS2IBS-256-1)
{
ICLASS:      VCVTPS2IBS
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_SAT_CVT_256
EXCEPTIONS:  AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR USES_DAZ 
PATTERN:     EVV 0x69 V66 MAP5 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn] W0 VL256 NOEVSR
OPERANDS:    REG0=YMM_R3():w:qq:i8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f32
IFORM:       VCVTPS2IBS_YMMi8_MASKmskw_YMMf32_AVX512
}

{
ICLASS:      VCVTPS2IBS
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_SAT_CVT_256
EXCEPTIONS:  AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR USES_DAZ 
PATTERN:     EVV 0x69 V66 MAP5 MOD[0b11] MOD=3 BCRC=1 UBIT=0 REG[rrr] RM[nnn] W0 FIX_ROUND_LEN256() AVX256_ROUND() NOEVSR
OPERANDS:    REG0=YMM_R3():w:qq:i8:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f32
IFORM:       VCVTPS2IBS_YMMi8_MASKmskw_YMMf32_AVX512
}

{
ICLASS:      VCVTPS2IBS
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_SAT_CVT_256
EXCEPTIONS:  AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR USES_DAZ 
PATTERN:     EVV 0x69 V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UBIT=1 W0 VL256 NOEVSR ESIZE_32_BITS() NELEM_FULL()
OPERANDS:    REG0=YMM_R3():w:qq:i8 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR
IFORM:       VCVTPS2IBS_YMMi8_MASKmskw_MEMf32_AVX512
}


# EMITTING VCVTPS2IBS (VCVTPS2IBS-512-1)
{
ICLASS:      VCVTPS2IBS
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_SAT_CVT_512
EXCEPTIONS:  AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR USES_DAZ 
PATTERN:     EVV 0x69 V66 MAP5 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn] W0 VL512 NOEVSR
OPERANDS:    REG0=ZMM_R3():w:zi8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf32
IFORM:       VCVTPS2IBS_ZMMi8_MASKmskw_ZMMf32_AVX512
}

{
ICLASS:      VCVTPS2IBS
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_SAT_CVT_512
EXCEPTIONS:  AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR USES_DAZ 
PATTERN:     EVV 0x69 V66 MAP5 MOD[0b11] MOD=3 BCRC=1 UBIT=1 REG[rrr] RM[nnn] W0 FIX_ROUND_LEN512() AVX512_ROUND() NOEVSR
OPERANDS:    REG0=ZMM_R3():w:zi8:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf32
IFORM:       VCVTPS2IBS_ZMMi8_MASKmskw_ZMMf32_AVX512
}

{
ICLASS:      VCVTPS2IBS
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_SAT_CVT_512
EXCEPTIONS:  AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR USES_DAZ 
PATTERN:     EVV 0x69 V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UBIT=1 W0 VL512 NOEVSR ESIZE_32_BITS() NELEM_FULL()
OPERANDS:    REG0=ZMM_R3():w:zi8 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR
IFORM:       VCVTPS2IBS_ZMMi8_MASKmskw_MEMf32_AVX512
}


# EMITTING VCVTPS2IUBS (VCVTPS2IUBS-128-1)
{
ICLASS:      VCVTPS2IUBS
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_SAT_CVT_128
EXCEPTIONS:  AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR USES_DAZ 
PATTERN:     EVV 0x6B V66 MAP5 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn] W0 VL128 NOEVSR
OPERANDS:    REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f32
IFORM:       VCVTPS2IUBS_XMMu8_MASKmskw_XMMf32_AVX512
}

{
ICLASS:      VCVTPS2IUBS
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_SAT_CVT_128
EXCEPTIONS:  AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR USES_DAZ 
PATTERN:     EVV 0x6B V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UBIT=1 W0 VL128 NOEVSR ESIZE_32_BITS() NELEM_FULL()
OPERANDS:    REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR
IFORM:       VCVTPS2IUBS_XMMu8_MASKmskw_MEMf32_AVX512
}


# EMITTING VCVTPS2IUBS (VCVTPS2IUBS-256-1)
{
ICLASS:      VCVTPS2IUBS
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_SAT_CVT_256
EXCEPTIONS:  AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR USES_DAZ 
PATTERN:     EVV 0x6B V66 MAP5 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn] W0 VL256 NOEVSR
OPERANDS:    REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f32
IFORM:       VCVTPS2IUBS_YMMu8_MASKmskw_YMMf32_AVX512
}

{
ICLASS:      VCVTPS2IUBS
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_SAT_CVT_256
EXCEPTIONS:  AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR USES_DAZ 
PATTERN:     EVV 0x6B V66 MAP5 MOD[0b11] MOD=3 BCRC=1 UBIT=0 REG[rrr] RM[nnn] W0 FIX_ROUND_LEN256() AVX256_ROUND() NOEVSR
OPERANDS:    REG0=YMM_R3():w:qq:u8:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f32
IFORM:       VCVTPS2IUBS_YMMu8_MASKmskw_YMMf32_AVX512
}

{
ICLASS:      VCVTPS2IUBS
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_SAT_CVT_256
EXCEPTIONS:  AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR USES_DAZ 
PATTERN:     EVV 0x6B V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UBIT=1 W0 VL256 NOEVSR ESIZE_32_BITS() NELEM_FULL()
OPERANDS:    REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR
IFORM:       VCVTPS2IUBS_YMMu8_MASKmskw_MEMf32_AVX512
}


# EMITTING VCVTPS2IUBS (VCVTPS2IUBS-512-1)
{
ICLASS:      VCVTPS2IUBS
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_SAT_CVT_512
EXCEPTIONS:  AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR USES_DAZ 
PATTERN:     EVV 0x6B V66 MAP5 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn] W0 VL512 NOEVSR
OPERANDS:    REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf32
IFORM:       VCVTPS2IUBS_ZMMu8_MASKmskw_ZMMf32_AVX512
}

{
ICLASS:      VCVTPS2IUBS
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_SAT_CVT_512
EXCEPTIONS:  AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR USES_DAZ 
PATTERN:     EVV 0x6B V66 MAP5 MOD[0b11] MOD=3 BCRC=1 UBIT=1 REG[rrr] RM[nnn] W0 FIX_ROUND_LEN512() AVX512_ROUND() NOEVSR
OPERANDS:    REG0=ZMM_R3():w:zu8:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf32
IFORM:       VCVTPS2IUBS_ZMMu8_MASKmskw_ZMMf32_AVX512
}

{
ICLASS:      VCVTPS2IUBS
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_SAT_CVT_512
EXCEPTIONS:  AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR USES_DAZ 
PATTERN:     EVV 0x6B V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UBIT=1 W0 VL512 NOEVSR ESIZE_32_BITS() NELEM_FULL()
OPERANDS:    REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR
IFORM:       VCVTPS2IUBS_ZMMu8_MASKmskw_MEMf32_AVX512
}


# EMITTING VCVTTNEBF162IBS (VCVTTNEBF162IBS-128-1)
{
ICLASS:      VCVTTNEBF162IBS
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_SAT_CVT_128
EXCEPTIONS:  AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  FLUSH_INPUT_DENORM MASKOP_EVEX 
PATTERN:     EVV 0x68 VF2 MAP5 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn] W0 VL128 NOEVSR
OPERANDS:    REG0=XMM_R3():w:dq:i8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:bf16
IFORM:       VCVTTNEBF162IBS_XMMi8_MASKmskw_XMMbf16_AVX512
}

{
ICLASS:      VCVTTNEBF162IBS
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_SAT_CVT_128
EXCEPTIONS:  AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL FLUSH_INPUT_DENORM MASKOP_EVEX MEMORY_FAULT_SUPPRESSION 
PATTERN:     EVV 0x68 VF2 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UBIT=1 W0 VL128 NOEVSR ESIZE_16_BITS() NELEM_FULL()
OPERANDS:    REG0=XMM_R3():w:dq:i8 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:bf16:TXT=BCASTSTR
IFORM:       VCVTTNEBF162IBS_XMMi8_MASKmskw_MEMbf16_AVX512
}


# EMITTING VCVTTNEBF162IBS (VCVTTNEBF162IBS-256-1)
{
ICLASS:      VCVTTNEBF162IBS
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_SAT_CVT_256
EXCEPTIONS:  AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  FLUSH_INPUT_DENORM MASKOP_EVEX 
PATTERN:     EVV 0x68 VF2 MAP5 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn] W0 VL256 NOEVSR
OPERANDS:    REG0=YMM_R3():w:qq:i8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:bf16
IFORM:       VCVTTNEBF162IBS_YMMi8_MASKmskw_YMMbf16_AVX512
}

{
ICLASS:      VCVTTNEBF162IBS
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_SAT_CVT_256
EXCEPTIONS:  AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  FLUSH_INPUT_DENORM MASKOP_EVEX 
PATTERN:     EVV 0x68 VF2 MAP5 MOD[0b11] MOD=3 BCRC=1 UBIT=0 REG[rrr] RM[nnn] W0 FIX_ROUND_LEN256() NOEVSR
OPERANDS:    REG0=YMM_R3():w:qq:i8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:bf16
IFORM:       VCVTTNEBF162IBS_YMMi8_MASKmskw_YMMbf16_AVX512
}

{
ICLASS:      VCVTTNEBF162IBS
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_SAT_CVT_256
EXCEPTIONS:  AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL FLUSH_INPUT_DENORM MASKOP_EVEX MEMORY_FAULT_SUPPRESSION 
PATTERN:     EVV 0x68 VF2 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UBIT=1 W0 VL256 NOEVSR ESIZE_16_BITS() NELEM_FULL()
OPERANDS:    REG0=YMM_R3():w:qq:i8 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:bf16:TXT=BCASTSTR
IFORM:       VCVTTNEBF162IBS_YMMi8_MASKmskw_MEMbf16_AVX512
}


# EMITTING VCVTTNEBF162IBS (VCVTTNEBF162IBS-512-1)
{
ICLASS:      VCVTTNEBF162IBS
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_SAT_CVT_512
EXCEPTIONS:  AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  FLUSH_INPUT_DENORM MASKOP_EVEX 
PATTERN:     EVV 0x68 VF2 MAP5 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn] W0 VL512 NOEVSR
OPERANDS:    REG0=ZMM_R3():w:zi8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zbf16
IFORM:       VCVTTNEBF162IBS_ZMMi8_MASKmskw_ZMMbf16_AVX512
}

{
ICLASS:      VCVTTNEBF162IBS
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_SAT_CVT_512
EXCEPTIONS:  AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  FLUSH_INPUT_DENORM MASKOP_EVEX 
PATTERN:     EVV 0x68 VF2 MAP5 MOD[0b11] MOD=3 BCRC=1 UBIT=1 REG[rrr] RM[nnn] W0 FIX_ROUND_LEN512() NOEVSR
OPERANDS:    REG0=ZMM_R3():w:zi8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zbf16
IFORM:       VCVTTNEBF162IBS_ZMMi8_MASKmskw_ZMMbf16_AVX512
}

{
ICLASS:      VCVTTNEBF162IBS
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_SAT_CVT_512
EXCEPTIONS:  AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL FLUSH_INPUT_DENORM MASKOP_EVEX MEMORY_FAULT_SUPPRESSION 
PATTERN:     EVV 0x68 VF2 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UBIT=1 W0 VL512 NOEVSR ESIZE_16_BITS() NELEM_FULL()
OPERANDS:    REG0=ZMM_R3():w:zi8 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:bf16:TXT=BCASTSTR
IFORM:       VCVTTNEBF162IBS_ZMMi8_MASKmskw_MEMbf16_AVX512
}


# EMITTING VCVTTNEBF162IUBS (VCVTTNEBF162IUBS-128-1)
{
ICLASS:      VCVTTNEBF162IUBS
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_SAT_CVT_128
EXCEPTIONS:  AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  FLUSH_INPUT_DENORM MASKOP_EVEX 
PATTERN:     EVV 0x6A VF2 MAP5 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn] W0 VL128 NOEVSR
OPERANDS:    REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:bf16
IFORM:       VCVTTNEBF162IUBS_XMMu8_MASKmskw_XMMbf16_AVX512
}

{
ICLASS:      VCVTTNEBF162IUBS
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_SAT_CVT_128
EXCEPTIONS:  AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL FLUSH_INPUT_DENORM MASKOP_EVEX MEMORY_FAULT_SUPPRESSION 
PATTERN:     EVV 0x6A VF2 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UBIT=1 W0 VL128 NOEVSR ESIZE_16_BITS() NELEM_FULL()
OPERANDS:    REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:bf16:TXT=BCASTSTR
IFORM:       VCVTTNEBF162IUBS_XMMu8_MASKmskw_MEMbf16_AVX512
}


# EMITTING VCVTTNEBF162IUBS (VCVTTNEBF162IUBS-256-1)
{
ICLASS:      VCVTTNEBF162IUBS
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_SAT_CVT_256
EXCEPTIONS:  AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  FLUSH_INPUT_DENORM MASKOP_EVEX 
PATTERN:     EVV 0x6A VF2 MAP5 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn] W0 VL256 NOEVSR
OPERANDS:    REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:bf16
IFORM:       VCVTTNEBF162IUBS_YMMu8_MASKmskw_YMMbf16_AVX512
}

{
ICLASS:      VCVTTNEBF162IUBS
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_SAT_CVT_256
EXCEPTIONS:  AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  FLUSH_INPUT_DENORM MASKOP_EVEX 
PATTERN:     EVV 0x6A VF2 MAP5 MOD[0b11] MOD=3 BCRC=1 UBIT=0 REG[rrr] RM[nnn] W0 FIX_ROUND_LEN256() NOEVSR
OPERANDS:    REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:bf16
IFORM:       VCVTTNEBF162IUBS_YMMu8_MASKmskw_YMMbf16_AVX512
}

{
ICLASS:      VCVTTNEBF162IUBS
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_SAT_CVT_256
EXCEPTIONS:  AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL FLUSH_INPUT_DENORM MASKOP_EVEX MEMORY_FAULT_SUPPRESSION 
PATTERN:     EVV 0x6A VF2 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UBIT=1 W0 VL256 NOEVSR ESIZE_16_BITS() NELEM_FULL()
OPERANDS:    REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:bf16:TXT=BCASTSTR
IFORM:       VCVTTNEBF162IUBS_YMMu8_MASKmskw_MEMbf16_AVX512
}


# EMITTING VCVTTNEBF162IUBS (VCVTTNEBF162IUBS-512-1)
{
ICLASS:      VCVTTNEBF162IUBS
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_SAT_CVT_512
EXCEPTIONS:  AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  FLUSH_INPUT_DENORM MASKOP_EVEX 
PATTERN:     EVV 0x6A VF2 MAP5 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn] W0 VL512 NOEVSR
OPERANDS:    REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zbf16
IFORM:       VCVTTNEBF162IUBS_ZMMu8_MASKmskw_ZMMbf16_AVX512
}

{
ICLASS:      VCVTTNEBF162IUBS
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_SAT_CVT_512
EXCEPTIONS:  AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  FLUSH_INPUT_DENORM MASKOP_EVEX 
PATTERN:     EVV 0x6A VF2 MAP5 MOD[0b11] MOD=3 BCRC=1 UBIT=1 REG[rrr] RM[nnn] W0 FIX_ROUND_LEN512() NOEVSR
OPERANDS:    REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zbf16
IFORM:       VCVTTNEBF162IUBS_ZMMu8_MASKmskw_ZMMbf16_AVX512
}

{
ICLASS:      VCVTTNEBF162IUBS
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_SAT_CVT_512
EXCEPTIONS:  AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL FLUSH_INPUT_DENORM MASKOP_EVEX MEMORY_FAULT_SUPPRESSION 
PATTERN:     EVV 0x6A VF2 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UBIT=1 W0 VL512 NOEVSR ESIZE_16_BITS() NELEM_FULL()
OPERANDS:    REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:bf16:TXT=BCASTSTR
IFORM:       VCVTTNEBF162IUBS_ZMMu8_MASKmskw_MEMbf16_AVX512
}


# EMITTING VCVTTPH2IBS (VCVTTPH2IBS-128-1)
{
ICLASS:      VCVTTPH2IBS
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_SAT_CVT_128
EXCEPTIONS:  AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR 
PATTERN:     EVV 0x68 VNP MAP5 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn] W0 VL128 NOEVSR
OPERANDS:    REG0=XMM_R3():w:dq:i8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f16
IFORM:       VCVTTPH2IBS_XMMi8_MASKmskw_XMMf16_AVX512
}

{
ICLASS:      VCVTTPH2IBS
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_SAT_CVT_128
EXCEPTIONS:  AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR 
PATTERN:     EVV 0x68 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UBIT=1 W0 VL128 NOEVSR ESIZE_16_BITS() NELEM_FULL()
OPERANDS:    REG0=XMM_R3():w:dq:i8 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f16:TXT=BCASTSTR
IFORM:       VCVTTPH2IBS_XMMi8_MASKmskw_MEMf16_AVX512
}


# EMITTING VCVTTPH2IBS (VCVTTPH2IBS-256-1)
{
ICLASS:      VCVTTPH2IBS
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_SAT_CVT_256
EXCEPTIONS:  AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR 
PATTERN:     EVV 0x68 VNP MAP5 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn] W0 VL256 NOEVSR
OPERANDS:    REG0=YMM_R3():w:qq:i8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f16
IFORM:       VCVTTPH2IBS_YMMi8_MASKmskw_YMMf16_AVX512
}

{
ICLASS:      VCVTTPH2IBS
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_SAT_CVT_256
EXCEPTIONS:  AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR 
PATTERN:     EVV 0x68 VNP MAP5 MOD[0b11] MOD=3 BCRC=1 UBIT=0 REG[rrr] RM[nnn] W0 FIX_ROUND_LEN256() SAE256() NOEVSR
OPERANDS:    REG0=YMM_R3():w:qq:i8:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f16
IFORM:       VCVTTPH2IBS_YMMi8_MASKmskw_YMMf16_AVX512
}

{
ICLASS:      VCVTTPH2IBS
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_SAT_CVT_256
EXCEPTIONS:  AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR 
PATTERN:     EVV 0x68 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UBIT=1 W0 VL256 NOEVSR ESIZE_16_BITS() NELEM_FULL()
OPERANDS:    REG0=YMM_R3():w:qq:i8 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f16:TXT=BCASTSTR
IFORM:       VCVTTPH2IBS_YMMi8_MASKmskw_MEMf16_AVX512
}


# EMITTING VCVTTPH2IBS (VCVTTPH2IBS-512-1)
{
ICLASS:      VCVTTPH2IBS
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_SAT_CVT_512
EXCEPTIONS:  AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR 
PATTERN:     EVV 0x68 VNP MAP5 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn] W0 VL512 NOEVSR
OPERANDS:    REG0=ZMM_R3():w:zi8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf16
IFORM:       VCVTTPH2IBS_ZMMi8_MASKmskw_ZMMf16_AVX512
}

{
ICLASS:      VCVTTPH2IBS
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_SAT_CVT_512
EXCEPTIONS:  AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR 
PATTERN:     EVV 0x68 VNP MAP5 MOD[0b11] MOD=3 BCRC=1 UBIT=1 REG[rrr] RM[nnn] W0 FIX_ROUND_LEN512() SAE() NOEVSR
OPERANDS:    REG0=ZMM_R3():w:zi8:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf16
IFORM:       VCVTTPH2IBS_ZMMi8_MASKmskw_ZMMf16_AVX512
}

{
ICLASS:      VCVTTPH2IBS
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_SAT_CVT_512
EXCEPTIONS:  AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR 
PATTERN:     EVV 0x68 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UBIT=1 W0 VL512 NOEVSR ESIZE_16_BITS() NELEM_FULL()
OPERANDS:    REG0=ZMM_R3():w:zi8 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f16:TXT=BCASTSTR
IFORM:       VCVTTPH2IBS_ZMMi8_MASKmskw_MEMf16_AVX512
}


# EMITTING VCVTTPH2IUBS (VCVTTPH2IUBS-128-1)
{
ICLASS:      VCVTTPH2IUBS
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_SAT_CVT_128
EXCEPTIONS:  AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR 
PATTERN:     EVV 0x6A VNP MAP5 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn] W0 VL128 NOEVSR
OPERANDS:    REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f16
IFORM:       VCVTTPH2IUBS_XMMu8_MASKmskw_XMMf16_AVX512
}

{
ICLASS:      VCVTTPH2IUBS
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_SAT_CVT_128
EXCEPTIONS:  AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR 
PATTERN:     EVV 0x6A VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UBIT=1 W0 VL128 NOEVSR ESIZE_16_BITS() NELEM_FULL()
OPERANDS:    REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f16:TXT=BCASTSTR
IFORM:       VCVTTPH2IUBS_XMMu8_MASKmskw_MEMf16_AVX512
}


# EMITTING VCVTTPH2IUBS (VCVTTPH2IUBS-256-1)
{
ICLASS:      VCVTTPH2IUBS
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_SAT_CVT_256
EXCEPTIONS:  AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR 
PATTERN:     EVV 0x6A VNP MAP5 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn] W0 VL256 NOEVSR
OPERANDS:    REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f16
IFORM:       VCVTTPH2IUBS_YMMu8_MASKmskw_YMMf16_AVX512
}

{
ICLASS:      VCVTTPH2IUBS
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_SAT_CVT_256
EXCEPTIONS:  AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR 
PATTERN:     EVV 0x6A VNP MAP5 MOD[0b11] MOD=3 BCRC=1 UBIT=0 REG[rrr] RM[nnn] W0 FIX_ROUND_LEN256() SAE256() NOEVSR
OPERANDS:    REG0=YMM_R3():w:qq:u8:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f16
IFORM:       VCVTTPH2IUBS_YMMu8_MASKmskw_YMMf16_AVX512
}

{
ICLASS:      VCVTTPH2IUBS
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_SAT_CVT_256
EXCEPTIONS:  AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR 
PATTERN:     EVV 0x6A VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UBIT=1 W0 VL256 NOEVSR ESIZE_16_BITS() NELEM_FULL()
OPERANDS:    REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f16:TXT=BCASTSTR
IFORM:       VCVTTPH2IUBS_YMMu8_MASKmskw_MEMf16_AVX512
}


# EMITTING VCVTTPH2IUBS (VCVTTPH2IUBS-512-1)
{
ICLASS:      VCVTTPH2IUBS
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_SAT_CVT_512
EXCEPTIONS:  AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR 
PATTERN:     EVV 0x6A VNP MAP5 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn] W0 VL512 NOEVSR
OPERANDS:    REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf16
IFORM:       VCVTTPH2IUBS_ZMMu8_MASKmskw_ZMMf16_AVX512
}

{
ICLASS:      VCVTTPH2IUBS
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_SAT_CVT_512
EXCEPTIONS:  AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR 
PATTERN:     EVV 0x6A VNP MAP5 MOD[0b11] MOD=3 BCRC=1 UBIT=1 REG[rrr] RM[nnn] W0 FIX_ROUND_LEN512() SAE() NOEVSR
OPERANDS:    REG0=ZMM_R3():w:zu8:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf16
IFORM:       VCVTTPH2IUBS_ZMMu8_MASKmskw_ZMMf16_AVX512
}

{
ICLASS:      VCVTTPH2IUBS
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_SAT_CVT_512
EXCEPTIONS:  AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR 
PATTERN:     EVV 0x6A VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UBIT=1 W0 VL512 NOEVSR ESIZE_16_BITS() NELEM_FULL()
OPERANDS:    REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f16:TXT=BCASTSTR
IFORM:       VCVTTPH2IUBS_ZMMu8_MASKmskw_MEMf16_AVX512
}


# EMITTING VCVTTPS2IBS (VCVTTPS2IBS-128-1)
{
ICLASS:      VCVTTPS2IBS
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_SAT_CVT_128
EXCEPTIONS:  AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR USES_DAZ 
PATTERN:     EVV 0x68 V66 MAP5 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn] W0 VL128 NOEVSR
OPERANDS:    REG0=XMM_R3():w:dq:i8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f32
IFORM:       VCVTTPS2IBS_XMMi8_MASKmskw_XMMf32_AVX512
}

{
ICLASS:      VCVTTPS2IBS
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_SAT_CVT_128
EXCEPTIONS:  AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR USES_DAZ 
PATTERN:     EVV 0x68 V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UBIT=1 W0 VL128 NOEVSR ESIZE_32_BITS() NELEM_FULL()
OPERANDS:    REG0=XMM_R3():w:dq:i8 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR
IFORM:       VCVTTPS2IBS_XMMi8_MASKmskw_MEMf32_AVX512
}


# EMITTING VCVTTPS2IBS (VCVTTPS2IBS-256-1)
{
ICLASS:      VCVTTPS2IBS
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_SAT_CVT_256
EXCEPTIONS:  AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR USES_DAZ 
PATTERN:     EVV 0x68 V66 MAP5 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn] W0 VL256 NOEVSR
OPERANDS:    REG0=YMM_R3():w:qq:i8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f32
IFORM:       VCVTTPS2IBS_YMMi8_MASKmskw_YMMf32_AVX512
}

{
ICLASS:      VCVTTPS2IBS
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_SAT_CVT_256
EXCEPTIONS:  AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR USES_DAZ 
PATTERN:     EVV 0x68 V66 MAP5 MOD[0b11] MOD=3 BCRC=1 UBIT=0 REG[rrr] RM[nnn] W0 FIX_ROUND_LEN256() SAE256() NOEVSR
OPERANDS:    REG0=YMM_R3():w:qq:i8:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f32
IFORM:       VCVTTPS2IBS_YMMi8_MASKmskw_YMMf32_AVX512
}

{
ICLASS:      VCVTTPS2IBS
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_SAT_CVT_256
EXCEPTIONS:  AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR USES_DAZ 
PATTERN:     EVV 0x68 V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UBIT=1 W0 VL256 NOEVSR ESIZE_32_BITS() NELEM_FULL()
OPERANDS:    REG0=YMM_R3():w:qq:i8 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR
IFORM:       VCVTTPS2IBS_YMMi8_MASKmskw_MEMf32_AVX512
}


# EMITTING VCVTTPS2IBS (VCVTTPS2IBS-512-1)
{
ICLASS:      VCVTTPS2IBS
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_SAT_CVT_512
EXCEPTIONS:  AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR USES_DAZ 
PATTERN:     EVV 0x68 V66 MAP5 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn] W0 VL512 NOEVSR
OPERANDS:    REG0=ZMM_R3():w:zi8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf32
IFORM:       VCVTTPS2IBS_ZMMi8_MASKmskw_ZMMf32_AVX512
}

{
ICLASS:      VCVTTPS2IBS
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_SAT_CVT_512
EXCEPTIONS:  AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR USES_DAZ 
PATTERN:     EVV 0x68 V66 MAP5 MOD[0b11] MOD=3 BCRC=1 UBIT=1 REG[rrr] RM[nnn] W0 FIX_ROUND_LEN512() SAE() NOEVSR
OPERANDS:    REG0=ZMM_R3():w:zi8:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf32
IFORM:       VCVTTPS2IBS_ZMMi8_MASKmskw_ZMMf32_AVX512
}

{
ICLASS:      VCVTTPS2IBS
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_SAT_CVT_512
EXCEPTIONS:  AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR USES_DAZ 
PATTERN:     EVV 0x68 V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UBIT=1 W0 VL512 NOEVSR ESIZE_32_BITS() NELEM_FULL()
OPERANDS:    REG0=ZMM_R3():w:zi8 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR
IFORM:       VCVTTPS2IBS_ZMMi8_MASKmskw_MEMf32_AVX512
}


# EMITTING VCVTTPS2IUBS (VCVTTPS2IUBS-128-1)
{
ICLASS:      VCVTTPS2IUBS
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_SAT_CVT_128
EXCEPTIONS:  AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR USES_DAZ 
PATTERN:     EVV 0x6A V66 MAP5 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn] W0 VL128 NOEVSR
OPERANDS:    REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f32
IFORM:       VCVTTPS2IUBS_XMMu8_MASKmskw_XMMf32_AVX512
}

{
ICLASS:      VCVTTPS2IUBS
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_SAT_CVT_128
EXCEPTIONS:  AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR USES_DAZ 
PATTERN:     EVV 0x6A V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UBIT=1 W0 VL128 NOEVSR ESIZE_32_BITS() NELEM_FULL()
OPERANDS:    REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR
IFORM:       VCVTTPS2IUBS_XMMu8_MASKmskw_MEMf32_AVX512
}


# EMITTING VCVTTPS2IUBS (VCVTTPS2IUBS-256-1)
{
ICLASS:      VCVTTPS2IUBS
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_SAT_CVT_256
EXCEPTIONS:  AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR USES_DAZ 
PATTERN:     EVV 0x6A V66 MAP5 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn] W0 VL256 NOEVSR
OPERANDS:    REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f32
IFORM:       VCVTTPS2IUBS_YMMu8_MASKmskw_YMMf32_AVX512
}

{
ICLASS:      VCVTTPS2IUBS
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_SAT_CVT_256
EXCEPTIONS:  AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR USES_DAZ 
PATTERN:     EVV 0x6A V66 MAP5 MOD[0b11] MOD=3 BCRC=1 UBIT=0 REG[rrr] RM[nnn] W0 FIX_ROUND_LEN256() SAE256() NOEVSR
OPERANDS:    REG0=YMM_R3():w:qq:u8:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f32
IFORM:       VCVTTPS2IUBS_YMMu8_MASKmskw_YMMf32_AVX512
}

{
ICLASS:      VCVTTPS2IUBS
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_SAT_CVT_256
EXCEPTIONS:  AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR USES_DAZ 
PATTERN:     EVV 0x6A V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UBIT=1 W0 VL256 NOEVSR ESIZE_32_BITS() NELEM_FULL()
OPERANDS:    REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR
IFORM:       VCVTTPS2IUBS_YMMu8_MASKmskw_MEMf32_AVX512
}


# EMITTING VCVTTPS2IUBS (VCVTTPS2IUBS-512-1)
{
ICLASS:      VCVTTPS2IUBS
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_SAT_CVT_512
EXCEPTIONS:  AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR USES_DAZ 
PATTERN:     EVV 0x6A V66 MAP5 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn] W0 VL512 NOEVSR
OPERANDS:    REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf32
IFORM:       VCVTTPS2IUBS_ZMMu8_MASKmskw_ZMMf32_AVX512
}

{
ICLASS:      VCVTTPS2IUBS
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_SAT_CVT_512
EXCEPTIONS:  AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR USES_DAZ 
PATTERN:     EVV 0x6A V66 MAP5 MOD[0b11] MOD=3 BCRC=1 UBIT=1 REG[rrr] RM[nnn] W0 FIX_ROUND_LEN512() SAE() NOEVSR
OPERANDS:    REG0=ZMM_R3():w:zu8:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf32
IFORM:       VCVTTPS2IUBS_ZMMu8_MASKmskw_ZMMf32_AVX512
}

{
ICLASS:      VCVTTPS2IUBS
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_SAT_CVT_512
EXCEPTIONS:  AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR USES_DAZ 
PATTERN:     EVV 0x6A V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UBIT=1 W0 VL512 NOEVSR ESIZE_32_BITS() NELEM_FULL()
OPERANDS:    REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR
IFORM:       VCVTTPS2IUBS_ZMMu8_MASKmskw_MEMf32_AVX512
}


# EMITTING VDPPHPS (VDPPHPS-128-1)
{
ICLASS:      VDPPHPS
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_VNNI_FP16_128
EXCEPTIONS:  AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  FIXED_ROUNDING_RNE FLUSH_INPUT_DENORM FLUSH_OUTPUT_DENORM MASKOP_EVEX 
PATTERN:     EVV 0x52 VNP V0F38 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn] W0 VL128
OPERANDS:    REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:2f16 REG3=XMM_B3():r:dq:2f16
IFORM:       VDPPHPS_XMMf32_MASKmskw_XMM2f16_XMM2f16_AVX512
}

{
ICLASS:      VDPPHPS
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_VNNI_FP16_128
EXCEPTIONS:  AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL FIXED_ROUNDING_RNE FLUSH_INPUT_DENORM FLUSH_OUTPUT_DENORM MASKOP_EVEX MEMORY_FAULT_SUPPRESSION 
PATTERN:     EVV 0x52 VNP V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UBIT=1 W0 VL128 ESIZE_32_BITS() NELEM_FULL()
OPERANDS:    REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:2f16 MEM0:r:vv:2f16:TXT=BCASTSTR
IFORM:       VDPPHPS_XMMf32_MASKmskw_XMM2f16_MEM2f16_AVX512
}


# EMITTING VDPPHPS (VDPPHPS-256-1)
{
ICLASS:      VDPPHPS
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_VNNI_FP16_256
EXCEPTIONS:  AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  FIXED_ROUNDING_RNE FLUSH_INPUT_DENORM FLUSH_OUTPUT_DENORM MASKOP_EVEX 
PATTERN:     EVV 0x52 VNP V0F38 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn] W0 VL256
OPERANDS:    REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:2f16 REG3=YMM_B3():r:qq:2f16
IFORM:       VDPPHPS_YMMf32_MASKmskw_YMM2f16_YMM2f16_AVX512
}

{
ICLASS:      VDPPHPS
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_VNNI_FP16_256
EXCEPTIONS:  AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL FIXED_ROUNDING_RNE FLUSH_INPUT_DENORM FLUSH_OUTPUT_DENORM MASKOP_EVEX MEMORY_FAULT_SUPPRESSION 
PATTERN:     EVV 0x52 VNP V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UBIT=1 W0 VL256 ESIZE_32_BITS() NELEM_FULL()
OPERANDS:    REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:2f16 MEM0:r:vv:2f16:TXT=BCASTSTR
IFORM:       VDPPHPS_YMMf32_MASKmskw_YMM2f16_MEM2f16_AVX512
}


# EMITTING VDPPHPS (VDPPHPS-512-1)
{
ICLASS:      VDPPHPS
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_VNNI_FP16_512
EXCEPTIONS:  AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  FIXED_ROUNDING_RNE FLUSH_INPUT_DENORM FLUSH_OUTPUT_DENORM MASKOP_EVEX 
PATTERN:     EVV 0x52 VNP V0F38 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn] W0 VL512
OPERANDS:    REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:z2f16 REG3=ZMM_B3():r:z2f16
IFORM:       VDPPHPS_ZMMf32_MASKmskw_ZMM2f16_ZMM2f16_AVX512
}

{
ICLASS:      VDPPHPS
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_VNNI_FP16_512
EXCEPTIONS:  AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL FIXED_ROUNDING_RNE FLUSH_INPUT_DENORM FLUSH_OUTPUT_DENORM MASKOP_EVEX MEMORY_FAULT_SUPPRESSION 
PATTERN:     EVV 0x52 VNP V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UBIT=1 W0 VL512 ESIZE_32_BITS() NELEM_FULL()
OPERANDS:    REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:z2f16 MEM0:r:vv:2f16:TXT=BCASTSTR
IFORM:       VDPPHPS_ZMMf32_MASKmskw_ZMM2f16_MEM2f16_AVX512
}


# EMITTING VMPSADBW (VMPSADBW-128-2)
{
ICLASS:      VMPSADBW
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_MEDIAX_128
EXCEPTIONS:  AVX512-E4NF
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX 
PATTERN:     EVV 0x42 VF3 V0F3A MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn] W0 VL128 UIMM8()
OPERANDS:    REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 REG3=XMM_B3():r:dq:u8 IMM0:r:b
IFORM:       VMPSADBW_XMMu16_MASKmskw_XMMu8_XMMu8_IMM8_AVX512
}

{
ICLASS:      VMPSADBW
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_MEDIAX_128
EXCEPTIONS:  AVX512-E4NF
REAL_OPCODE: Y
ATTRIBUTES:  DISP8_FULLMEM MASKOP_EVEX 
PATTERN:     EVV 0x42 VF3 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() BCRC=0 UBIT=1 W0 VL128 UIMM8() ESIZE_16_BITS() NELEM_FULLMEM()
OPERANDS:    REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 MEM0:r:dq:u8 IMM0:r:b
IFORM:       VMPSADBW_XMMu16_MASKmskw_XMMu8_MEMu8_IMM8_AVX512
}


# EMITTING VMPSADBW (VMPSADBW-256-2)
{
ICLASS:      VMPSADBW
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_MEDIAX_256
EXCEPTIONS:  AVX512-E4NF
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX 
PATTERN:     EVV 0x42 VF3 V0F3A MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn] W0 VL256 UIMM8()
OPERANDS:    REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 REG3=YMM_B3():r:qq:u8 IMM0:r:b
IFORM:       VMPSADBW_YMMu16_MASKmskw_YMMu8_YMMu8_IMM8_AVX512
}

{
ICLASS:      VMPSADBW
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_MEDIAX_256
EXCEPTIONS:  AVX512-E4NF
REAL_OPCODE: Y
ATTRIBUTES:  DISP8_FULLMEM MASKOP_EVEX 
PATTERN:     EVV 0x42 VF3 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() BCRC=0 UBIT=1 W0 VL256 UIMM8() ESIZE_16_BITS() NELEM_FULLMEM()
OPERANDS:    REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 MEM0:r:qq:u8 IMM0:r:b
IFORM:       VMPSADBW_YMMu16_MASKmskw_YMMu8_MEMu8_IMM8_AVX512
}


# EMITTING VMPSADBW (VMPSADBW-512-1)
{
ICLASS:      VMPSADBW
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_MEDIAX_512
EXCEPTIONS:  AVX512-E4NF
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX 
PATTERN:     EVV 0x42 VF3 V0F3A MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn] W0 VL512 UIMM8()
OPERANDS:    REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 REG3=ZMM_B3():r:zu8 IMM0:r:b
IFORM:       VMPSADBW_ZMMu16_MASKmskw_ZMMu8_ZMMu8_IMM8_AVX512
}

{
ICLASS:      VMPSADBW
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_MEDIAX_512
EXCEPTIONS:  AVX512-E4NF
REAL_OPCODE: Y
ATTRIBUTES:  DISP8_FULLMEM MASKOP_EVEX 
PATTERN:     EVV 0x42 VF3 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() BCRC=0 UBIT=1 W0 VL512 UIMM8() ESIZE_16_BITS() NELEM_FULLMEM()
OPERANDS:    REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 MEM0:r:zd:u8 IMM0:r:b
IFORM:       VMPSADBW_ZMMu16_MASKmskw_ZMMu8_MEMu8_IMM8_AVX512
}


# EMITTING VPDPBSSD (VPDPBSSD-128-1)
{
ICLASS:      VPDPBSSD
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_VNNI_INT8_128
EXCEPTIONS:  AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX 
PATTERN:     EVV 0x50 VF2 V0F38 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn] W0 VL128
OPERANDS:    REG0=XMM_R3():rw:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:4i8 REG3=XMM_B3():r:dq:4i8
IFORM:       VPDPBSSD_XMMi32_MASKmskw_XMM4i8_XMM4i8_AVX512
}

{
ICLASS:      VPDPBSSD
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_VNNI_INT8_128
EXCEPTIONS:  AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION 
PATTERN:     EVV 0x50 VF2 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UBIT=1 W0 VL128 ESIZE_32_BITS() NELEM_FULL()
OPERANDS:    REG0=XMM_R3():rw:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:4i8 MEM0:r:vv:4i8:TXT=BCASTSTR
IFORM:       VPDPBSSD_XMMi32_MASKmskw_XMM4i8_MEM4i8_AVX512
}


# EMITTING VPDPBSSD (VPDPBSSD-256-1)
{
ICLASS:      VPDPBSSD
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_VNNI_INT8_256
EXCEPTIONS:  AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX 
PATTERN:     EVV 0x50 VF2 V0F38 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn] W0 VL256
OPERANDS:    REG0=YMM_R3():rw:qq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:4i8 REG3=YMM_B3():r:qq:4i8
IFORM:       VPDPBSSD_YMMi32_MASKmskw_YMM4i8_YMM4i8_AVX512
}

{
ICLASS:      VPDPBSSD
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_VNNI_INT8_256
EXCEPTIONS:  AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION 
PATTERN:     EVV 0x50 VF2 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UBIT=1 W0 VL256 ESIZE_32_BITS() NELEM_FULL()
OPERANDS:    REG0=YMM_R3():rw:qq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:4i8 MEM0:r:vv:4i8:TXT=BCASTSTR
IFORM:       VPDPBSSD_YMMi32_MASKmskw_YMM4i8_MEM4i8_AVX512
}


# EMITTING VPDPBSSD (VPDPBSSD-512-1)
{
ICLASS:      VPDPBSSD
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_VNNI_INT8_512
EXCEPTIONS:  AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX 
PATTERN:     EVV 0x50 VF2 V0F38 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn] W0 VL512
OPERANDS:    REG0=ZMM_R3():rw:zi32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:z4i8 REG3=ZMM_B3():r:z4i8
IFORM:       VPDPBSSD_ZMMi32_MASKmskw_ZMM4i8_ZMM4i8_AVX512
}

{
ICLASS:      VPDPBSSD
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_VNNI_INT8_512
EXCEPTIONS:  AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION 
PATTERN:     EVV 0x50 VF2 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UBIT=1 W0 VL512 ESIZE_32_BITS() NELEM_FULL()
OPERANDS:    REG0=ZMM_R3():rw:zi32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:z4i8 MEM0:r:vv:4i8:TXT=BCASTSTR
IFORM:       VPDPBSSD_ZMMi32_MASKmskw_ZMM4i8_MEM4i8_AVX512
}


# EMITTING VPDPBSSDS (VPDPBSSDS-128-1)
{
ICLASS:      VPDPBSSDS
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_VNNI_INT8_128
EXCEPTIONS:  AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX 
PATTERN:     EVV 0x51 VF2 V0F38 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn] W0 VL128
OPERANDS:    REG0=XMM_R3():rw:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:4i8 REG3=XMM_B3():r:dq:4i8
IFORM:       VPDPBSSDS_XMMi32_MASKmskw_XMM4i8_XMM4i8_AVX512
}

{
ICLASS:      VPDPBSSDS
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_VNNI_INT8_128
EXCEPTIONS:  AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION 
PATTERN:     EVV 0x51 VF2 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UBIT=1 W0 VL128 ESIZE_32_BITS() NELEM_FULL()
OPERANDS:    REG0=XMM_R3():rw:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:4i8 MEM0:r:vv:4i8:TXT=BCASTSTR
IFORM:       VPDPBSSDS_XMMi32_MASKmskw_XMM4i8_MEM4i8_AVX512
}


# EMITTING VPDPBSSDS (VPDPBSSDS-256-1)
{
ICLASS:      VPDPBSSDS
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_VNNI_INT8_256
EXCEPTIONS:  AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX 
PATTERN:     EVV 0x51 VF2 V0F38 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn] W0 VL256
OPERANDS:    REG0=YMM_R3():rw:qq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:4i8 REG3=YMM_B3():r:qq:4i8
IFORM:       VPDPBSSDS_YMMi32_MASKmskw_YMM4i8_YMM4i8_AVX512
}

{
ICLASS:      VPDPBSSDS
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_VNNI_INT8_256
EXCEPTIONS:  AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION 
PATTERN:     EVV 0x51 VF2 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UBIT=1 W0 VL256 ESIZE_32_BITS() NELEM_FULL()
OPERANDS:    REG0=YMM_R3():rw:qq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:4i8 MEM0:r:vv:4i8:TXT=BCASTSTR
IFORM:       VPDPBSSDS_YMMi32_MASKmskw_YMM4i8_MEM4i8_AVX512
}


# EMITTING VPDPBSSDS (VPDPBSSDS-512-1)
{
ICLASS:      VPDPBSSDS
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_VNNI_INT8_512
EXCEPTIONS:  AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX 
PATTERN:     EVV 0x51 VF2 V0F38 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn] W0 VL512
OPERANDS:    REG0=ZMM_R3():rw:zi32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:z4i8 REG3=ZMM_B3():r:z4i8
IFORM:       VPDPBSSDS_ZMMi32_MASKmskw_ZMM4i8_ZMM4i8_AVX512
}

{
ICLASS:      VPDPBSSDS
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_VNNI_INT8_512
EXCEPTIONS:  AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION 
PATTERN:     EVV 0x51 VF2 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UBIT=1 W0 VL512 ESIZE_32_BITS() NELEM_FULL()
OPERANDS:    REG0=ZMM_R3():rw:zi32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:z4i8 MEM0:r:vv:4i8:TXT=BCASTSTR
IFORM:       VPDPBSSDS_ZMMi32_MASKmskw_ZMM4i8_MEM4i8_AVX512
}


# EMITTING VPDPBSUD (VPDPBSUD-128-1)
{
ICLASS:      VPDPBSUD
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_VNNI_INT8_128
EXCEPTIONS:  AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX 
PATTERN:     EVV 0x50 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn] W0 VL128
OPERANDS:    REG0=XMM_R3():rw:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:4i8 REG3=XMM_B3():r:dq:4u8
IFORM:       VPDPBSUD_XMMi32_MASKmskw_XMM4i8_XMM4u8_AVX512
}

{
ICLASS:      VPDPBSUD
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_VNNI_INT8_128
EXCEPTIONS:  AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION 
PATTERN:     EVV 0x50 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UBIT=1 W0 VL128 ESIZE_32_BITS() NELEM_FULL()
OPERANDS:    REG0=XMM_R3():rw:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:4i8 MEM0:r:vv:4u8:TXT=BCASTSTR
IFORM:       VPDPBSUD_XMMi32_MASKmskw_XMM4i8_MEM4u8_AVX512
}


# EMITTING VPDPBSUD (VPDPBSUD-256-1)
{
ICLASS:      VPDPBSUD
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_VNNI_INT8_256
EXCEPTIONS:  AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX 
PATTERN:     EVV 0x50 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn] W0 VL256
OPERANDS:    REG0=YMM_R3():rw:qq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:4i8 REG3=YMM_B3():r:qq:4u8
IFORM:       VPDPBSUD_YMMi32_MASKmskw_YMM4i8_YMM4u8_AVX512
}

{
ICLASS:      VPDPBSUD
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_VNNI_INT8_256
EXCEPTIONS:  AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION 
PATTERN:     EVV 0x50 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UBIT=1 W0 VL256 ESIZE_32_BITS() NELEM_FULL()
OPERANDS:    REG0=YMM_R3():rw:qq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:4i8 MEM0:r:vv:4u8:TXT=BCASTSTR
IFORM:       VPDPBSUD_YMMi32_MASKmskw_YMM4i8_MEM4u8_AVX512
}


# EMITTING VPDPBSUD (VPDPBSUD-512-1)
{
ICLASS:      VPDPBSUD
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_VNNI_INT8_512
EXCEPTIONS:  AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX 
PATTERN:     EVV 0x50 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn] W0 VL512
OPERANDS:    REG0=ZMM_R3():rw:zi32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:z4i8 REG3=ZMM_B3():r:z4u8
IFORM:       VPDPBSUD_ZMMi32_MASKmskw_ZMM4i8_ZMM4u8_AVX512
}

{
ICLASS:      VPDPBSUD
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_VNNI_INT8_512
EXCEPTIONS:  AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION 
PATTERN:     EVV 0x50 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UBIT=1 W0 VL512 ESIZE_32_BITS() NELEM_FULL()
OPERANDS:    REG0=ZMM_R3():rw:zi32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:z4i8 MEM0:r:vv:4u8:TXT=BCASTSTR
IFORM:       VPDPBSUD_ZMMi32_MASKmskw_ZMM4i8_MEM4u8_AVX512
}


# EMITTING VPDPBSUDS (VPDPBSUDS-128-1)
{
ICLASS:      VPDPBSUDS
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_VNNI_INT8_128
EXCEPTIONS:  AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX 
PATTERN:     EVV 0x51 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn] W0 VL128
OPERANDS:    REG0=XMM_R3():rw:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:4i8 REG3=XMM_B3():r:dq:4u8
IFORM:       VPDPBSUDS_XMMi32_MASKmskw_XMM4i8_XMM4u8_AVX512
}

{
ICLASS:      VPDPBSUDS
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_VNNI_INT8_128
EXCEPTIONS:  AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION 
PATTERN:     EVV 0x51 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UBIT=1 W0 VL128 ESIZE_32_BITS() NELEM_FULL()
OPERANDS:    REG0=XMM_R3():rw:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:4i8 MEM0:r:vv:4u8:TXT=BCASTSTR
IFORM:       VPDPBSUDS_XMMi32_MASKmskw_XMM4i8_MEM4u8_AVX512
}


# EMITTING VPDPBSUDS (VPDPBSUDS-256-1)
{
ICLASS:      VPDPBSUDS
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_VNNI_INT8_256
EXCEPTIONS:  AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX 
PATTERN:     EVV 0x51 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn] W0 VL256
OPERANDS:    REG0=YMM_R3():rw:qq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:4i8 REG3=YMM_B3():r:qq:4u8
IFORM:       VPDPBSUDS_YMMi32_MASKmskw_YMM4i8_YMM4u8_AVX512
}

{
ICLASS:      VPDPBSUDS
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_VNNI_INT8_256
EXCEPTIONS:  AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION 
PATTERN:     EVV 0x51 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UBIT=1 W0 VL256 ESIZE_32_BITS() NELEM_FULL()
OPERANDS:    REG0=YMM_R3():rw:qq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:4i8 MEM0:r:vv:4u8:TXT=BCASTSTR
IFORM:       VPDPBSUDS_YMMi32_MASKmskw_YMM4i8_MEM4u8_AVX512
}


# EMITTING VPDPBSUDS (VPDPBSUDS-512-1)
{
ICLASS:      VPDPBSUDS
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_VNNI_INT8_512
EXCEPTIONS:  AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX 
PATTERN:     EVV 0x51 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn] W0 VL512
OPERANDS:    REG0=ZMM_R3():rw:zi32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:z4i8 REG3=ZMM_B3():r:z4u8
IFORM:       VPDPBSUDS_ZMMi32_MASKmskw_ZMM4i8_ZMM4u8_AVX512
}

{
ICLASS:      VPDPBSUDS
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_VNNI_INT8_512
EXCEPTIONS:  AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION 
PATTERN:     EVV 0x51 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UBIT=1 W0 VL512 ESIZE_32_BITS() NELEM_FULL()
OPERANDS:    REG0=ZMM_R3():rw:zi32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:z4i8 MEM0:r:vv:4u8:TXT=BCASTSTR
IFORM:       VPDPBSUDS_ZMMi32_MASKmskw_ZMM4i8_MEM4u8_AVX512
}


# EMITTING VPDPBUUD (VPDPBUUD-128-1)
{
ICLASS:      VPDPBUUD
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_VNNI_INT8_128
EXCEPTIONS:  AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX 
PATTERN:     EVV 0x50 VNP V0F38 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn] W0 VL128
OPERANDS:    REG0=XMM_R3():rw:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:4u8 REG3=XMM_B3():r:dq:4u8
IFORM:       VPDPBUUD_XMMu32_MASKmskw_XMM4u8_XMM4u8_AVX512
}

{
ICLASS:      VPDPBUUD
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_VNNI_INT8_128
EXCEPTIONS:  AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION 
PATTERN:     EVV 0x50 VNP V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UBIT=1 W0 VL128 ESIZE_32_BITS() NELEM_FULL()
OPERANDS:    REG0=XMM_R3():rw:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:4u8 MEM0:r:vv:4u8:TXT=BCASTSTR
IFORM:       VPDPBUUD_XMMu32_MASKmskw_XMM4u8_MEM4u8_AVX512
}


# EMITTING VPDPBUUD (VPDPBUUD-256-1)
{
ICLASS:      VPDPBUUD
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_VNNI_INT8_256
EXCEPTIONS:  AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX 
PATTERN:     EVV 0x50 VNP V0F38 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn] W0 VL256
OPERANDS:    REG0=YMM_R3():rw:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:4u8 REG3=YMM_B3():r:qq:4u8
IFORM:       VPDPBUUD_YMMu32_MASKmskw_YMM4u8_YMM4u8_AVX512
}

{
ICLASS:      VPDPBUUD
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_VNNI_INT8_256
EXCEPTIONS:  AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION 
PATTERN:     EVV 0x50 VNP V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UBIT=1 W0 VL256 ESIZE_32_BITS() NELEM_FULL()
OPERANDS:    REG0=YMM_R3():rw:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:4u8 MEM0:r:vv:4u8:TXT=BCASTSTR
IFORM:       VPDPBUUD_YMMu32_MASKmskw_YMM4u8_MEM4u8_AVX512
}


# EMITTING VPDPBUUD (VPDPBUUD-512-1)
{
ICLASS:      VPDPBUUD
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_VNNI_INT8_512
EXCEPTIONS:  AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX 
PATTERN:     EVV 0x50 VNP V0F38 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn] W0 VL512
OPERANDS:    REG0=ZMM_R3():rw:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:z4u8 REG3=ZMM_B3():r:z4u8
IFORM:       VPDPBUUD_ZMMu32_MASKmskw_ZMM4u8_ZMM4u8_AVX512
}

{
ICLASS:      VPDPBUUD
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_VNNI_INT8_512
EXCEPTIONS:  AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION 
PATTERN:     EVV 0x50 VNP V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UBIT=1 W0 VL512 ESIZE_32_BITS() NELEM_FULL()
OPERANDS:    REG0=ZMM_R3():rw:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:z4u8 MEM0:r:vv:4u8:TXT=BCASTSTR
IFORM:       VPDPBUUD_ZMMu32_MASKmskw_ZMM4u8_MEM4u8_AVX512
}


# EMITTING VPDPBUUDS (VPDPBUUDS-128-1)
{
ICLASS:      VPDPBUUDS
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_VNNI_INT8_128
EXCEPTIONS:  AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX 
PATTERN:     EVV 0x51 VNP V0F38 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn] W0 VL128
OPERANDS:    REG0=XMM_R3():rw:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:4u8 REG3=XMM_B3():r:dq:4u8
IFORM:       VPDPBUUDS_XMMu32_MASKmskw_XMM4u8_XMM4u8_AVX512
}

{
ICLASS:      VPDPBUUDS
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_VNNI_INT8_128
EXCEPTIONS:  AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION 
PATTERN:     EVV 0x51 VNP V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UBIT=1 W0 VL128 ESIZE_32_BITS() NELEM_FULL()
OPERANDS:    REG0=XMM_R3():rw:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:4u8 MEM0:r:vv:4u8:TXT=BCASTSTR
IFORM:       VPDPBUUDS_XMMu32_MASKmskw_XMM4u8_MEM4u8_AVX512
}


# EMITTING VPDPBUUDS (VPDPBUUDS-256-1)
{
ICLASS:      VPDPBUUDS
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_VNNI_INT8_256
EXCEPTIONS:  AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX 
PATTERN:     EVV 0x51 VNP V0F38 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn] W0 VL256
OPERANDS:    REG0=YMM_R3():rw:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:4u8 REG3=YMM_B3():r:qq:4u8
IFORM:       VPDPBUUDS_YMMu32_MASKmskw_YMM4u8_YMM4u8_AVX512
}

{
ICLASS:      VPDPBUUDS
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_VNNI_INT8_256
EXCEPTIONS:  AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION 
PATTERN:     EVV 0x51 VNP V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UBIT=1 W0 VL256 ESIZE_32_BITS() NELEM_FULL()
OPERANDS:    REG0=YMM_R3():rw:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:4u8 MEM0:r:vv:4u8:TXT=BCASTSTR
IFORM:       VPDPBUUDS_YMMu32_MASKmskw_YMM4u8_MEM4u8_AVX512
}


# EMITTING VPDPBUUDS (VPDPBUUDS-512-1)
{
ICLASS:      VPDPBUUDS
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_VNNI_INT8_512
EXCEPTIONS:  AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX 
PATTERN:     EVV 0x51 VNP V0F38 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn] W0 VL512
OPERANDS:    REG0=ZMM_R3():rw:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:z4u8 REG3=ZMM_B3():r:z4u8
IFORM:       VPDPBUUDS_ZMMu32_MASKmskw_ZMM4u8_ZMM4u8_AVX512
}

{
ICLASS:      VPDPBUUDS
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_VNNI_INT8_512
EXCEPTIONS:  AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION 
PATTERN:     EVV 0x51 VNP V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UBIT=1 W0 VL512 ESIZE_32_BITS() NELEM_FULL()
OPERANDS:    REG0=ZMM_R3():rw:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:z4u8 MEM0:r:vv:4u8:TXT=BCASTSTR
IFORM:       VPDPBUUDS_ZMMu32_MASKmskw_ZMM4u8_MEM4u8_AVX512
}


