#BEGIN_LEGAL
#
#Copyright (c) 2024 Intel Corporation
#
#  Licensed under the Apache License, Version 2.0 (the "License");
#  you may not use this file except in compliance with the License.
#  You may obtain a copy of the License at
#
#      http://www.apache.org/licenses/LICENSE-2.0
#
#  Unless required by applicable law or agreed to in writing, software
#  distributed under the License is distributed on an "AS IS" BASIS,
#  WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
#  See the License for the specific language governing permissions and
#  limitations under the License.
#  
#END_LEGAL
#
#
#
#    ***** GENERATED FILE -- DO NOT EDIT! *****
#    ***** GENERATED FILE -- DO NOT EDIT! *****
#    ***** GENERATED FILE -- DO NOT EDIT! *****
#
#
#
EVEX_INSTRUCTIONS()::
# EMITTING VPDPWSUD (VPDPWSUD-128-1)
{
ICLASS:      VPDPWSUD
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_VNNI_INT16_128
EXCEPTIONS:  AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX 
PATTERN:     EVV 0xD2 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn] W0 VL128
OPERANDS:    REG0=XMM_R3():rw:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:2i16 REG3=XMM_B3():r:dq:2u16
IFORM:       VPDPWSUD_XMMi32_MASKmskw_XMM2i16_XMM2u16_AVX512
}

{
ICLASS:      VPDPWSUD
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_VNNI_INT16_128
EXCEPTIONS:  AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION 
PATTERN:     EVV 0xD2 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UBIT=1 W0 VL128 ESIZE_32_BITS() NELEM_FULL()
OPERANDS:    REG0=XMM_R3():rw:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:2i16 MEM0:r:vv:2u16:TXT=BCASTSTR
IFORM:       VPDPWSUD_XMMi32_MASKmskw_XMM2i16_MEM2u16_AVX512
}


# EMITTING VPDPWSUD (VPDPWSUD-256-1)
{
ICLASS:      VPDPWSUD
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_VNNI_INT16_256
EXCEPTIONS:  AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX 
PATTERN:     EVV 0xD2 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn] W0 VL256
OPERANDS:    REG0=YMM_R3():rw:qq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:2i16 REG3=YMM_B3():r:qq:2u16
IFORM:       VPDPWSUD_YMMi32_MASKmskw_YMM2i16_YMM2u16_AVX512
}

{
ICLASS:      VPDPWSUD
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_VNNI_INT16_256
EXCEPTIONS:  AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION 
PATTERN:     EVV 0xD2 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UBIT=1 W0 VL256 ESIZE_32_BITS() NELEM_FULL()
OPERANDS:    REG0=YMM_R3():rw:qq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:2i16 MEM0:r:vv:2u16:TXT=BCASTSTR
IFORM:       VPDPWSUD_YMMi32_MASKmskw_YMM2i16_MEM2u16_AVX512
}


# EMITTING VPDPWSUD (VPDPWSUD-512-1)
{
ICLASS:      VPDPWSUD
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_VNNI_INT16_512
EXCEPTIONS:  AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX 
PATTERN:     EVV 0xD2 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn] W0 VL512
OPERANDS:    REG0=ZMM_R3():rw:zi32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:z2i16 REG3=ZMM_B3():r:z2u16
IFORM:       VPDPWSUD_ZMMi32_MASKmskw_ZMM2i16_ZMM2u16_AVX512
}

{
ICLASS:      VPDPWSUD
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_VNNI_INT16_512
EXCEPTIONS:  AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION 
PATTERN:     EVV 0xD2 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UBIT=1 W0 VL512 ESIZE_32_BITS() NELEM_FULL()
OPERANDS:    REG0=ZMM_R3():rw:zi32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:z2i16 MEM0:r:vv:2u16:TXT=BCASTSTR
IFORM:       VPDPWSUD_ZMMi32_MASKmskw_ZMM2i16_MEM2u16_AVX512
}


# EMITTING VPDPWSUDS (VPDPWSUDS-128-1)
{
ICLASS:      VPDPWSUDS
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_VNNI_INT16_128
EXCEPTIONS:  AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX 
PATTERN:     EVV 0xD3 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn] W0 VL128
OPERANDS:    REG0=XMM_R3():rw:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:2i16 REG3=XMM_B3():r:dq:2u16
IFORM:       VPDPWSUDS_XMMi32_MASKmskw_XMM2i16_XMM2u16_AVX512
}

{
ICLASS:      VPDPWSUDS
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_VNNI_INT16_128
EXCEPTIONS:  AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION 
PATTERN:     EVV 0xD3 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UBIT=1 W0 VL128 ESIZE_32_BITS() NELEM_FULL()
OPERANDS:    REG0=XMM_R3():rw:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:2i16 MEM0:r:vv:2u16:TXT=BCASTSTR
IFORM:       VPDPWSUDS_XMMi32_MASKmskw_XMM2i16_MEM2u16_AVX512
}


# EMITTING VPDPWSUDS (VPDPWSUDS-256-1)
{
ICLASS:      VPDPWSUDS
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_VNNI_INT16_256
EXCEPTIONS:  AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX 
PATTERN:     EVV 0xD3 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn] W0 VL256
OPERANDS:    REG0=YMM_R3():rw:qq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:2i16 REG3=YMM_B3():r:qq:2u16
IFORM:       VPDPWSUDS_YMMi32_MASKmskw_YMM2i16_YMM2u16_AVX512
}

{
ICLASS:      VPDPWSUDS
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_VNNI_INT16_256
EXCEPTIONS:  AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION 
PATTERN:     EVV 0xD3 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UBIT=1 W0 VL256 ESIZE_32_BITS() NELEM_FULL()
OPERANDS:    REG0=YMM_R3():rw:qq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:2i16 MEM0:r:vv:2u16:TXT=BCASTSTR
IFORM:       VPDPWSUDS_YMMi32_MASKmskw_YMM2i16_MEM2u16_AVX512
}


# EMITTING VPDPWSUDS (VPDPWSUDS-512-1)
{
ICLASS:      VPDPWSUDS
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_VNNI_INT16_512
EXCEPTIONS:  AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX 
PATTERN:     EVV 0xD3 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn] W0 VL512
OPERANDS:    REG0=ZMM_R3():rw:zi32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:z2i16 REG3=ZMM_B3():r:z2u16
IFORM:       VPDPWSUDS_ZMMi32_MASKmskw_ZMM2i16_ZMM2u16_AVX512
}

{
ICLASS:      VPDPWSUDS
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_VNNI_INT16_512
EXCEPTIONS:  AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION 
PATTERN:     EVV 0xD3 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UBIT=1 W0 VL512 ESIZE_32_BITS() NELEM_FULL()
OPERANDS:    REG0=ZMM_R3():rw:zi32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:z2i16 MEM0:r:vv:2u16:TXT=BCASTSTR
IFORM:       VPDPWSUDS_ZMMi32_MASKmskw_ZMM2i16_MEM2u16_AVX512
}


# EMITTING VPDPWUSD (VPDPWUSD-128-1)
{
ICLASS:      VPDPWUSD
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_VNNI_INT16_128
EXCEPTIONS:  AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX 
PATTERN:     EVV 0xD2 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn] W0 VL128
OPERANDS:    REG0=XMM_R3():rw:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:2u16 REG3=XMM_B3():r:dq:2i16
IFORM:       VPDPWUSD_XMMi32_MASKmskw_XMM2u16_XMM2i16_AVX512
}

{
ICLASS:      VPDPWUSD
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_VNNI_INT16_128
EXCEPTIONS:  AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION 
PATTERN:     EVV 0xD2 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UBIT=1 W0 VL128 ESIZE_32_BITS() NELEM_FULL()
OPERANDS:    REG0=XMM_R3():rw:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:2u16 MEM0:r:vv:2i16:TXT=BCASTSTR
IFORM:       VPDPWUSD_XMMi32_MASKmskw_XMM2u16_MEM2i16_AVX512
}


# EMITTING VPDPWUSD (VPDPWUSD-256-1)
{
ICLASS:      VPDPWUSD
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_VNNI_INT16_256
EXCEPTIONS:  AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX 
PATTERN:     EVV 0xD2 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn] W0 VL256
OPERANDS:    REG0=YMM_R3():rw:qq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:2u16 REG3=YMM_B3():r:qq:2i16
IFORM:       VPDPWUSD_YMMi32_MASKmskw_YMM2u16_YMM2i16_AVX512
}

{
ICLASS:      VPDPWUSD
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_VNNI_INT16_256
EXCEPTIONS:  AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION 
PATTERN:     EVV 0xD2 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UBIT=1 W0 VL256 ESIZE_32_BITS() NELEM_FULL()
OPERANDS:    REG0=YMM_R3():rw:qq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:2u16 MEM0:r:vv:2i16:TXT=BCASTSTR
IFORM:       VPDPWUSD_YMMi32_MASKmskw_YMM2u16_MEM2i16_AVX512
}


# EMITTING VPDPWUSD (VPDPWUSD-512-1)
{
ICLASS:      VPDPWUSD
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_VNNI_INT16_512
EXCEPTIONS:  AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX 
PATTERN:     EVV 0xD2 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn] W0 VL512
OPERANDS:    REG0=ZMM_R3():rw:zi32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:z2u16 REG3=ZMM_B3():r:z2i16
IFORM:       VPDPWUSD_ZMMi32_MASKmskw_ZMM2u16_ZMM2i16_AVX512
}

{
ICLASS:      VPDPWUSD
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_VNNI_INT16_512
EXCEPTIONS:  AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION 
PATTERN:     EVV 0xD2 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UBIT=1 W0 VL512 ESIZE_32_BITS() NELEM_FULL()
OPERANDS:    REG0=ZMM_R3():rw:zi32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:z2u16 MEM0:r:vv:2i16:TXT=BCASTSTR
IFORM:       VPDPWUSD_ZMMi32_MASKmskw_ZMM2u16_MEM2i16_AVX512
}


# EMITTING VPDPWUSDS (VPDPWUSDS-128-1)
{
ICLASS:      VPDPWUSDS
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_VNNI_INT16_128
EXCEPTIONS:  AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX 
PATTERN:     EVV 0xD3 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn] W0 VL128
OPERANDS:    REG0=XMM_R3():rw:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:2u16 REG3=XMM_B3():r:dq:2i16
IFORM:       VPDPWUSDS_XMMi32_MASKmskw_XMM2u16_XMM2i16_AVX512
}

{
ICLASS:      VPDPWUSDS
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_VNNI_INT16_128
EXCEPTIONS:  AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION 
PATTERN:     EVV 0xD3 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UBIT=1 W0 VL128 ESIZE_32_BITS() NELEM_FULL()
OPERANDS:    REG0=XMM_R3():rw:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:2u16 MEM0:r:vv:2i16:TXT=BCASTSTR
IFORM:       VPDPWUSDS_XMMi32_MASKmskw_XMM2u16_MEM2i16_AVX512
}


# EMITTING VPDPWUSDS (VPDPWUSDS-256-1)
{
ICLASS:      VPDPWUSDS
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_VNNI_INT16_256
EXCEPTIONS:  AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX 
PATTERN:     EVV 0xD3 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn] W0 VL256
OPERANDS:    REG0=YMM_R3():rw:qq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:2u16 REG3=YMM_B3():r:qq:2i16
IFORM:       VPDPWUSDS_YMMi32_MASKmskw_YMM2u16_YMM2i16_AVX512
}

{
ICLASS:      VPDPWUSDS
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_VNNI_INT16_256
EXCEPTIONS:  AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION 
PATTERN:     EVV 0xD3 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UBIT=1 W0 VL256 ESIZE_32_BITS() NELEM_FULL()
OPERANDS:    REG0=YMM_R3():rw:qq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:2u16 MEM0:r:vv:2i16:TXT=BCASTSTR
IFORM:       VPDPWUSDS_YMMi32_MASKmskw_YMM2u16_MEM2i16_AVX512
}


# EMITTING VPDPWUSDS (VPDPWUSDS-512-1)
{
ICLASS:      VPDPWUSDS
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_VNNI_INT16_512
EXCEPTIONS:  AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX 
PATTERN:     EVV 0xD3 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn] W0 VL512
OPERANDS:    REG0=ZMM_R3():rw:zi32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:z2u16 REG3=ZMM_B3():r:z2i16
IFORM:       VPDPWUSDS_ZMMi32_MASKmskw_ZMM2u16_ZMM2i16_AVX512
}

{
ICLASS:      VPDPWUSDS
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_VNNI_INT16_512
EXCEPTIONS:  AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION 
PATTERN:     EVV 0xD3 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UBIT=1 W0 VL512 ESIZE_32_BITS() NELEM_FULL()
OPERANDS:    REG0=ZMM_R3():rw:zi32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:z2u16 MEM0:r:vv:2i16:TXT=BCASTSTR
IFORM:       VPDPWUSDS_ZMMi32_MASKmskw_ZMM2u16_MEM2i16_AVX512
}


# EMITTING VPDPWUUD (VPDPWUUD-128-1)
{
ICLASS:      VPDPWUUD
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_VNNI_INT16_128
EXCEPTIONS:  AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX 
PATTERN:     EVV 0xD2 VNP V0F38 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn] W0 VL128
OPERANDS:    REG0=XMM_R3():rw:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:2u16 REG3=XMM_B3():r:dq:2u16
IFORM:       VPDPWUUD_XMMu32_MASKmskw_XMM2u16_XMM2u16_AVX512
}

{
ICLASS:      VPDPWUUD
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_VNNI_INT16_128
EXCEPTIONS:  AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION 
PATTERN:     EVV 0xD2 VNP V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UBIT=1 W0 VL128 ESIZE_32_BITS() NELEM_FULL()
OPERANDS:    REG0=XMM_R3():rw:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:2u16 MEM0:r:vv:2u16:TXT=BCASTSTR
IFORM:       VPDPWUUD_XMMu32_MASKmskw_XMM2u16_MEM2u16_AVX512
}


# EMITTING VPDPWUUD (VPDPWUUD-256-1)
{
ICLASS:      VPDPWUUD
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_VNNI_INT16_256
EXCEPTIONS:  AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX 
PATTERN:     EVV 0xD2 VNP V0F38 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn] W0 VL256
OPERANDS:    REG0=YMM_R3():rw:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:2u16 REG3=YMM_B3():r:qq:2u16
IFORM:       VPDPWUUD_YMMu32_MASKmskw_YMM2u16_YMM2u16_AVX512
}

{
ICLASS:      VPDPWUUD
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_VNNI_INT16_256
EXCEPTIONS:  AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION 
PATTERN:     EVV 0xD2 VNP V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UBIT=1 W0 VL256 ESIZE_32_BITS() NELEM_FULL()
OPERANDS:    REG0=YMM_R3():rw:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:2u16 MEM0:r:vv:2u16:TXT=BCASTSTR
IFORM:       VPDPWUUD_YMMu32_MASKmskw_YMM2u16_MEM2u16_AVX512
}


# EMITTING VPDPWUUD (VPDPWUUD-512-1)
{
ICLASS:      VPDPWUUD
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_VNNI_INT16_512
EXCEPTIONS:  AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX 
PATTERN:     EVV 0xD2 VNP V0F38 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn] W0 VL512
OPERANDS:    REG0=ZMM_R3():rw:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:z2u16 REG3=ZMM_B3():r:z2u16
IFORM:       VPDPWUUD_ZMMu32_MASKmskw_ZMM2u16_ZMM2u16_AVX512
}

{
ICLASS:      VPDPWUUD
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_VNNI_INT16_512
EXCEPTIONS:  AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION 
PATTERN:     EVV 0xD2 VNP V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UBIT=1 W0 VL512 ESIZE_32_BITS() NELEM_FULL()
OPERANDS:    REG0=ZMM_R3():rw:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:z2u16 MEM0:r:vv:2u16:TXT=BCASTSTR
IFORM:       VPDPWUUD_ZMMu32_MASKmskw_ZMM2u16_MEM2u16_AVX512
}


# EMITTING VPDPWUUDS (VPDPWUUDS-128-1)
{
ICLASS:      VPDPWUUDS
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_VNNI_INT16_128
EXCEPTIONS:  AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX 
PATTERN:     EVV 0xD3 VNP V0F38 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn] W0 VL128
OPERANDS:    REG0=XMM_R3():rw:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:2u16 REG3=XMM_B3():r:dq:2u16
IFORM:       VPDPWUUDS_XMMu32_MASKmskw_XMM2u16_XMM2u16_AVX512
}

{
ICLASS:      VPDPWUUDS
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_VNNI_INT16_128
EXCEPTIONS:  AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION 
PATTERN:     EVV 0xD3 VNP V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UBIT=1 W0 VL128 ESIZE_32_BITS() NELEM_FULL()
OPERANDS:    REG0=XMM_R3():rw:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:2u16 MEM0:r:vv:2u16:TXT=BCASTSTR
IFORM:       VPDPWUUDS_XMMu32_MASKmskw_XMM2u16_MEM2u16_AVX512
}


# EMITTING VPDPWUUDS (VPDPWUUDS-256-1)
{
ICLASS:      VPDPWUUDS
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_VNNI_INT16_256
EXCEPTIONS:  AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX 
PATTERN:     EVV 0xD3 VNP V0F38 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn] W0 VL256
OPERANDS:    REG0=YMM_R3():rw:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:2u16 REG3=YMM_B3():r:qq:2u16
IFORM:       VPDPWUUDS_YMMu32_MASKmskw_YMM2u16_YMM2u16_AVX512
}

{
ICLASS:      VPDPWUUDS
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_VNNI_INT16_256
EXCEPTIONS:  AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION 
PATTERN:     EVV 0xD3 VNP V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UBIT=1 W0 VL256 ESIZE_32_BITS() NELEM_FULL()
OPERANDS:    REG0=YMM_R3():rw:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:2u16 MEM0:r:vv:2u16:TXT=BCASTSTR
IFORM:       VPDPWUUDS_YMMu32_MASKmskw_YMM2u16_MEM2u16_AVX512
}


# EMITTING VPDPWUUDS (VPDPWUUDS-512-1)
{
ICLASS:      VPDPWUUDS
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_VNNI_INT16_512
EXCEPTIONS:  AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX 
PATTERN:     EVV 0xD3 VNP V0F38 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn] W0 VL512
OPERANDS:    REG0=ZMM_R3():rw:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:z2u16 REG3=ZMM_B3():r:z2u16
IFORM:       VPDPWUUDS_ZMMu32_MASKmskw_ZMM2u16_ZMM2u16_AVX512
}

{
ICLASS:      VPDPWUUDS
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_VNNI_INT16_512
EXCEPTIONS:  AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION 
PATTERN:     EVV 0xD3 VNP V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UBIT=1 W0 VL512 ESIZE_32_BITS() NELEM_FULL()
OPERANDS:    REG0=ZMM_R3():rw:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:z2u16 MEM0:r:vv:2u16:TXT=BCASTSTR
IFORM:       VPDPWUUDS_ZMMu32_MASKmskw_ZMM2u16_MEM2u16_AVX512
}


