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#Copyright (c) 2022 Intel Corporation
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xed_reg_enum_t XMM_R3()::
mode16 | OUTREG=XMM_R3_32()
mode32 | OUTREG=XMM_R3_32()
mode64 | OUTREG=XMM_R3_64()

xed_reg_enum_t XMM_R3_32()::
REG=0 | OUTREG=XED_REG_XMM0
REG=1 | OUTREG=XED_REG_XMM1
REG=2 | OUTREG=XED_REG_XMM2
REG=3 | OUTREG=XED_REG_XMM3
REG=4 | OUTREG=XED_REG_XMM4
REG=5 | OUTREG=XED_REG_XMM5
REG=6 | OUTREG=XED_REG_XMM6
REG=7 | OUTREG=XED_REG_XMM7

xed_reg_enum_t XMM_R3_64()::
REXR4=0 REXR=0 REG=0 | OUTREG=XED_REG_XMM0
REXR4=0 REXR=0 REG=1 | OUTREG=XED_REG_XMM1
REXR4=0 REXR=0 REG=2 | OUTREG=XED_REG_XMM2
REXR4=0 REXR=0 REG=3 | OUTREG=XED_REG_XMM3
REXR4=0 REXR=0 REG=4 | OUTREG=XED_REG_XMM4
REXR4=0 REXR=0 REG=5 | OUTREG=XED_REG_XMM5
REXR4=0 REXR=0 REG=6 | OUTREG=XED_REG_XMM6
REXR4=0 REXR=0 REG=7 | OUTREG=XED_REG_XMM7

REXR4=0 REXR=1 REG=0 | OUTREG=XED_REG_XMM8
REXR4=0 REXR=1 REG=1 | OUTREG=XED_REG_XMM9
REXR4=0 REXR=1 REG=2 | OUTREG=XED_REG_XMM10
REXR4=0 REXR=1 REG=3 | OUTREG=XED_REG_XMM11
REXR4=0 REXR=1 REG=4 | OUTREG=XED_REG_XMM12
REXR4=0 REXR=1 REG=5 | OUTREG=XED_REG_XMM13
REXR4=0 REXR=1 REG=6 | OUTREG=XED_REG_XMM14
REXR4=0 REXR=1 REG=7 | OUTREG=XED_REG_XMM15

REXR4=1 REXR=0 REG=0 | OUTREG=XED_REG_XMM16
REXR4=1 REXR=0 REG=1 | OUTREG=XED_REG_XMM17
REXR4=1 REXR=0 REG=2 | OUTREG=XED_REG_XMM18
REXR4=1 REXR=0 REG=3 | OUTREG=XED_REG_XMM19
REXR4=1 REXR=0 REG=4 | OUTREG=XED_REG_XMM20
REXR4=1 REXR=0 REG=5 | OUTREG=XED_REG_XMM21
REXR4=1 REXR=0 REG=6 | OUTREG=XED_REG_XMM22
REXR4=1 REXR=0 REG=7 | OUTREG=XED_REG_XMM23
REXR4=1 REXR=1 REG=0 | OUTREG=XED_REG_XMM24
REXR4=1 REXR=1 REG=1 | OUTREG=XED_REG_XMM25
REXR4=1 REXR=1 REG=2 | OUTREG=XED_REG_XMM26
REXR4=1 REXR=1 REG=3 | OUTREG=XED_REG_XMM27
REXR4=1 REXR=1 REG=4 | OUTREG=XED_REG_XMM28
REXR4=1 REXR=1 REG=5 | OUTREG=XED_REG_XMM29
REXR4=1 REXR=1 REG=6 | OUTREG=XED_REG_XMM30
REXR4=1 REXR=1 REG=7 | OUTREG=XED_REG_XMM31


xed_reg_enum_t YMM_R3()::
mode16 | OUTREG=YMM_R3_32()
mode32 | OUTREG=YMM_R3_32()
mode64 | OUTREG=YMM_R3_64()

xed_reg_enum_t YMM_R3_32()::
REG=0 | OUTREG=XED_REG_YMM0
REG=1 | OUTREG=XED_REG_YMM1
REG=2 | OUTREG=XED_REG_YMM2
REG=3 | OUTREG=XED_REG_YMM3
REG=4 | OUTREG=XED_REG_YMM4
REG=5 | OUTREG=XED_REG_YMM5
REG=6 | OUTREG=XED_REG_YMM6
REG=7 | OUTREG=XED_REG_YMM7
xed_reg_enum_t YMM_R3_64()::
REXR4=0 REXR=0 REG=0 | OUTREG=XED_REG_YMM0
REXR4=0 REXR=0 REG=1 | OUTREG=XED_REG_YMM1
REXR4=0 REXR=0 REG=2 | OUTREG=XED_REG_YMM2
REXR4=0 REXR=0 REG=3 | OUTREG=XED_REG_YMM3
REXR4=0 REXR=0 REG=4 | OUTREG=XED_REG_YMM4
REXR4=0 REXR=0 REG=5 | OUTREG=XED_REG_YMM5
REXR4=0 REXR=0 REG=6 | OUTREG=XED_REG_YMM6
REXR4=0 REXR=0 REG=7 | OUTREG=XED_REG_YMM7
REXR4=0 REXR=1 REG=0 | OUTREG=XED_REG_YMM8
REXR4=0 REXR=1 REG=1 | OUTREG=XED_REG_YMM9
REXR4=0 REXR=1 REG=2 | OUTREG=XED_REG_YMM10
REXR4=0 REXR=1 REG=3 | OUTREG=XED_REG_YMM11
REXR4=0 REXR=1 REG=4 | OUTREG=XED_REG_YMM12
REXR4=0 REXR=1 REG=5 | OUTREG=XED_REG_YMM13
REXR4=0 REXR=1 REG=6 | OUTREG=XED_REG_YMM14
REXR4=0 REXR=1 REG=7 | OUTREG=XED_REG_YMM15

REXR4=1 REXR=0 REG=0 | OUTREG=XED_REG_YMM16
REXR4=1 REXR=0 REG=1 | OUTREG=XED_REG_YMM17
REXR4=1 REXR=0 REG=2 | OUTREG=XED_REG_YMM18
REXR4=1 REXR=0 REG=3 | OUTREG=XED_REG_YMM19
REXR4=1 REXR=0 REG=4 | OUTREG=XED_REG_YMM20
REXR4=1 REXR=0 REG=5 | OUTREG=XED_REG_YMM21
REXR4=1 REXR=0 REG=6 | OUTREG=XED_REG_YMM22
REXR4=1 REXR=0 REG=7 | OUTREG=XED_REG_YMM23
REXR4=1 REXR=1 REG=0 | OUTREG=XED_REG_YMM24
REXR4=1 REXR=1 REG=1 | OUTREG=XED_REG_YMM25
REXR4=1 REXR=1 REG=2 | OUTREG=XED_REG_YMM26
REXR4=1 REXR=1 REG=3 | OUTREG=XED_REG_YMM27
REXR4=1 REXR=1 REG=4 | OUTREG=XED_REG_YMM28
REXR4=1 REXR=1 REG=5 | OUTREG=XED_REG_YMM29
REXR4=1 REXR=1 REG=6 | OUTREG=XED_REG_YMM30
REXR4=1 REXR=1 REG=7 | OUTREG=XED_REG_YMM31



xed_reg_enum_t ZMM_R3()::
mode16 | OUTREG=ZMM_R3_32()
mode32 | OUTREG=ZMM_R3_32()
mode64 | OUTREG=ZMM_R3_64()

xed_reg_enum_t ZMM_R3_32()::
REG=0 | OUTREG=XED_REG_ZMM0
REG=1 | OUTREG=XED_REG_ZMM1
REG=2 | OUTREG=XED_REG_ZMM2
REG=3 | OUTREG=XED_REG_ZMM3
REG=4 | OUTREG=XED_REG_ZMM4
REG=5 | OUTREG=XED_REG_ZMM5
REG=6 | OUTREG=XED_REG_ZMM6
REG=7 | OUTREG=XED_REG_ZMM7

xed_reg_enum_t ZMM_R3_64()::
REXR4=0 REXR=0 REG=0 | OUTREG=XED_REG_ZMM0
REXR4=0 REXR=0 REG=1 | OUTREG=XED_REG_ZMM1
REXR4=0 REXR=0 REG=2 | OUTREG=XED_REG_ZMM2
REXR4=0 REXR=0 REG=3 | OUTREG=XED_REG_ZMM3
REXR4=0 REXR=0 REG=4 | OUTREG=XED_REG_ZMM4
REXR4=0 REXR=0 REG=5 | OUTREG=XED_REG_ZMM5
REXR4=0 REXR=0 REG=6 | OUTREG=XED_REG_ZMM6
REXR4=0 REXR=0 REG=7 | OUTREG=XED_REG_ZMM7
REXR4=0 REXR=1 REG=0 | OUTREG=XED_REG_ZMM8
REXR4=0 REXR=1 REG=1 | OUTREG=XED_REG_ZMM9
REXR4=0 REXR=1 REG=2 | OUTREG=XED_REG_ZMM10
REXR4=0 REXR=1 REG=3 | OUTREG=XED_REG_ZMM11
REXR4=0 REXR=1 REG=4 | OUTREG=XED_REG_ZMM12
REXR4=0 REXR=1 REG=5 | OUTREG=XED_REG_ZMM13
REXR4=0 REXR=1 REG=6 | OUTREG=XED_REG_ZMM14
REXR4=0 REXR=1 REG=7 | OUTREG=XED_REG_ZMM15

REXR4=1 REXR=0 REG=0 | OUTREG=XED_REG_ZMM16
REXR4=1 REXR=0 REG=1 | OUTREG=XED_REG_ZMM17
REXR4=1 REXR=0 REG=2 | OUTREG=XED_REG_ZMM18
REXR4=1 REXR=0 REG=3 | OUTREG=XED_REG_ZMM19
REXR4=1 REXR=0 REG=4 | OUTREG=XED_REG_ZMM20
REXR4=1 REXR=0 REG=5 | OUTREG=XED_REG_ZMM21
REXR4=1 REXR=0 REG=6 | OUTREG=XED_REG_ZMM22
REXR4=1 REXR=0 REG=7 | OUTREG=XED_REG_ZMM23
REXR4=1 REXR=1 REG=0 | OUTREG=XED_REG_ZMM24
REXR4=1 REXR=1 REG=1 | OUTREG=XED_REG_ZMM25
REXR4=1 REXR=1 REG=2 | OUTREG=XED_REG_ZMM26
REXR4=1 REXR=1 REG=3 | OUTREG=XED_REG_ZMM27
REXR4=1 REXR=1 REG=4 | OUTREG=XED_REG_ZMM28
REXR4=1 REXR=1 REG=5 | OUTREG=XED_REG_ZMM29
REXR4=1 REXR=1 REG=6 | OUTREG=XED_REG_ZMM30
REXR4=1 REXR=1 REG=7 | OUTREG=XED_REG_ZMM31

