_8( C&firefly,roc-rk3328-ccrockchip,rk3328 +7Firefly roc-rk3328-ccaliases=/serial@ff110000E/serial@ff120000M/serial@ff130000U/i2c@ff150000Z/i2c@ff160000_/i2c@ff170000d/i2c@ff180000i/ethernet@ff540000s/ethernet@ff550000cpus+cpu@0}cpuarm,cortex-a53xpsci cpu@1}cpuarm,cortex-a53xpsci cpu@2}cpuarm,cortex-a53xpsci cpu@3}cpuarm,cortex-a53xpsci idle-statespscicpu-sleeparm,idle-state 1HxYi l2-cache0cache opp_table0operating-points-v2z opp-408000000Q~@opp-600000000#F~@opp-8160000000,B@@opp-1008000000<@opp-1200000000G(@opp-1296000000M?d @bus simple-bus+dmac@ff1f0000arm,pl330arm,primecell@ apb_pclk analog-soundsimple-audio-cardi2s*Analog Adisabledsimple-audio-card,cpuHsimple-audio-card,codecHarm-pmuarm,cortex-a53-pmu0defgR display-subsystemrockchip,display-subsysteme hdmi-soundsimple-audio-cardi2s*HDMI Adisabledsimple-audio-card,cpuHsimple-audio-card,codecHpsciarm,psci-1.0arm,psci-0.2smctimerarm,armv8-timer0   xin24m fixed-clockkxn6xin24m Di2s@ff000000(rockchip,rk3328-i2srockchip,rk3066-i2s )7i2s_clki2s_hclk  txrx Adisabled i2s@ff010000(rockchip,rk3328-i2srockchip,rk3066-i2s *8i2s_clki2s_hclktxrx Adisabled i2s@ff020000(rockchip,rk3328-i2srockchip,rk3066-i2s +9i2s_clki2s_hclktxrx Adisabledspdif@ff030000rockchip,rk3328-spdif .: mclkhclk txdefault Adisabledpdm@ff040000 rockchip,pdm=Rpdm_clkpdm_hclkrxdefaultsleep Adisabledsyscon@ff100000&rockchip,rk3328-grfsysconsimple-mfd :io-domains"rockchip,rk3328-io-voltage-domainAokay#1grf-gpiorockchip,rk3328-grf-gpio>N dpower-controller!rockchip,rk3328-power-controllerZ+ <pd_hevc@6pd_video@5pd_vpu@8Freboot-modesyscon-reboot-modenuRBRBRB RBserial@ff110000&rockchip,rk3328-uartsnps,dw-apb-uart 7&baudclkapb_pclktxrxdefault  !" Adisabledserial@ff120000&rockchip,rk3328-uartsnps,dw-apb-uart 8'baudclkapb_pclktxrxdefault #$% Adisabledserial@ff130000&rockchip,rk3328-uartsnps,dw-apb-uart 9(baudclkapb_pclktxrxdefault&Aokayi2c@ff150000(rockchip,rk3328-i2crockchip,rk3399-i2c $+7 i2cpclkdefault' Adisabledi2c@ff160000(rockchip,rk3328-i2crockchip,rk3399-i2c %+8 i2cpclkdefault(Aokaypmic@18rockchip,rk805 )kxin32krk805-clkout2>Ndefault*++ ++!- gregulatorsDCDC_REG1 9vdd_logicH 4` xregulator-state-memB@DCDC_REG29vdd_armH 4` x regulator-state-mem~DCDC_REG39vcc_ddrxregulator-state-memDCDC_REG49vcc_ioH2Z`2Zx regulator-state-mem2ZLDO_REG19vcc_18Hw@`w@x regulator-state-memw@LDO_REG2 9vcc18_emmcHw@`w@x regulator-state-memw@LDO_REG39vdd_10HB@`B@xregulator-state-memB@i2c@ff170000(rockchip,rk3328-i2crockchip,rk3399-i2c &+9 i2cpclkdefault, Adisabledi2c@ff180000(rockchip,rk3328-i2crockchip,rk3399-i2c '+: i2cpclkdefault- Adisabledspi@ff190000(rockchip,rk3328-spirockchip,rk3066-spi 1+ spiclkapb_pclk txrxdefault./01 Adisabledwatchdog@ff1a0000 snps,dw-wdt (pwm@ff1b0000rockchip,rk3328-pwm< pwmpclkdefault2 Adisabledpwm@ff1b0010rockchip,rk3328-pwm< pwmpclkdefault3 Adisabledpwm@ff1b0020rockchip,rk3328-pwm < pwmpclkdefault4 Adisabledpwm@ff1b0030rockchip,rk3328-pwm0 2< pwmpclkdefault5 Adisabledthermal-zonessoc-thermal6tripstrip-point0#p/passivetrip-point1#L/passive 7soc-crit#s/ criticalcooling-mapsmap0:70? Ntsadc@ff250000rockchip,rk3328-tsadc% :[$kP$tsadcapb_pclkinitdefaultsleep898B tsadc-apb:Aokay 6efuse@ff260000rockchip,rk3328-efuse&P+> pclk_efuse id@7cpu-leakage@17logic-leakage@19cpu-version@1a Eadc@ff280000.rockchip,rk3328-saradcrockchip,rk3399-saradc( P%saradcapb_pclkV saradc-apb Adisabledgpu@ff300000"rockchip,rk3328-maliarm,mali-4500TZW]XY[\"gpgpmmupppp0ppmmu0pp1ppmmu1 buscorefiommu@ff330200rockchip,iommu3 ` h265e_mmu aclkiface Adisablediommu@ff340800rockchip,iommu4@ b vepu_mmuF aclkiface Adisabledvideo-codec@ff350000rockchip,rk3328-vpu5  vdpuF aclkhclk;&<iommu@ff350800rockchip,iommu5@  vpu_mmuF aclkiface&< ;iommu@ff360480rockchip,iommu 6@6@ J rkvdec_mmuB aclkiface Adisabledvop@ff370000rockchip,rk3328-vop7>  x;aclk_vopdclk_vophclk_vop axiahbdclk=Aokayport+ endpoint@04> Ciommu@ff373f00rockchip,iommu7?  vop_mmu; aclkifaceAokay =hdmi@ff3c0000rockchip,rk3328-dw-hdmi<#GFiahbisfrcecD?Ihdmidefault @AB:Aokay portsportendpoint4C >codec@ff410000rockchip,rk3328-codecA* pclkmclk: Adisabled phy@ff430000rockchip,rk3328-hdmi-phyC SDysysclkrefoclkrefpclk hdmi_phykSE _cpu-versionpAokay ?clock-controller@ff440000(rockchip,rk3328-crurockchip,crusysconD:k{[x=&'(ABDC"\5H4$zDDD|kn6n6n6n6#FLGрxhxhрxhxh syscon@ff450000.rockchip,rk3328-usb2phy-grfsysconsimple-mfdE+usb2-phy@100rockchip,rk3328-usb2phyDphyclk usb480m_phyk[{FAokay Fotg-portp$;<=otg-bvalidotg-idlinestateAokay Uhost-portp > linestateAokay Vmmc@ff5000000rockchip,rk3328-dw-mshcrockchip,rk3288-dw-mshcP@   =!JNbiuciuciu-driveciu-sampleрAokaydefaultGHIJ %K1mmc@ff5100000rockchip,rk3328-dw-mshcrockchip,rk3288-dw-mshcQ@   >"KObiuciuciu-driveciu-sampleр Adisabledmmc@ff5200000rockchip,rk3328-dw-mshcrockchip,rk3288-dw-mshcR@  ?#LPbiuciuciu-driveciu-sampleрAokay>KZdefault LMN%1ethernet@ff540000rockchip,rk3328-gmacT macirq8dWXZYMstmmacethmac_clk_rxmac_clk_txclk_mac_refclk_mac_refoutaclk_macpclk_macc stmmaceth:hAokay[dfOOsinputPrgmiidefaultQ ) 'P$ethernet@ff550000rockchip,rk3328-gmacU: macirq8TSSUVIstmmacethmac_clk_rxmac_clk_txclk_mac_refaclk_macpclk_macclk_macphybdstmmacethmac-phyrmiiRh Adisabledmdiosnps,dwmac-mdio+ethernet-phy@04ethernet-phy-id1234.d400ethernet-phy-ieee802.3-c22VddefaultST Rusb@ff5800002rockchip,rk3328-usbrockchip,rk3066-usbsnps,dwc2X Motghost,;@ DU Iusb2-phyAokayusb@ff5c0000 generic-ehci\  NFDVIusbAokayusb@ff5d0000 generic-ohci]  NFDVIusbAokayinterrupt-controller@ff811000 arm,gic-400J[@ @ `    pinctrlrockchip,rk3328-pinctrl:+gpio0@ff210000rockchip,gpio-bank! 3>N[J bgpio1@ff220000rockchip,gpio-bank" 4>N[J )gpio2@ff230000rockchip,gpio-bank# 5>N[Jgpio3@ff240000rockchip,gpio-bank$ 6>N[Jpcfg-pull-upp Ypcfg-pull-down} apcfg-pull-none Wpcfg-pull-none-2ma `pcfg-pull-up-2mappcfg-pull-up-4map Zpcfg-pull-none-4ma ]pcfg-pull-down-4ma}pcfg-pull-none-8ma [pcfg-pull-up-8map \pcfg-pull-none-12ma  ^pcfg-pull-up-12map  _pcfg-output-highpcfg-output-lowpcfg-input-highp Xpcfg-inputi2c0i2c0-xfer WW 'i2c1i2c1-xfer WW (i2c2i2c2-xfer  WW ,i2c3i2c3-xfer WW -i2c3-pins WWhdmi_i2chdmii2c-xfer WW Apdm-0pdmm0-clkW pdmm0-fsyncWpdmm0-sdi0W pdmm0-sdi1W pdmm0-sdi2W pdmm0-sdi3W pdmm0-clk-sleepX pdmm0-sdi0-sleepX pdmm0-sdi1-sleepX pdmm0-sdi2-sleepX pdmm0-sdi3-sleepX pdmm0-fsync-sleepXtsadcotp-pin W 8otp-out W 9uart0uart0-xfer  WY uart0-cts W !uart0-rts W "uart0-rts-pin Wuart1uart1-xfer WY #uart1-ctsW $uart1-rtsW %uart1-rts-pinWuart2-0uart2m0-xfer WYuart2-1uart2m1-xfer WY &spi0-0spi0m0-clkYspi0m0-cs0 Yspi0m0-tx Yspi0m0-rx Yspi0m0-cs1 Yspi0-1spi0m1-clkYspi0m1-cs0Yspi0m1-txYspi0m1-rxYspi0m1-cs1Yspi0-2spi0m2-clkY .spi0m2-cs0Y 1spi0m2-txY /spi0m2-rxY 0i2s1i2s1-mclkWi2s1-sclkWi2s1-lrckrxWi2s1-lrcktxWi2s1-sdiWi2s1-sdoWi2s1-sdio1Wi2s1-sdio2Wi2s1-sdio3Wi2s1-sleepXXXXXXXXXi2s2-0i2s2m0-mclkWi2s2m0-sclkWi2s2m0-lrckrxWi2s2m0-lrcktxWi2s2m0-sdiWi2s2m0-sdoWi2s2m0-sleep`XXXXXXi2s2-1i2s2m1-mclkWi2s2m1-sclkWi2sm1-lrckrxWi2s2m1-lrcktxWi2s2m1-sdiWi2s2m1-sdoWi2s2m1-sleepPXXXXXspdif-0spdifm0-txWspdif-1spdifm1-txWspdif-2spdifm2-txW sdmmc0-0sdmmc0m0-pwrenZsdmmc0m0-pinZsdmmc0-1sdmmc0m1-pwrenZsdmmc0m1-pinZ csdmmc0sdmmc0-clk[ Gsdmmc0-cmd\ Hsdmmc0-dectnZ Isdmmc0-wrprtZsdmmc0-bus1\sdmmc0-bus4@\\\\ Jsdmmc0-pinsZZZZZZZZsdmmc0extsdmmc0ext-clk]sdmmc0ext-cmdZsdmmc0ext-wrprtZsdmmc0ext-dectnZsdmmc0ext-bus1Zsdmmc0ext-bus4@ZZZZsdmmc0ext-pinsZZZZZZZZsdmmc1sdmmc1-clk [sdmmc1-cmd \sdmmc1-pwren\sdmmc1-wrprt\sdmmc1-dectn\sdmmc1-bus1\sdmmc1-bus4@\\\\sdmmc1-pins Z ZZZZZZZZemmcemmc-clk^ Lemmc-cmd_ Memmc-pwrenWemmc-rstnoutWemmc-bus1_emmc-bus4@____emmc-bus8________ Npwm0pwm0-pinW 2pwm1pwm1-pinW 3pwm2pwm2-pinW 4pwmirpwmir-pinW 5gmac-1rgmiim1-pins` [ ]][]]] ] ][ []][[[ [][[[[ Qrmiim1-pins`^```` ` `^ ^ W WWWWWgmac2phyfephyled-speed10Wfephyled-duplexWfephyled-rxm1W Sfephyled-txm1Wfephyled-linkm1W Ttsadc_pintsadc-int Wtsadc-pin Whdmi_pinhdmi-cecW @hdmi-hpda Bcif-0dvp-d2d9-m0WWWWW W W WWWWWcif-1dvp-d2d9-m1WWWWWWWWWWWWpmicpmic-int-lY *usb2usb20-host-drvW echosenserial2:1500000n8external-gmac-clock fixed-clockxsY@ gmac_clkink Odc-12vregulator-fixed9dc_12vxH` fsdmmc-regulatorregulator-fixed bdefaultc9vcc_sdH2Z`2Z Ksdmmcio-regulatorregulator-gpio dw@2Z 9vcc_sdiovoltageHw@`2Zx+ vcc-host1-5v-regulatorregulator-fixed  )defaulte 9vcc_host1_5vx+vcc-sysregulator-fixed9vcc_sysxHLK@`LK@f +vcc-phy-regulatorregulator-fixed9vcc_phyx Pleds gpio-ledsled-0 firefly:blue:power heartbeat g 5on#led-1 firefly:yellow:user mmc1 g 5off compatibleinterrupt-parent#address-cells#size-cellsmodelserial0serial1serial2i2c0i2c1i2c2i2c3ethernet0ethernet1device_typeregclocks#cooling-cellscpu-idle-statesdynamic-power-coefficientenable-methodnext-level-cacheoperating-points-v2cpu-supplyphandleentry-methodlocal-timer-stoparm,psci-suspend-paramentry-latency-usexit-latency-usmin-residency-usopp-sharedopp-hzopp-microvoltclock-latency-nsopp-suspendrangesinterruptsarm,pl330-periph-burstclock-names#dma-cellssimple-audio-card,formatsimple-audio-card,mclk-fssimple-audio-card,namestatussound-daiinterrupt-affinityports#clock-cellsclock-frequencyclock-output-namesdmasdma-names#sound-dai-cellspinctrl-namespinctrl-0pinctrl-1vccio1-supplyvccio2-supplyvccio3-supplyvccio4-supplyvccio5-supplyvccio6-supplypmuio-supplygpio-controller#gpio-cells#power-domain-cellsoffsetmode-normalmode-recoverymode-bootloadermode-loaderreg-io-widthreg-shiftrockchip,system-power-controllerwakeup-sourcevcc1-supplyvcc2-supplyvcc3-supplyvcc4-supplyvcc5-supplyvcc6-supplyregulator-nameregulator-min-microvoltregulator-max-microvoltregulator-always-onregulator-boot-onregulator-on-in-suspendregulator-suspend-microvolt#pwm-cellspolling-delay-passivepolling-delaysustainable-powerthermal-sensorstemperaturehysteresistripcooling-devicecontributionassigned-clocksassigned-clock-ratespinctrl-2resetsreset-namesrockchip,grfrockchip,hw-tshut-temp#thermal-sensor-cellsrockchip,efuse-sizebits#io-channel-cellsinterrupt-names#iommu-cellsiommuspower-domainsremote-endpointphysphy-namesnvmem-cellsnvmem-cell-names#phy-cells#reset-cellsassigned-clock-parentsfifo-depthmax-frequencybus-widthcap-mmc-highspeedcap-sd-highspeeddisable-wpsd-uhs-sdr12sd-uhs-sdr25sd-uhs-sdr50sd-uhs-sdr104vmmc-supplyvqmmc-supplymmc-ddr-1_8vmmc-hs200-1_8vnon-removablesnps,txpblclock_in_outphy-supplyphy-modesnps,aalsnps,reset-gpiosnps,reset-active-lowsnps,reset-delays-ussnps,rxpbltx_delayrx_delayphy-handlephy-is-integrateddr_modeg-np-tx-fifo-sizeg-rx-fifo-sizeg-tx-fifo-size#interrupt-cellsinterrupt-controllerbias-pull-upbias-pull-downbias-disabledrive-strengthoutput-highoutput-lowinput-enablerockchip,pinsstdout-pathvin-supplygpiosregulator-typeenable-active-highlabellinux,default-triggerdefault-state