|8u(u$rockchip,rk3308-evbrockchip,rk3308 +7Rockchip RK3308 EVBaliases=/i2c@ff040000B/i2c@ff050000G/i2c@ff060000L/i2c@ff070000Q/serial@ff0a0000Y/serial@ff0b0000a/serial@ff0c0000i/serial@ff0d0000q/serial@ff0e0000y/spi@ff120000~/spi@ff130000/spi@ff140000cpus+cpu@0cpuarm,cortex-a35psciZ cpu@1cpuarm,cortex-a35pscicpu@2cpuarm,cortex-a35psci cpu@3cpuarm,cortex-a35psci idle-statespscicpu-sleeparm,idle-state+<Sxdtl2-cachecachecpu0-opp-tableoperating-points-v2opp-408000000Q ~~r`@opp-600000000#F ~~r`@opp-8160000000, r`@opp-1008000000< **r`@arm-pmuarm,cortex-a35-pmu0STUV external-mac-clock fixed-clock mac_clkinpsci arm,psci-1.0smctimerarm,armv8-timer0   xin24m fixed-clockn6xin24mgrf@ff000000&rockchip,rk3308-grfsysconsimple-mfdKreboot-modesyscon-reboot-modeRB'RB3RB?RBMRB syscon@ff008000.rockchip,rk3308-usb2phy-grfsysconsimple-mfd@+usb2phy@100rockchip,rk3308-usb2phy[k Hphyclk usb480m_phy disabled otg-port$CDEotg-bvalidotg-idlinestate disabled9host-port J linestate disabled:syscon@ff00b000-rockchip,rk3308-detect-grfsysconsimple-mfd+syscon@ff00c000+rockchip,rk3308-core-grfsysconsimple-mfd+i2c@ff040000(rockchip,rk3308-i2crockchip,rk3399-i2c i2cpclk  default + disabledi2c@ff050000(rockchip,rk3308-i2crockchip,rk3399-i2c i2cpclk  default + disabledi2c@ff060000(rockchip,rk3308-i2crockchip,rk3399-i2c i2cpclk  default+ disabledi2c@ff070000(rockchip,rk3308-i2crockchip,rk3399-i2c i2cpclk default+ disabledwatchdog@ff080000 rockchip,rk3308-wdtsnps,dw-wdt   disabledserial@ff0a0000&rockchip,rk3308-uartsnps,dw-apb-uart  baudclkapb_pclkdefault  disabledserial@ff0b0000&rockchip,rk3308-uartsnps,dw-apb-uart  baudclkapb_pclkdefault  disabledserial@ff0c0000&rockchip,rk3308-uartsnps,dw-apb-uart  baudclkapb_pclkdefault disabledserial@ff0d0000&rockchip,rk3308-uartsnps,dw-apb-uart  baudclkapb_pclkdefault disabledserial@ff0e0000&rockchip,rk3308-uartsnps,dw-apb-uart baudclkapb_pclkdefaultokayspi@ff120000(rockchip,rk3308-spirockchip,rk3066-spi +spiclkapb_pclktxrxdefault disabledspi@ff130000(rockchip,rk3308-spirockchip,rk3066-spi +spiclkapb_pclktxrxdefault ! disabledspi@ff140000(rockchip,rk3308-spirockchip,rk3066-spi +spiclkapb_pclk""txrxdefault#$%& disabledpwm@ff160000(rockchip,rk3308-pwmrockchip,rk3328-pwmy pwmpclkdefault' disabledpwm@ff160010(rockchip,rk3308-pwmrockchip,rk3328-pwmy pwmpclkdefault( disabledpwm@ff160020(rockchip,rk3308-pwmrockchip,rk3328-pwm y pwmpclkdefault) disabledpwm@ff160030(rockchip,rk3308-pwmrockchip,rk3328-pwm0y pwmpclkdefault* disabledpwm@ff170000(rockchip,rk3308-pwmrockchip,rk3328-pwmx pwmpclkdefault+ disabledpwm@ff170010(rockchip,rk3308-pwmrockchip,rk3328-pwmx pwmpclkdefault, disabledpwm@ff170020(rockchip,rk3308-pwmrockchip,rk3328-pwm x pwmpclkdefault- disabledpwm@ff170030(rockchip,rk3308-pwmrockchip,rk3328-pwm0x pwmpclkdefault. disabledpwm@ff180000(rockchip,rk3308-pwmrockchip,rk3328-pwm pwmpclkdefault/okay^pwm@ff180010(rockchip,rk3308-pwmrockchip,rk3328-pwm pwmpclkdefault0 disabledpwm@ff180020(rockchip,rk3308-pwmrockchip,rk3328-pwm  pwmpclkdefault1 disabledpwm@ff180030(rockchip,rk3308-pwmrockchip,rk3328-pwm0 pwmpclkdefault2 disabledrktimer@ff1a0000rockchip,rk3288-timer   pclktimersaradc@ff1e0000.rockchip,rk3308-saradcrockchip,rk3399-saradc %%saradcapb_pclk F saradc-apbokay3Wdma-controller@ff2c0000arm,pl330arm,primecell,@* apb_pclkAdma-controller@ff2d0000arm,pl330arm,primecell-@* apb_pclkA"i2s@ff350000(rockchip,rk3308-i2srockchip,rk3066-i2s5 4\i2s_clki2s_hclk"" txrx reset-mreset-hdefault4567 disabledi2s@ff360000(rockchip,rk3308-i2srockchip,rk3066-i2s6 5^i2s_clki2s_hclk" rx reset-mreset-h disabledspdif-tx@ff3a0000,rockchip,rk3308-spdifrockchip,rk3066-spdif: 7b mclkhclk" txdefault8 disabledusb@ff4000002rockchip,rk3308-usbrockchip,rk3066-usbsnps,dwc2@ BotgLotgTfu@ 9 usb2-phy disabledusb@ff440000 generic-ehciD G :usb disabledusb@ff450000 generic-ohciE H :usb disabledmmc@ff4800000rockchip,rk3308-dw-mshcrockchip,rk3288-dw-mshcH@ L 012biuciuciu-driveciu-sampleрdefault;<=> disabledmmc@ff4900000rockchip,rk3308-dw-mshcrockchip,rk3288-dw-mshcI@ M :;<biuciuciu-driveciu-sampleр disabledmmc@ff4a00000rockchip,rk3308-dw-mshcrockchip,rk3288-dw-mshcJ@ N 567biuciuciu-driveciu-sampleрdefault ?@A disablednand-controller@ff4b0000(rockchip,rk3308-nfcrockchip,rv1108-nfcK@ Q-ahbnfc[-рBCDEFGHdefault disabledethernet@ff4e0000rockchip,rk3308-gmacN @macirq@@BBA@C[stmmacethmac_clk_rxmac_clk_txclk_mac_refclk_mac_refoutaclk_macpclk_macclk_mac_speedrmiidefaultIJ } stmmacethK disabledclock-controller@ff500000rockchip,rk3308-cruPK[interrupt-controller@ff580000 arm,gic-400@XX X@ X`   sram@fff80000 mmio-sram+ddr-sram@0vad-sram@8000pinctrlrockchip,rk3308-pinctrlK+defaultLgpio0@ff220000rockchip,gpio-bank" (+Ygpio1@ff230000rockchip,gpio-bank# )+gpio2@ff240000rockchip,gpio-bank$ *+gpio3@ff250000rockchip,gpio-bank% ++gpio4@ff260000rockchip,gpio-bank& ,+pcfg-pull-up7Vpcfg-pull-downDSpcfg-pull-noneSOpcfg-pull-none-2maS`pcfg-pull-up-2ma7`pcfg-pull-up-4ma7`Upcfg-pull-none-4maS`Tpcfg-pull-down-4maD`pcfg-pull-none-8maS`Mpcfg-pull-up-8ma7`Npcfg-pull-none-12maS` Qpcfg-pull-up-12ma7` Ppcfg-pull-none-smtSoRpcfg-output-highpcfg-output-lowpcfg-input-high7pcfg-inputemmcemmc-clk Memmc-cmdNemmc-pwren Oemmc-rstn Oemmc-bus1Nemmc-bus4@NNNNemmc-bus8NNNNNNNNflashflash-csn0 OEflash-rdy OGflash-ale OBflash-cle ODflash-wrnOHflash-rdn OFflash-bus8PPPPPPPPCgmacrmii-pinsQQQOOOOO OImac-refclk-12ma QJmac-refclk Ogmac-m1rmiim1-pinsQQQOOOOO Omacm1-refclk-12ma Qmacm1-refclk Oi2c0i2c0-xfer RR i2c1i2c1-xfer  R R i2c2i2c2-xfer RRi2c3-m0i2c3m0-xfer RRi2c3-m1i2c3m1-xfer  R Ri2c3-m2i2c3m2-xfer RRi2s_2ch_0i2s-2ch-0-mclk Oi2s-2ch-0-sclk O4i2s-2ch-0-lrckO5i2s-2ch-0-sdoO7i2s-2ch-0-sdiO6i2s_8ch_0i2s-8ch-0-mclkOi2s-8ch-0-sclktxOi2s-8ch-0-sclkrxOi2s-8ch-0-lrcktxOi2s-8ch-0-lrckrxOi2s-8ch-0-sdo0 Oi2s-8ch-0-sdo1 Oi2s-8ch-0-sdo2 Oi2s-8ch-0-sdo3 Oi2s-8ch-0-sdi0 Oi2s-8ch-0-sdi1Oi2s-8ch-0-sdi2Oi2s-8ch-0-sdi3Oi2s_8ch_1_m0i2s-8ch-1-m0-mclkOi2s-8ch-1-m0-sclktxOi2s-8ch-1-m0-sclkrxOi2s-8ch-1-m0-lrcktxOi2s-8ch-1-m0-lrckrxOi2s-8ch-1-m0-sdo0Oi2s-8ch-1-m0-sdo1-sdi3Oi2s-8ch-1-m0-sdo2-sdi2 Oi2s-8ch-1-m0-sdo3_sdi1 Oi2s-8ch-1-m0-sdi0 Oi2s_8ch_1_m1i2s-8ch-1-m1-mclk Oi2s-8ch-1-m1-sclktx Oi2s-8ch-1-m1-sclkrxOi2s-8ch-1-m1-lrcktxOi2s-8ch-1-m1-lrckrxOi2s-8ch-1-m1-sdo0Oi2s-8ch-1-m1-sdo1-sdi3Oi2s-8ch-1-m1-sdo2-sdi2Oi2s-8ch-1-m1-sdo3_sdi1Oi2s-8ch-1-m1-sdi0Opdm_m0pdm-m0-clkOpdm-m0-sdi0 Opdm-m0-sdi1 Opdm-m0-sdi2 Opdm-m0-sdi3Opdm_m1pdm-m1-clkOpdm-m1-sdi0Opdm-m1-sdi1Opdm-m1-sdi2Opdm-m1-sdi3Opdm_m2pdm-m2-clkmOpdm-m2-clkOpdm-m2-sdi0 Opdm-m2-sdi1Opdm-m2-sdi2Opdm-m2-sdi3Opwm0pwm0-pin Opwm0-pin-pull-down S/pwm1pwm1-pinO0pwm1-pin-pull-downSpwm2pwm2-pinO1pwm2-pin-pull-downSpwm3pwm3-pinO2pwm3-pin-pull-downSpwm4pwm4-pinO+pwm4-pin-pull-downSpwm5pwm5-pinO,pwm5-pin-pull-downSpwm6pwm6-pinO-pwm6-pin-pull-downSpwm7pwm7-pinO.pwm7-pin-pull-downSpwm8pwm8-pin O'pwm8-pin-pull-down Spwm9pwm9-pin O(pwm9-pin-pull-down Spwm10pwm10-pin O)pwm10-pin-pull-down Spwm11pwm11-pinO*pwm11-pin-pull-downSrtcrtc-32kOLsdmmcsdmmc-clkT;sdmmc-cmdU<sdmmc-detU=sdmmc-pwrenTsdmmc-bus1Usdmmc-bus4@UUUU>sdiosdio-clkMAsdio-cmdN@sdio-pwrenMsdio-wrptMsdio-intnMsdio-bus1Nsdio-bus4@NNNN?spdif_inspdif-inOspdif_outspdif-outO8spi0spi0-clkUspi0-csn0Uspi0-misoUspi0-mosiUspi1spi1-clk Uspi1-csn0 Uspi1-miso U spi1-mosi U!spi1-m1spi1m1-misoUspi1m1-mosiUspi1m1-clkUspi1m1-csn0 Uspi2spi2-clkU#spi2-csn0U$spi2-misoU%spi2-mosiU&tsadctsadc-otp-pin Otsadc-otp-out Ouart0uart0-xfer VVuart0-ctsOuart0-rtsOuart0-rts-pinOuart1uart1-xfer VVuart1-ctsOuart1-rtsOuart2-m0uart2m0-xfer VVuart2-m1uart2m1-xfer VVuart3uart3-xfer  V Vuart3-m1uart3m1-xfer VVuart4uart4-xfer  VVuart4-ctsOuart4-rtsOuart4-rts-pinObuttonspwr-keyVXusbusb-drvO]sdio-pwrseqwifi-enable-hOchosenserial4:1500000n8adc-keys0 adc-keysWbuttonsdw@func-key functionFPadc-keys1 adc-keysWbuttonsdw@esc-keymicmute>home-keyumode menu-keyplay vol-down-keyr volume downvol-up-keys volume upFPgpio-keys gpio-keys2defaultXpower =YtGPIO Key PowerCdUvcc12v-dcinregulator-fixed cvcc12v_dcinrZvcc5v0-sysregulator-fixed cvcc5v0_sysrLK@LK@Z\vcc-1v8regulator-fixedcvcc_1v8rw@w@[3vcc-ddrregulator-fixedcvcc_ddrr``\vcc-ioregulator-fixedcvcc_ior2Z2Z\[vccio-flashregulator-fixed cvccio_flashr2Z2Z[vcc5v0-hostregulator-fixed Ydefault] cvbus_host\vdd-corepwm-regulator^ cvdd_corer xr`\vdd-logregulator-fixedcvdd_logr\vdd-1v0regulator-fixedcvdd_1v0rB@B@\ compatibleinterrupt-parent#address-cells#size-cellsmodeli2c0i2c1i2c2i2c3serial0serial1serial2serial3serial4spi0spi1spi2device_typeregenable-methodclocks#cooling-cellsdynamic-power-coefficientoperating-points-v2cpu-idle-statesnext-level-cachecpu-supplyphandleentry-methodlocal-timer-stoparm,psci-suspend-paramentry-latency-usexit-latency-usmin-residency-usopp-sharedopp-hzopp-microvoltclock-latency-nsopp-suspendinterruptsinterrupt-affinityclock-frequencyclock-output-names#clock-cellsoffsetmode-bootloadermode-loadermode-normalmode-recoverymode-fastbootassigned-clocksassigned-clock-parentsclock-namesstatusinterrupt-names#phy-cellspinctrl-namespinctrl-0reg-shiftreg-io-widthdmasdma-names#pwm-cells#io-channel-cellsresetsreset-namesvref-supplyarm,pl330-periph-burst#dma-cellsdr_modeg-np-tx-fifo-sizeg-rx-fifo-sizeg-tx-fifo-sizephysphy-namesbus-widthfifo-depthmax-frequencyassigned-clock-ratesphy-moderockchip,grf#reset-cells#interrupt-cellsinterrupt-controllerrangesgpio-controller#gpio-cellsbias-pull-upbias-pull-downbias-disabledrive-strengthinput-schmitt-enableoutput-highoutput-lowinput-enablerockchip,pinsstdout-pathio-channelsio-channel-namespoll-intervalkeyup-threshold-microvoltlinux,codelabelpress-threshold-microvoltautorepeatgpiosdebounce-intervalwakeup-sourceregulator-nameregulator-min-microvoltregulator-max-microvoltregulator-always-onregulator-boot-onvin-supplygpioenable-active-highpwmsregulator-settling-time-up-uspwm-supply