d}8^0(M])tronsmart,orion-r68-metarockchip,rk3368 +7Rockchip Orion R68aliases=/ethernet@ff290000G/i2c@ff650000L/i2c@ff660000Q/i2c@ff140000V/i2c@ff150000[/i2c@ff160000`/i2c@ff170000e/serial@ff180000m/serial@ff190000u/serial@ff690000}/serial@ff1b0000/serial@ff1c0000/spi@ff110000/spi@ff120000/spi@ff130000/mmc@ff0c0000/mmc@ff0f0000cpus+cpu-mapcluster0core0core1core2core3cluster1core0core1core2core3 cpu@0cpuarm,cortex-a53pscicpu@1cpuarm,cortex-a53pscicpu@2cpuarm,cortex-a53pscicpu@3cpuarm,cortex-a53psci cpu@100cpuarm,cortex-a53pscicpu@101cpuarm,cortex-a53pscicpu@102cpuarm,cortex-a53pscicpu@103cpuarm,cortex-a53psciarm-pmuarm,armv8-pmuv3`pqrstuvw  psci arm,psci-0.2smctimerarm,armv8-timer0   oscillator fixed-clockn6 xin24m mmc@ff0c00000rockchip,rk3368-dw-mshcrockchip,rk3288-dw-mshc @- ;  D r vBbiuciuciu-driveciu-sampleN Y `resetlokays}default mmc@ff0d00000rockchip,rk3368-dw-mshcrockchip,rk3288-dw-mshc @-р ;  E s wBbiuciuciu-driveciu-sampleN !Y `reset ldisabledmmc@ff0f00000rockchip,rk3368-dw-mshcrockchip,rk3288-dw-mshc@-р ;  G u yBbiuciuciu-driveciu-sampleN #Y `resetlokays default saradc@ff100000rockchip,saradc $; I [Bsaradcapb_pclkY W `saradc-apblokay,spi@ff110000(rockchip,rk3368-spirockchip,rk3066-spi; A RBspiclkapb_pclk ,default+ ldisabledspi@ff120000(rockchip,rk3368-spirockchip,rk3066-spi; B SBspiclkapb_pclk -default+ ldisabledspi@ff130000(rockchip,rk3368-spirockchip,rk3066-spi; C TBspiclkapb_pclk )default !+ ldisabledi2c@ff140000(rockchip,rk3368-i2crockchip,rk3288-i2c >+Bi2c; Ndefault" ldisabledi2c@ff150000(rockchip,rk3368-i2crockchip,rk3288-i2c ?+Bi2c; Odefault# ldisabledi2c@ff160000(rockchip,rk3368-i2crockchip,rk3288-i2c @+Bi2c; Pdefault$ ldisabledi2c@ff170000(rockchip,rk3368-i2crockchip,rk3288-i2c A+Bi2c; Qdefault% ldisabledserial@ff180000&rockchip,rk3368-uartsnps,dw-apb-uartn6; M UBbaudclkapb_pclk 78B ldisabledserial@ff190000&rockchip,rk3368-uartsnps,dw-apb-uartn6; N VBbaudclkapb_pclk 88B ldisabledserial@ff1b0000&rockchip,rk3368-uartsnps,dw-apb-uartn6; P XBbaudclkapb_pclk :8B ldisabledserial@ff1c0000&rockchip,rk3368-uartsnps,dw-apb-uartn6; Q YBbaudclkapb_pclk ;8Blokaydefault&dma-controller@ff250000arm,pl330arm,primecell%@OZu;  Bapb_pclkthermal-zonescpu-thermald'tripscpu_alert0$passive(cpu_alert18passive)cpu_crits criticalcooling-mapsmap0(0map1)0 gpu-thermald'tripsgpu_alert08passive*gpu_crit8 criticalcooling-mapsmap0*0tsadc@ff280000rockchip,rk3368-tsadc( %; H ZBtsadcapb_pclkY  `tsadc-apbinitdefaultsleep+,+s ldisabled'ethernet@ff290000rockchip,rk3368-gmac) ,macirq<-8;  f g c ]MBstmmacethmac_clk_rxmac_clk_txclk_mac_refclk_mac_refoutaclk_macpclk_maclokayI Y.pinput}/rgmiidefault0 1  'B@0usb@ff500000 generic-ehciP ; lokayusb@ff5800002rockchip,rk3368-usbrockchip,rk3066-usbsnps,dwc2X ; Botgotg@@ lokaydma-controller@ff600000arm,pl330arm,primecell`@OZu;  Bapb_pclk9i2c@ff650000(rockchip,rk3368-i2crockchip,rk3288-i2ce; LBi2c <default2+lokaysyr827@40silergy,syr827@3vdd_cpuB,^ 4v`@3hym8563@51haoyu,hym8563Q  xin32ki2c@ff660000(rockchip,rk3368-i2crockchip,rk3288-i2cf =+Bi2c; Mdefault4 ldisabledpwm@ff680000(rockchip,rk3368-pwmrockchip,rk3288-pwmhdefault5; _ ldisabledpwm@ff680010(rockchip,rk3368-pwmrockchip,rk3288-pwmhdefault6; _ ldisabledpwm@ff680020(rockchip,rk3368-pwmrockchip,rk3288-pwmh ; _ ldisabledpwm@ff680030(rockchip,rk3368-pwmrockchip,rk3288-pwmh0default7; _ ldisabledserial@ff690000&rockchip,rk3368-uartsnps,dw-apb-uarti; O WBbaudclkapb_pclk 9default88Blokaymbox@ff6b0000rockchip,rk3368-mailboxk0; E Bpclk_mailbox ldisabledsyscon@ff738000)rockchip,rk3368-pmugrfsysconsimple-mfds<io-domains&rockchip,rk3368-pmu-io-voltage-domain ldisabledreboot-modesyscon-reboot-modeRBRB RB RBclock-controller@ff760000rockchip,rk3368-cruv<- ( syscon@ff770000&rockchip,rk3368-grfsysconsimple-mfdw-io-domains"rockchip,rk3368-io-voltage-domain ldisabledwatchdog@ff800000 rockchip,rk3368-wdtsnps,dw-wdt; p Olokaytimer@ff810000,rockchip,rk3368-timerrockchip,rk3288-timer  B; a U Bpclktimerspdif@ff880000rockchip,rk3368-spdif 6; S  Bmclkhclk59:txdefault: ldisabledi2s-2ch@ff890000(rockchip,rk3368-i2srockchip,rk3066-i2s (Bi2s_clki2s_hclk; T 599:txrx ldisabledi2s-8ch@ff898000(rockchip,rk3368-i2srockchip,rk3066-i2s 5Bi2s_clki2s_hclk; R 599:txrxdefault; ldisablediommu@ff900800rockchip,iommu ,iep_mmu;  BaclkifaceD ldisablediommu@ff914000rockchip,iommu @P ,isp_mmu;  BaclkifaceDQ ldisablediommu@ff930300rockchip,iommu ,vop_mmu;  BaclkifaceD ldisablediommu@ff9a0440rockchip,iommu @@@  ,hevc_mmu;  BaclkifaceD ldisablediommu@ff9a0800rockchip,iommu  ,vepu_mmuvdpu_mmu;  BaclkifaceD ldisabledefuse@ffb00000rockchip,rk3368-efuse +; q Bpclk_efusecpu-leakage@17temp-adjust@1finterrupt-controller@ffb71000 arm,gic-400l@ @ `   pinctrlrockchip,rk3368-pinctrl<-<+gpio0@ff750000rockchip,gpio-banku; @ QlFgpio1@ff780000rockchip,gpio-bankx; A Rlgpio2@ff790000rockchip,gpio-banky; B SlDgpio3@ff7a0000rockchip,gpio-bankz; C Tl1pcfg-pull-up?pcfg-pull-downBpcfg-pull-none@pcfg-pull-none-12ma Aemmcemmc-clk=emmc-cmd>emmc-pwr?emmc-bus1?emmc-bus4@????emmc-bus8>>>>>>>>emmc-reset@Cgmacrgmii-pins@@@A A AAA A@@@@@@0rmii-pins@@@A A A@@@@i2c0i2c0-xfer @@2i2c1i2c1-xfer @@4i2c2i2c2-xfer  @@"i2c3i2c3-xfer @@#i2c4i2c4-xfer @@$i2c5i2c5-xfer @@%i2si2s-8ch-bus @ @@@@@@@@;pwm0pwm0-pin@5pwm1pwm1-pin@6pwm3pwm3-pin@7sdio0sdio0-bus1?sdio0-bus4@????sdio0-cmd?sdio0-clk@sdio0-cd?sdio0-wp?sdio0-pwr?sdio0-bkpwr?sdio0-int?sdmmcsdmmc-clk = sdmmc-cmd > sdmmc-cd > sdmmc-bus1>sdmmc-bus4@>>>>spdifspdif-tx@:spi0spi0-clk?spi0-cs0?spi0-cs1?spi0-tx?spi0-rx?spi1spi1-clk?spi1-cs0?spi1-cs1?spi1-rx?spi1-tx?spi2spi2-clk ?spi2-cs0 ?!spi2-rx ? spi2-tx ?tsadcotp-pin@+otp-out@,uart0uart0-xfer ?@uart0-cts@uart0-rts@uart1uart1-xfer ?@uart1-cts@uart1-rts@uart2uart2-xfer ?@8uart3uart3-xfer ?@uart3-cts@uart3-rts@uart4uart4-xfer ?@&uart4-cts@uart4-rts@pcfg-pull-none-drv-8ma=pcfg-pull-up-drv-8ma>keyspwr-keyBEledsstby-pwren @Hled-ctl@Gusbhost-vbus-drv@Ichosenserial2:115200n8memorymemoryemmc-pwrseqmmc-pwrseq-emmcCdefault Dexternal-gmac-clock fixed-clock sY@  ext_gmac.gpio-keys gpio-keysdefaultEpower  F .GPIO Power4tgpio-leds gpio-ledsled-0 1.orion:red:leddefaultG?onled-1 F .orion:blue:leddefaultH?offvcc18-regulatorregulator-fixed3vcc_18^w@vw@3vcc-host-regulatorregulator-fixed FdefaultI 3vcc_host3vcc-io-regulatorregulator-fixed3vcc_io^2Zv2Z3Jvcc-lan-regulatorregulator-fixed3vcc_lan^2Zv2ZJ/vcc-sd-regulatorregulator-fixed3vcc_sd 1 ^w@v2ZJvcc-sys-regulatorregulator-fixed3vcc_sys^LK@vLK@3vcc-io-sd-regulatorregulator-fixed 3vccio_sd^w@v2ZJvccio-wl-regulatorregulator-fixed 3vccio_wl^2Zv2ZJvdd-10-regulatorregulator-fixed3vdd_10^B@vB@3 compatibleinterrupt-parent#address-cells#size-cellsmodelethernet0i2c0i2c1i2c2i2c3i2c4i2c5serial0serial1serial2serial3serial4spi0spi1spi2mmc0mmc1cpudevice_typeregenable-method#cooling-cellsphandleinterruptsinterrupt-affinityclock-frequencyclock-output-names#clock-cellsmax-frequencyclocksclock-namesfifo-depthresetsreset-namesstatusbus-widthcap-sd-highspeedcard-detect-delaypinctrl-namespinctrl-0vmmc-supplyvqmmc-supplycap-mmc-highspeedmmc-pwrseqmmc-hs200-1_2vmmc-hs200-1_8vnon-removable#io-channel-cellsvref-supplyreg-shiftreg-io-width#dma-cellsarm,pl330-broken-no-flushparm,pl330-periph-burstpolling-delay-passivepolling-delaythermal-sensorstemperaturehysteresistripcooling-devicepinctrl-1pinctrl-2#thermal-sensor-cellsrockchip,hw-tshut-tempinterrupt-namesrockchip,grfassigned-clocksassigned-clock-parentsclock_in_outphy-supplyphy-modesnps,reset-gpiosnps,reset-active-lowsnps,reset-delays-ustx_delayrx_delaydr_modeg-np-tx-fifo-sizeg-rx-fifo-sizeg-tx-fifo-sizefcs,suspend-voltage-selectorregulator-nameregulator-enable-ramp-delayregulator-min-microvoltregulator-max-microvoltregulator-ramp-delayregulator-always-onregulator-boot-onvin-supply#pwm-cells#mbox-cellsoffsetmode-normalmode-recoverymode-bootloadermode-loader#reset-cellsdmasdma-names#iommu-cellsrockchip,disable-mmu-resetinterrupt-controller#interrupt-cellsrockchip,pmurangesgpio-controller#gpio-cellsbias-pull-upbias-pull-downbias-disabledrive-strengthrockchip,pinsstdout-pathreset-gpioswakeup-sourcelabellinux,codedefault-state