Ð þí@48<0(;ø)rockchip,rk3568-evb1-v10rockchip,rk3568 +$7Rockchip RK3568 EVB1 DDR4 V10 Boardaliases=/pinctrl/gpio@fdd60000C/pinctrl/gpio@fe740000I/pinctrl/gpio@fe750000O/pinctrl/gpio@fe760000U/pinctrl/gpio@fe770000[/i2c@fdd40000`/i2c@fe5a0000e/i2c@fe5b0000j/i2c@fe5c0000o/i2c@fe5d0000t/i2c@fe5e0000y/serial@fdd50000/serial@fe650000‰/serial@fe660000‘/serial@fe670000™/serial@fe680000¡/serial@fe690000©/serial@fe6a0000±/serial@fe6b0000¹/serial@fe6c0000Á/serial@fe6d0000cpus+cpu@0Écpuarm,cortex-a55ÕÙàpsciîcpu@100Écpuarm,cortex-a55Õàpsciîcpu@200Écpuarm,cortex-a55Õàpsciîcpu@300Écpuarm,cortex-a55Õàpsciîcpu0-opp-tableoperating-points-v2 opp-408000000Q–  »  » Œ0*œ@opp-600000000#ÃF  »  » Œ0opp-8160000000£,  »  » Œ0;opp-1104000000AÍ´  »  » Œ0opp-1416000000Tfr  »  » Œ0opp-1608000000_Ø" à˜à˜Œ0opp-1800000000kIÒ Œ0opp-1992000000v»‚ Œ0Œ0Œ0firmwarescmi arm,scmi-smcG‚R+protocol@14ÕXpmuarm,cortex-a55-pmu0eäåæçppsci arm,psci-1.0çsmctimerarm,armv8-timer0e   ƒxin24m fixed-clockšn6ªxin24mXxin32k fixed-clockš€ªxin32k½ ÇdefaultXsram@10f000 mmio-sramÕð+Õðsram@0arm,scmi-shmemÕinterrupt-controller@fd400000 arm,gic-v3 Õý@ýF e Üñý (syscon@fdc20000)rockchip,rk3568-pmugrfsysconsimple-mfdÕýÂsyscon@fdc60000&rockchip,rk3568-grfsysconsimple-mfdÕýÆclock-controller@fdd00000rockchip,rk3568-pmucruÕýÐX& clock-controller@fdd20000rockchip,rk3568-cruÕýÒX&i2c@fdd40000(rockchip,rk3568-i2crockchip,rk3399-i2cÕýÔ e.Ù  - 3i2cpclk½ Çdefault+ ?disabledserial@fdd50000&rockchip,rk3568-uartsnps,dw-apb-uartÕýÕ etÙ ,3baudclkapb_pclkF ½ ÇdefaultKX ?disabledmmc@fe0000000rockchip,rk3568-dw-mshcrockchip,rk3288-dw-mshcÕþ@ ed ÙÁÂŽ3biuciuciu-driveciu-samplebmðÑ€{ë‚reset ?disabledmmc@fe2b00000rockchip,rk3568-dw-mshcrockchip,rk3288-dw-mshcÕþ+@ eb Ù°±Š‹3biuciuciu-driveciu-samplebmðÑ€{Ô‚reset ?disabledmmc@fe2c00000rockchip,rk3568-dw-mshcrockchip,rk3288-dw-mshcÕþ,@ ec Ù²³Œ3biuciuciu-driveciu-samplebmðÑ€{Ö‚reset ?disabledmmc@fe310000rockchip,rk3568-dwcmshcÕþ1 eŽ{}ž ëÂn6(Ù|zy{}3corebusaxiblocktimer?okay³m ë½dmac@fe530000arm,pl330arm,primecellÕþS@e ËÙ  3apb_pclkâ dmac@fe550000arm,pl330arm,primecellÕþU@eËÙ  3apb_pclkâi2c@fe5a0000(rockchip,rk3568-i2crockchip,rk3399-i2cÕþZ e/ÙHG 3i2cpclk½Çdefault+ ?disabledi2c@fe5b0000(rockchip,rk3568-i2crockchip,rk3399-i2cÕþ[ e0ÙJI 3i2cpclk½Çdefault+ ?disabledi2c@fe5c0000(rockchip,rk3568-i2crockchip,rk3399-i2cÕþ\ e1ÙLK 3i2cpclk½Çdefault+ ?disabledi2c@fe5d0000(rockchip,rk3568-i2crockchip,rk3399-i2cÕþ] e2ÙNM 3i2cpclk½Çdefault+ ?disabledi2c@fe5e0000(rockchip,rk3568-i2crockchip,rk3399-i2cÕþ^ e3ÙPO 3i2cpclk½Çdefault+ ?disabledserial@fe650000&rockchip,rk3568-uartsnps,dw-apb-uartÕþe euÙ3baudclkapb_pclkF  ½ÇdefaultKX ?disabledserial@fe660000&rockchip,rk3568-uartsnps,dw-apb-uartÕþf evÙ# 3baudclkapb_pclkF  ½ÇdefaultKX?okayserial@fe670000&rockchip,rk3568-uartsnps,dw-apb-uartÕþg ewÙ'$3baudclkapb_pclkF  ½ÇdefaultKX ?disabledserial@fe680000&rockchip,rk3568-uartsnps,dw-apb-uartÕþh exÙ+(3baudclkapb_pclkF  ½ÇdefaultKX ?disabledserial@fe690000&rockchip,rk3568-uartsnps,dw-apb-uartÕþi eyÙ/,3baudclkapb_pclkF ½ÇdefaultKX ?disabledserial@fe6a0000&rockchip,rk3568-uartsnps,dw-apb-uartÕþj ezÙ303baudclkapb_pclkF ½ÇdefaultKX ?disabledserial@fe6b0000&rockchip,rk3568-uartsnps,dw-apb-uartÕþk e{Ù743baudclkapb_pclkF  ½ÇdefaultKX ?disabledserial@fe6c0000&rockchip,rk3568-uartsnps,dw-apb-uartÕþl e|Ù;83baudclkapb_pclkF  ½ÇdefaultKX ?disabledserial@fe6d0000&rockchip,rk3568-uartsnps,dw-apb-uartÕþm e}Ù?<3baudclkapb_pclkF  ½ÇdefaultKX ?disabledpinctrlrockchip,rk3568-pinctrlíú+Õgpio@fdd60000rockchip,gpio-bankÕýÖ e!Ù .Üñgpio@fe740000rockchip,gpio-bankÕþt e"ÙcÜñgpio@fe750000rockchip,gpio-bankÕþu e#ÙeÜñgpio@fe760000rockchip,gpio-bankÕþv e$ÙgÜñgpio@fe770000rockchip,gpio-bankÕþw e%ÙiÜñpcfg-pull-up#!pcfg-pull-none0pcfg-pull-none-drv-level-10=#pcfg-pull-none-drv-level-20="pcfg-pull-none-drv-level-30=&pcfg-pull-up-drv-level-1#=%pcfg-pull-up-drv-level-2#= pcfg-pull-none-smt0L$acodecaudiopwmbt656bt1120camcan0can1can2cifclk32kclk32k-out0a cpuebcedpdpemmceth0eth1flashfspigmac0gmac1gpuhdmitxi2c0i2c0-xfer a $ $ i2c1i2c1-xfer a $ $i2c2i2c2m0-xfer a $$i2c3i2c3m0-xfer a$$i2c4i2c4m0-xfer a $ $i2c5i2c5m0-xfer a $ $i2s1i2s2i2s3ispjtaglcdcmcunpupcie20pcie30x1pcie30x2pdmpmicpmupwm0pwm1pwm2pwm3pwm4pwm5pwm6pwm7pwm8pwm9pwm10pwm11pwm12pwm13pwm14pwm15refclksatasata0sata1sata2scrsdmmc0sdmmc1sdmmc2spdifspi0spi1spi2spi3tsadcuart0uart0-xfer a!! uart1uart1m0-xfer a ! !uart2uart2m0-xfer a!!uart3uart3m0-xfer a!!uart4uart4m0-xfer a!!uart5uart5m0-xfer a!!uart6uart6m0-xfer a!!uart7uart7m0-xfer a!!uart8uart8m0-xfer a!!uart9uart9m0-xfer a!!vopspi0-hsspi1-hsspi2-hsspi3-hsgmac-txd-level3gmac-txc-level2chosenoserial2:1500000n8dc-12vregulator-fixed{dc_12vŠž°·È·'vcc3v3-sysregulator-fixed {vcc3v3_sysŠž°2Z È2Z à'vcc5v0-sysregulator-fixed {vcc5v0_sysŠž°LK@ÈLK@à'vcc3v3-lcd0-nregulator-fixed{vcc3v3_lcd0_nžregulator-state-memëvcc3v3-lcd1-nregulator-fixed{vcc3v3_lcd1_nžregulator-state-memë compatibleinterrupt-parent#address-cells#size-cellsmodelgpio0gpio1gpio2gpio3gpio4i2c0i2c1i2c2i2c3i2c4i2c5serial0serial1serial2serial3serial4serial5serial6serial7serial8serial9device_typeregclocksenable-methodoperating-points-v2phandleopp-sharedopp-hzopp-microvoltclock-latency-nsopp-suspendarm,smc-idshmem#clock-cellsinterruptsinterrupt-affinityarm,no-tick-in-suspendclock-frequencyclock-output-namespinctrl-0pinctrl-namesrangesinterrupt-controller#interrupt-cellsmbi-aliasmbi-rangesmsi-controller#reset-cellsclock-namesstatusdmasreg-io-widthreg-shiftfifo-depthmax-frequencyresetsreset-namesassigned-clocksassigned-clock-ratesbus-widthnon-removablearm,pl330-periph-burst#dma-cellsrockchip,grfrockchip,pmugpio-controller#gpio-cellsbias-pull-upbias-disabledrive-strengthinput-schmitt-enablerockchip,pinsstdout-pathregulator-nameregulator-always-onregulator-boot-onregulator-min-microvoltregulator-max-microvoltvin-supplyregulator-off-in-suspend