8(x$mediatek,mt8183-evbmediatek,mt8183 +!7MediaTek MT8183 evaluation boardaliases=/soc/i2c@11007000B/soc/i2c@11011000G/soc/i2c@11009000L/soc/i2c@1100f000Q/soc/i2c@11008000V/soc/i2c@11016000[/soc/i2c@11005000`/soc/i2c@1101a000e/soc/i2c@1101b000j/soc/i2c@11014000o/soc/i2c@11015000u/soc/i2c@11017000{/soc/ovl@14008000/soc/ovl@14009000/soc/ovl@1400a000/soc/rdma@1400b000/soc/rdma@1400c000/soc/serial@11002000opp-table-cluster0operating-points-v2 opp0-793000000/D8@ opp0-9100000006= }opp0-1014000000opp0-1417000000Tu@ Popp0-1508000000YA A opp0-1586000000^p 6 opp0-1625000000`ۈ@  opp0-1677000000c@5 opp0-1716000000fHf opp0-1781000000j'@opp0-1846000000nB@opp0-1924000000ropp0-1989000000v@opp-table-cluster1operating-points-v2#opp1-793000000/D8@ `opp1-9100000006= opp1-1014000000opp-689000000)N@ Popp-767000000-} A opp-8450000002]@ 6 opp-8710000003g  opp-92300000075 opp-9620000009Vf opp-1027000000=6opp-1092000000AB@opp-1144000000D0opp-1196000000GIccimediatek,mt8183-ccicciintermediate!cpus+cpu-mapcluster0core0 core1 core2 core3 cluster1core0 core1 core2 core3 cpu@0cpuarm,cortex-a53!psci/Bcpuintermediate RTl{!cpu@1cpuarm,cortex-a53!psci/Bcpuintermediate RTl{!cpu@2cpuarm,cortex-a53!psci/Bcpuintermediate RTl{!cpu@3cpuarm,cortex-a53!psci/Bcpuintermediate RTl{!cpu@100cpuarm,cortex-a73!psci/B"cpuintermediate#Rl{!$cpu@101cpuarm,cortex-a73!psci/B"cpuintermediate#Rl{!$cpu@102cpuarm,cortex-a73!psci/B"cpuintermediate#Rl{!$cpu@103cpuarm,cortex-a73!psci/B"cpuintermediate#Rl{!$idle-statespscicpu-sleeparm,idle-state cluster-sleep-0arm,idle-statecluster-sleep-1arm,idle-state"opp-table-0operating-points-v2]opp-300000000 h Popp-320000000 Popp-340000000C < Popp-360000000u* Ҧ Popp-380000000W  Popp-400000000ׄ z Popp-420000000  Popp-460000000k  L Popp-500000000e } Popp-540000000 / ` Popp-580000000" 4 Popp-620000000$s  Popp-653000000&@ YF Popp-698000000) Aopp-743000000,IG  6opp-800000000/ Hpmu-a53arm,cortex-a53-pmu %&pmu-a73arm,cortex-a73-pmu %'psci arm,psci-1.0(smcfixed-factor-clock-13mfixed-factor-clock(clk13m2oscillator fixed-clock/clk26m(timerarm,armv8-timer %@   soc+ simple-bus?efuse@8000000%mediatek,mt8183-efusemediatek,efuse+ Fdisabledinterrupt-controller@c000000 arm,gic-v3M %^P   @ A B  %ppi-partitionsinterrupt-partition-0s&interrupt-partition-1s'syscon@c530000mediatek,mt8183-mcucfgsyscon Sinterrupt-controller@c530a80.mediatek,mt8183-sysirqmediatek,mt6577-sysirq^M % S Pcpu-debug@d410000&arm,coresight-cpu-debugarm,primecell A). apb_pclk cpu-debug@d510000&arm,coresight-cpu-debugarm,primecell Q). apb_pclk cpu-debug@d610000&arm,coresight-cpu-debugarm,primecell a). apb_pclk cpu-debug@d710000&arm,coresight-cpu-debugarm,primecell q). apb_pclk cpu-debug@d810000&arm,coresight-cpu-debugarm,primecell ). apb_pclk cpu-debug@d910000&arm,coresight-cpu-debugarm,primecell ). apb_pclk cpu-debug@da10000&arm,coresight-cpu-debugarm,primecell ). apb_pclk cpu-debug@db10000&arm,coresight-cpu-debugarm,primecell ). apb_pclk syscon@10000000 mediatek,mt8183-topckgensysconsyscon@10001000 mediatek,mt8183-infracfgsyscon|)syscon@10003000mediatek,mt8183-pericfgsyscon0Ppinctrl@10005000mediatek,mt8183-pinctrlPDiocfg0iocfg1iocfg2iocfg3iocfg4iocfg5iocfg6iocfg7iocfg8eint*^ M*i2c0:pins_i2cRSi2c1Hpins_i2cQTi2c2<pins_i2cghi2c3Fpins_i2c23i2c4;pins_i2ciji2c5Kpins_i2c01spi0=pins_spiUVWXmmc0defaultSpins_cmd_dat${}~z pins_clk|pins_rst mmc0Tpins_cmd_dat${}~z)  epins_clk|) fpins_ds) fpins_rst)  mmc1defaultWpins_cmd_dat "! pins_clkpins_pmu8mmc1Xpins_cmd_dat "!) epins_clk)fspi1Gpins_spispi2Ipins_spi^spi3Jpins_spispi4Lpins_spispi5Mpins_spi pwm1Epins_pwmZsyscon@10006000)mediatek,mt8183-scpsyssysconsimple-mfd`power-controller!mediatek,mt8183-power-controller+DDpower-domain@0 )/)7audioaudio1audio2Dpower-domain@1X)Dpower-domain@2mfg+Dpower-domain@3+Dj+power-domain@4Dpower-domain@5Dpower-domain@6X)Dpower-domain@7X,,,,,,,,,, 5mmmm-0mm-1mm-2mm-3mm-4mm-5mm-6mm-7mm-8mm-9X)x-+Dpower-domain@8@.. ......camcam-0cam-1cam-2cam-3cam-4cam-5cam-6X)x-Dpower-domain@9 "/ /ispisp-0isp-1X)x-Dpower-domain@10 x-Dpower-domain@11 x-Dpower-domain@12 @&#000000-vpuvpu1vpu-0vpu-1vpu-2vpu-3vpu-4vpu-5X)x-+Dpower-domain@13 $vpu2X)Dpower-domain@14%vpu3X)Dwatchdog@10007000mediatek,mt8183-wdtp|Qsyscon@1000c000"mediatek,mt8183-apmixedsyssysconApwrap@1000d000mediatek,mt8183-pwrappwrap )) spiwrapmt6358mediatek,mt6358^ *Mmt6358codecmediatek,mt6358-soundmt6358regulatormediatek,mt6358-regulatorbuck_vdram1vdram1 L0buck_vcorevcore jbuck_vpavpa 7Pbuck_vproc11vproc11 j$buck_vproc12vproc12 jbuck_vgpuvgpu j+buck_vs2vs2 L0buck_vmodemvmodem jbuck_vs1vs1B@'{l0ldo_vdram2vdram2 'w@ ldo_vsim1vsim1/M`ldo_vibrvibrO2Z<ldo_vrf12regulator-fixedvrf12OOxldo_vio18regulator-fixedvio18w@w@ Vldo_vusbvusb-/M`ldo_vcamioregulator-fixedvcamiow@w@Eldo_vcamdvcamd w@Eldo_vcn18regulator-fixedvcn18w@w@ldo_vfe28regulator-fixedvfe28**ldo_vsram_proc11 vsram_proc11 jldo_vcn28regulator-fixedvcn28**ldo_vsram_others vsram_others jldo_vsram_gpu vsram_gpu j^ldo_vxo22regulator-fixedvxo22!!xldo_vefusevefuseldo_vaux18regulator-fixedvaux18w@w@ldo_vmchvmch,@ 2Z<Yldo_vbif28regulator-fixedvbif28**ldo_vsram_proc12 vsram_proc12 jldo_vcama1vcama1w@-Eldo_vemcvemc,@ 2Z<Uldo_vio28regulator-fixedvio28**ldo_va12regulator-fixedva12OOldo_vrf18regulator-fixedvrf18w@w@xldo_vcn33_bt vcn33_bt2Z5gldo_vcn33_wifi vcn33_wifi2Z5gldo_vcama2vcama2w@-Eldo_vmcvmcw@2Z<Zldo_vldo28vldo28*-ldo_vaud28regulator-fixedvaud28**ldo_vsim2vsim2/M`mt6358rtcmediatek,mt6358-rtcmt6358keysmediatek,mt6358-keyspower4tChome4fkeyboard@10010000mediatek,mt6779-keypad (kpd Fdisabledscp@10500000mediatek,mt8183-scp P\ sramcfg )mainQ1 Fdisabledtimer@10017000,mediatek,mt8183-timermediatek,mt6765-timerp 2iommu@10205000mediatek,mt8183-m4u P _3456789n`mailbox@10238000mediatek,mt8183-gce#@ {)gce_auxadc@11001000.mediatek,mt8183-auxadcmediatek,mt8173-auxadc)#mainFokay@serial@11002000*mediatek,mt8183-uartmediatek,mt6577-uart  [ () baudbusFokayserial@11003000*mediatek,mt8183-uartmediatek,mt6577-uart0 \ () baudbus Fdisabledserial@11004000*mediatek,mt8183-uartmediatek,mt6577-uart@ ] () baudbus Fdisabledi2c@11005000mediatek,mt8183-i2c P W)W)* maindma+ Fdisabledi2c@11007000mediatek,mt8183-i2c p Q) )* maindma+Fokaydefault:/i2c@11008000mediatek,mt8183-i2c  R) )*)G maindmaarb+Fokaydefault;/B@i2c@11009000mediatek,mt8183-i2c  S) )*)I maindmaarb+Fokaydefault</spi@1100a000mediatek,mt8183-spi+ x6)parent-clksel-clkspi-clkFokaydefault=svs@1100b000mediatek,mt8183-svs ) main>?(svs-calibration-datat-calibration-datathermal@1100b000mediatek,mt8183-thermal) )# thermauxadc) L@A?calibration-dataBthermal-zonescpu-thermal#d9GBWtripstrip-point0i upassivetrip-point1i8upassiveCcpu-criti8u criticalcooling-mapsmap0C0 map1C0tzts1#9GBWtripscooling-mapstzts2#9GBWtripscooling-mapstzts3#9GBWtripscooling-mapstzts4#9GBWtripscooling-mapstzts5#9GBWtripscooling-mapstztsABB#9GBWtripscooling-mapspwm@1100e000mediatek,mt8183-disp-pwm D)5mainmmpwm@11006000mediatek,mt8183-pwm`0))))))topmainpwm1pwm2pwm3pwm4FokayEdefaulti2c@1100f000mediatek,mt8183-i2c  T) )* maindma+FokaydefaultF/spi@11010000mediatek,mt8183-spi+ |6)8parent-clksel-clkspi-clkFokaydefaultGi2c@11011000mediatek,mt8183-i2c  U)9)* maindma+FokaydefaultH/spi@11012000mediatek,mt8183-spi+  6);parent-clksel-clkspi-clkFokaydefaultIspi@11013000mediatek,mt8183-spi+0 6)<parent-clksel-clkspi-clkFokaydefaultJi2c@11014000mediatek,mt8183-i2c @ )H)*)G maindmaarb+ Fdisabledi2c@11015000mediatek,mt8183-i2c P )J)*)I maindmaarb+ Fdisabledi2c@11016000mediatek,mt8183-i2c ` V)D)*)E maindmaarb+FokaydefaultK/B@i2c@11017000mediatek,mt8183-i2c p )F)*)E maindmaarb+ Fdisabledspi@11018000mediatek,mt8183-spi+ 6)Kparent-clksel-clkspi-clkFokaydefaultLspi@11019000mediatek,mt8183-spi+ 6)Lparent-clksel-clkspi-clkFokaydefaultMi2c@1101a000mediatek,mt8183-i2c  X)b)* maindma+ Fdisabledi2c@1101b000mediatek,mt8183-i2c  Y)c)* maindma+ Fdisabledusb@11201000#mediatek,mt8183-mtu3mediatek,mtu3  . > macippc HNO)=)Zsys_ckref_ck P e+? Fdisabledusb@11200000'mediatek,mt8183-xhcimediatek,mtk-xhci mac I)=)Zsys_ckref_ck Fdisabledaudio-controller@11220000 mediatek,mt8183-audiosyssyscon"Rmt8183-afe-pcmmediatek,mt8183-audio Q audiosysDDRRRRR RRRRR R R R RR)/)7  0HLKOtuvwxyz{|}~(waud_afe_clkaud_dac_clkaud_dac_predis_clkaud_adc_clkaud_adc_adda6_clkaud_apll22m_clkaud_apll24m_clkaud_apll1_tuner_clkaud_apll2_tuner_clkaud_i2s1_bclk_swaud_i2s2_bclk_swaud_i2s3_bclk_swaud_i2s4_bclk_swaud_tdm_clkaud_tml_clkaud_infra_clkmtkaif_26m_clktop_mux_audiotop_mux_aud_intbustop_syspll_d2_d4top_mux_aud_1top_apll1_cktop_mux_aud_2top_apll2_cktop_mux_aud_eng1top_apll1_d8top_mux_aud_eng2top_apll2_d8top_i2s0_m_seltop_i2s1_m_seltop_i2s2_m_seltop_i2s3_m_seltop_i2s4_m_seltop_i2s5_m_seltop_apll12_div0top_apll12_div1top_apll12_div2top_apll12_div3top_apll12_div4top_apll12_divbtop_clk26m_clkmmc@11230000mediatek,mt8183-mmc # M))sourcehclksource_cgFokaydefaultstate_uhsST %4EMS(bUnV{Ummc@11240000mediatek,mt8183-mmc $ N ))(sourcehclksource_cgFokaydefaultstate_uhsWX MbYnZCdsi-phy@11e50000mediatek,mt8183-mipi-txA mipi_tx0_pll[calibration-dataaefuse@11f10000%mediatek,mt8183-efusemediatek,efuse+calib@180 ?calib@190 [calib@580d>t-phy@11f40000.mediatek,mt8183-tphymediatek,generic-tphy-v2+?Fokayusb-phy@0(refFokayNusb-phy@700 (refFokayOsyscon@13000000mediatek,mt8183-mfgcfgsyscon\gpu@13040000&mediatek,mt8183-maliarm,mali-bifrost@$ !jobmmugpu\DDD1core0core1core2]D+P^syscon@14000000mediatek,mt8183-mmsyssyscon|\__c_,mdp3-rdma0@14001000mediatek,mt8183-mdp3-rdmac_{D, ,` \__mdp3-rsz0@14003000mediatek,mt8183-mdp3-rsz0c_0{,mdp3-rsz1@14004000mediatek,mt8183-mdp3-rsz@c_@{,mdp3-wrot0@14005000mediatek,mt8183-mdp3-wrotPc_P{!D,`mdp3-wdma@14006000mediatek,mt8183-mdp3-wdma`c_`{"D,)`ovl@14008000mediatek,mt8183-disp-ovl D,`c_ovl@14009000mediatek,mt8183-disp-ovl-2l D,`c_ovl@1400a000mediatek,mt8183-disp-ovl-2l D,`c_rdma@1400b000mediatek,mt8183-disp-rdma D,`c_rdma@1400c000mediatek,mt8183-disp-rdma D,`c_color@1400e0006mediatek,mt8183-disp-colormediatek,mt8173-disp-color D,c_ccorr@1400f000mediatek,mt8183-disp-ccorr D,c_aal@14010000mediatek,mt8183-disp-aal D,c_gamma@14011000mediatek,mt8183-disp-gamma D,c_dither@14012000mediatek,mt8183-disp-dither  D,c_ dsi@14014000mediatek,mt8183-dsi@ D,, aenginedigitalhs,adphymutex@14016000mediatek,mt8183-disp-mutex` D{c_`larb@14017000mediatek,mt8183-smi-larbpx-,,Dapbsmi3smi@14019000mediatek,mt8183-smi-common ,,,,apbsmigals0gals1D-mdp3-ccorr@1401c000mediatek,mt8183-mdp3-ccorrc_{1,+syscon@15020000mediatek,mt8183-imgsyssyscon/larb@15021000mediatek,mt8183-smi-larbx-/ / , apbsmigalsD 8larb@1502f000mediatek,mt8183-smi-larbx-//,  apbsmigalsD 5syscon@16000000mediatek,mt8183-vdecsyssysconblarb@16010000mediatek,mt8183-smi-larbx-bbapbsmiD 4syscon@17000000mediatek,mt8183-vencsyssysconclarb@17010000mediatek,mt8183-smi-larbx-ccapbsmiD 7venc_jpg@17030000+mediatek,mt8183-jpgencmediatek,mtk-jpgenc ``D cjpgencsyscon@19000000 mediatek,mt8183-ipu_connsyscon0syscon@19010000mediatek,mt8183-ipu_adlsysconsyscon@19180000!mediatek,mt8183-ipu_core0sysconsyscon@19280000!mediatek,mt8183-ipu_core1syscon(syscon@1a000000mediatek,mt8183-camsyssyscon.larb@1a001000mediatek,mt8183-smi-larbx-.., apbsmigalsD9larb@1a002000mediatek,mt8183-smi-larb x-. . , apbsmigalsD6memory@40000000memory@chosenserial0:921600n8reserved-memory+?scp_mem_regionshared-dma-poolP1ntc@0murata,ncp03wf104w@p@ compatibleinterrupt-parent#address-cells#size-cellsmodeli2c0i2c1i2c2i2c3i2c4i2c5i2c6i2c7i2c8i2c9i2c10i2c11ovl0ovl-2l0ovl-2l1rdma0rdma1serial0opp-sharedphandleopp-hzopp-microvoltrequired-oppsclocksclock-namesoperating-points-v2proc-supplycpudevice_typeregenable-methodcapacity-dmips-mhzcpu-idle-statesdynamic-power-coefficient#cooling-cellsmediatek,ccientry-methodlocal-timer-stoparm,psci-suspend-paramentry-latency-usexit-latency-usmin-residency-usinterrupts#clock-cellsclock-divclock-multclock-output-namesclock-frequencyrangesstatus#interrupt-cellsinterrupt-controlleraffinity#reset-cellsreg-namesgpio-controller#gpio-cellsgpio-rangespinmuxmediatek,pull-up-advmediatek,drive-strength-advbias-disableinput-enablebias-pull-upbias-pull-downdrive-strengthoutput-high#power-domain-cellsmediatek,infracfgdomain-supplymediatek,smimediatek,dmic-moderegulator-nameregulator-min-microvoltregulator-max-microvoltregulator-ramp-delayregulator-enable-ramp-delayregulator-always-onregulator-allowed-modeslinux,keycodeswakeup-sourcememory-regionmediatek,larbs#iommu-cells#mbox-cells#io-channel-cellspinctrl-namespinctrl-0mediatek,pad-selectnvmem-cellsnvmem-cell-names#thermal-sensor-cellsresetsmediatek,auxadcmediatek,apmixedsyspolling-delay-passivepolling-delaythermal-sensorssustainable-powertemperaturehysteresistripcooling-devicecontributionpower-domains#pwm-cellsphysmediatek,syscon-wakeupreset-namespinctrl-1bus-widthmax-frequencycap-mmc-highspeedmmc-hs200-1_8vmmc-hs400-1_8vcap-mmc-hw-resetno-sdiono-sdhs400-ds-delayvmmc-supplyvqmmc-supplyassigned-clocksassigned-clock-parentsnon-removablecap-sd-highspeedsd-uhs-sdr50sd-uhs-sdr104cap-sdio-irqno-mmckeep-power-in-suspend#phy-cellsmediatek,discthinterrupt-namespower-domain-namesmali-supplysram-supplymboxesmediatek,gce-client-regmediatek,gce-eventsiommusmediatek,rdma-fifo-sizephy-namesstdout-pathno-mappullup-uvpullup-ohmpulldown-ohmio-channels