8\($%mediatek,mt8195-demomediatek,mt8195 +7MediaTek MT8195 demo boardaliases=/soc/mailbox@10320000B/soc/mailbox@10330000G/soc/serial@11001100cpus+cpu@0Ocpuarm,cortex-a55[_pscimec3@4 cpu@100Ocpuarm,cortex-a55[_pscimec3@4 cpu@200Ocpuarm,cortex-a55[_pscimec3@4 cpu@300Ocpuarm,cortex-a55[_pscimec3@4 cpu@400Ocpuarm,cortex-a78[_pscimf cpu@500Ocpuarm,cortex-a78[_pscimfcpu@600Ocpuarm,cortex-a78[_pscimfcpu@700Ocpuarm,cortex-a78[_pscimfcpu-mapcluster0core0 core1 core2 core3 core4 core5core6core7idle-statespscicpu-off-larm,idle-state2&_6Dcpu-off-barm,idle-state-&6cluster-off-larm,idle-state7&6Hcluster-off-barm,idle-state2&6l2-cache0cachel2-cache1cachel3-cachecachedsu-pmu arm,dsu-pmuG R dmic-codec dmic-codecWd2mt8195-soundt disabledfixed-factor-clock-13mfixed-factor-clockclk13m&oscillator-26m fixed-clockclk26moscillator-32k fixed-clockclk32kperformance-controller@11bc10mediatek,cpufreq-hw [ 0 pmu-a55arm,cortex-a55-pmu Gpmu-a78arm,cortex-a78-pmu Gpsci arm,psci-1.0fsmctimerarm,armv8-timer @G   soc+ simple-businterrupt-controller@c000000 arm,gic-v3  [   G ppi-partitionsinterrupt-partition-0' interrupt-partition-1' syscon@10000000 mediatek,mt8195-topckgensyscon[syscon@10001000.mediatek,mt8195-infracfg_aosysconsimple-mfd[0syscon@10003000mediatek,mt8195-pericfgsyscon[00pinctrl@10005000mediatek,mt8195-pinctrl[PB=iocfg0iocfg_bmiocfg_bliocfg_briocfg_lmiocfg_rbiocfg_tleintGWcGgpio-keys-pinsxpinsojvi2c6-pins?pinsommc0-default-pins3pins-clkozfpins-cmd-dat$o~}|{wvutyvepins-rstoxemmc0-uhs-pins4pins-clkozfpins-cmd-dat$o~}|{wvutyvepins-dsofpins-rstoxemmc1-default-pins7pins-clkoofpins-cmd-datonpqrsvepins-insertommc1-uhs-pins8pins-clkoofpins-cmd-datonpqrsveuart0-pins,pinsobcuart1-pins-pinsofgsyscon@10006000)mediatek,mt8195-scpsyssysconsimple-mfd[`power-controller!mediatek,mt8195-power-controller+(power-domain@8[+power-domain@9[ mfg+power-domain@10[ power-domain@11[ power-domain@12[ power-domain@13[ power-domain@14[power-domain@15[ @AK   vppsysvppsys1vppsys2vppsys3vppsys4vppsys5vppsys6vppsys7vppsys0-0vppsys0-1vppsys0-2vppsys0-3vppsys0-4vppsys0-5vppsys0-6vppsys0-7vppsys0-8vppsys0-9vppsys0-10vppsys0-11vppsys0-12vppsys0-13vppsys0-14vppsys0-15vppsys0-16vppsys0-17vppsys0-18+power-domain@24[vdec1-0power-domain@27[power-domain@16[8$%&'()Dvdosys0vdosys0-0vdosys0-1vdosys0-2vdosys0-3vdosys0-4vdosys0-5+power-domain@17[vppsys1vppsys1-0vppsys1-1power-domain@22[ $wepsys-0wepsys-1wepsys-2wepsys-3power-domain@23[vdec0-0power-domain@25[ vdec2-0power-domain@26[power-domain@18[ !!!&vdosys1vdosys1-0vdosys1-1vdosys1-2+power-domain@19[power-domain@20[power-domain@21[Qhdmi_txpower-domain@28[""  img-0img-1+power-domain@29[power-domain@30["#ipeipe-0ipe-1power-domain@31[($$$$$cam-0cam-1cam-2cam-3cam-4+power-domain@32[ power-domain@33[!power-domain@34["power-domain@0[power-domain@1[power-domain@2[power-domain@3[power-domain@4[57csi_rx_topcsi_rx_top1power-domain@5[% etherpower-domain@6[Xn adspadsp1+power-domain@7[ g"n2audioaudio1audio2audio3watchdog@10007000mediatek,mt8195-wdt[p0+syscon@1000c000"mediatek,mt8195-apmixedsyssyscon[timer@10017000,mediatek,mt8195-timermediatek,mt6765-timer[pG &pwrap@10024000mediatek,mt8195-pwrapsyscon[@=pwrapG spiwrap$pmicmediatek,mt6359 mt6359codecregulatorsbuck_vs13vs1B 5Z!rbuck_vgpu113vgpu11BZ7r buck_vmodem3vmodemBZ*rbuck_vpu3vpuBZ7r buck_vcore3vcoreBZ r buck_vs23vs2B 5Zjrbuck_vpa3vpaB Z7r,buck_vproc23vproc2BZ7Lr buck_vproc13vproc1BZ7Lr buck_vcore_sshub 3vcore_sshubBZ7buck_vgpu11_sshub 3vgpu11_sshubBZ7ldo_vaud183vaud18Bw@Zw@rldo_vsim13vsim1BZ/M`ldo_vibr3vibrBOZ2Zldo_vrf123vrf12BZ ldo_vusb3vusbB-Z-r1ldo_vsram_proc2 3vsram_proc2B ZLrldo_vio183vio18BZrldo_vcamio3vcamioBZldo_vcn183vcn18Bw@Zw@rldo_vfe283vfe28B*Z*rxldo_vcn133vcn13B Z ldo_vcn33_1_bt 3vcn33_1_btB*Z5gldo_vcn33_1_wifi 3vcn33_1_wifiB*Z5gldo_vaux183vaux18Bw@Zw@rldo_vsram_others 3vsram_othersB Zrldo_vefuse3vefuseBZldo_vxo223vxo22Bw@Z!ldo_vrfck3vrfckB`Zldo_vrfck_13vrfckBZjldo_vbif283vbif28B*Z*rldo_vio283vio28B*Z2Zldo_vemc3vemcB,@ Z2Zldo_vemc_13vemcB&%Z2Z5ldo_vcn33_2_bt 3vcn33_2_btB*Z5gldo_vcn33_2_wifi 3vcn33_2_wifiB*Z5gldo_va123va12BOZ ldo_va093va09B 5ZOldo_vrf183vrf18BZPldo_vsram_md 3vsram_mdB Z*rldo_vufs3vufsBZ6ldo_vm183vm18BZldo_vbbck3vbbckBZOldo_vsram_proc1 3vsram_proc1B ZLrldo_vsim23vsim2BZ/M`ldo_vsram_others_sshub3vsram_others_sshubB Zmt6359rtcmediatek,mt6358-rtcspmi@10027000mediatek,mt8195-spmi [p =pmifspmimstE(pmif_sys_ckpmif_tmr_ckspmimst_clk_mux$infra-iommu@10315000mediatek,mt8195-iommu-infra[1PPPGmailbox@10320000mediatek,mt8195-gce[2@Ggmailbox@10330000mediatek,mt8195-gce[3@Gscp@10500000mediatek,mt8195-scp0[Prp=sramcfgl1tcmG disabledclock-controller@10720000mediatek,mt8195-scp_adsp[r'dsp@10803000mediatek,mt8195-dsp [0 =cfgsram,Xn'#Kadsp_selclk26m_ckaudio_local_busmainpll_d7_d2scp_adsp_audiodspaudio_h(rxtx)* disabledmailbox@10816000mediatek,mt8195-adsp-mbox[`G)mailbox@10817000mediatek,mt8195-adsp-mbox[pG*mt8195-afe-pcm@10890000mediatek,mt8195-audio[(G6+ !audiosysg"#neabcd2'clk26mapll1_ckapll2_ckapll12_div0apll12_div1apll12_div2apll12_div3apll12_div9a1sys_hp_selaud_intbus_selaudio_h_selaudio_local_bus_seldptx_m_seli2so1_m_seli2so2_m_seli2si1_m_seli2si2_m_selinfra_ao_audio_26m_bscp_adsp_audiodsp disabledserial@11001100*mediatek,mt8195-uartmediatek,mt6577-uart[G  baudbusokay-default;,serial@11001200*mediatek,mt8195-uartmediatek,mt6577-uart[G  baudbusokay-default;-serial@11001300*mediatek,mt8195-uartmediatek,mt6577-uart[G  baudbus disabledserial@11001400*mediatek,mt8195-uartmediatek,mt6577-uart[G  baudbus disabledserial@11001500*mediatek,mt8195-uartmediatek,mt6577-uart[G  baudbus disabledserial@11001600*mediatek,mt8195-uartmediatek,mt6577-uart[G  baudbus disabledauxadc@11002000.mediatek,mt8195-auxadcmediatek,mt8173-auxadc[ mainE disabledsyscon@11003000"mediatek,mt8195-pericfg_aosyscon[0%spi@1100a000(mediatek,mt8195-spimediatek,mt6765-spi+[Gparent-clksel-clkspi-clk disabledspi@11010000(mediatek,mt8195-spimediatek,mt6765-spi+[G3parent-clksel-clkspi-clk disabledspi@11012000(mediatek,mt8195-spimediatek,mt6765-spi+[ G4parent-clksel-clkspi-clk disabledspi@11013000(mediatek,mt8195-spimediatek,mt6765-spi+[0G5parent-clksel-clkspi-clk disabledspi@11018000(mediatek,mt8195-spimediatek,mt6765-spi+[G<parent-clksel-clkspi-clk disabledspi@11019000(mediatek,mt8195-spimediatek,mt6765-spi+[G=parent-clksel-clkspi-clk disabledspi@1101d000mediatek,mt8195-spi-slave[GRspi disabledspi@1101e000mediatek,mt8195-spi-slave[GSspi disabledusb@11200000'mediatek,mt8195-xhcimediatek,mtk-xhci [  > =macippcGW./,-$/B$sys_ckref_ckmcu_ckdma_ckxhci_ck \0gsokay12mmc@11230000(mediatek,mt8195-mmcmediatek,mt8183-mmc [#Gsourcehclksource_cgokay-defaultstate_uhs;34  L5'64mmc@11240000(mediatek,mt8195-mmcmediatek,mt8183-mmc [$G$sourcehclksource_cgokay-defaultstate_uhs;78 B K\i9':mmc@11250000(mediatek,mt8195-mmcmediatek,mt8183-mmc [%G Isourcehclksource_cg  disabledusb@11290000'mediatek,mt8195-xhcimediatek,mtk-xhci [))> =macippcGW;./$%%$sys_ckref_ckmcu_ckdma_ckxhci_ck \0hsokay1usb@112a0000'mediatek,mt8195-xhcimediatek,mtk-xhci [**> =macippcGW<01 %%$sys_ckref_ckmcu_ckdma_ckxhci_ck \0isokay1usb@112b0000'mediatek,mt8195-xhcimediatek,mtk-xhci [++> =macippcGW=23 %% $sys_ckref_ckmcu_ckdma_ckxhci_ck \0jsokay1spi@1132c000(mediatek,mt8195-normediatek,mt8173-nor[2G9o%% spisfaxi+ disabledefuse@11c10000%mediatek,mt8195-efusemediatek,efuse[+usb3-tx-imp@184,1[wGusb3-rx-imp@184,2[wFusb3-intr@185[wEusb3-tx-imp@186,1[wDusb3-rx-imp@186,2[wCusb3-intr@187[wBusb2-intr-p0@188,1[wusb2-intr-p1@188,2[wusb2-intr-p2@189,1[wusb2-intr-p3@189,2[wt-phy@11c40000.mediatek,mt8195-tphymediatek,generic-tphy-v3+okayusb-phy@0[ref|<t-phy@11c50000.mediatek,mt8195-tphymediatek,generic-tphy-v3+okayusb-phy@0[ref|=i2c@11d00000(mediatek,mt8195-i2cmediatek,mt8192-i2c ["G>; maindma+ disabledi2c@11d01000(mediatek,mt8195-i2cmediatek,mt8192-i2c ["G>; maindma+okay;?-defaultpmic@34mediatek,mt6360[4 eIRQBchargermediatek,mt6360-chg@usb-otg-vbus-regulator usb-otg-vbus 3usb-otg-vbusBC(ZX2regulatormediatek,mt6360-regulator@buck1BUCK1 3mt6360,buck1BZ  buck2BUCK2 3mt6360,buck2BZ  @ldo1LDO1 3mt6360,ldo1BOZ6ldo2LDO2 3mt6360,ldo2BOZ6ldo3LDO3 3mt6360,ldo3BOZ6:ldo5LDO5 3mt6360,ldo5B)2Z69ldo6LDO6 3mt6360,ldo6B Z ldo7LDO7 3mt6360,ldo7B Z i2c@11d02000(mediatek,mt8195-i2cmediatek,mt8192-i2c [ "G>; maindma+ disabledclock-controller@11d03000mediatek,mt8195-imp_iic_wrap_s[0>i2c@11e00000(mediatek,mt8195-i2cmediatek,mt8192-i2c ["GA; maindma+ disabledi2c@11e01000(mediatek,mt8195-i2cmediatek,mt8192-i2c ["GA; maindma+ disabledi2c@11e02000(mediatek,mt8195-i2cmediatek,mt8192-i2c [ "GA; maindma+ disabledi2c@11e03000(mediatek,mt8195-i2cmediatek,mt8192-i2c [0"GA; maindma+ disabledi2c@11e04000(mediatek,mt8195-i2cmediatek,mt8192-i2c [@"GA; maindma+ disabledclock-controller@11e05000mediatek,mt8195-imp_iic_wrap_w[PAt-phy@11e30000.mediatek,mt8195-tphymediatek,generic-tphy-v3+(okayusb-phy@0[  refda_ref|;usb-phy@700[ refda_ref BCDintrrx_imptx_imp|t-phy@11e40000.mediatek,mt8195-tphymediatek,generic-tphy-v3+okayusb-phy@0[  refda_ref|.usb-phy@700[ refda_ref EFGintrrx_imptx_imp|/ufs-phy@11fa0000.mediatek,mt8195-ufsphymediatek,mt8183-ufsphy[ unipromp| disabledclock-controller@13fbf000mediatek,mt8195-mfgcfg[clock-controller@14000000mediatek,mt8195-vppsys0[smi@14010000mediatek,mt8195-smi-sub-common[apbsmigals0H(Ismi@14011000mediatek,mt8195-smi-sub-common[apbsmigals0H(esmi@14012000mediatek,mt8195-smi-common-vpp[  apbsmigals0gals1(Hlarb@14013000mediatek,mt8195-smi-larb[0Iapbsmi(Liommu@14018000mediatek,mt8195-iommu-vpp[8JKLMNOPQRSTUVWGRbclk(clock-controller@14e00000mediatek,mt8195-wpesys[clock-controller@14e02000mediatek,mt8195-wpesys_vpp0[ clock-controller@14e03000mediatek,mt8195-wpesys_vpp1[0larb@14e04000mediatek,mt8195-smi-larb[@Xapbsmi(mlarb@14e05000mediatek,mt8195-smi-larb[PH apbsmigals(Nclock-controller@14f00000mediatek,mt8195-vppsys1[larb@14f02000mediatek,mt8195-smi-larb[ X apbsmigals(llarb@14f03000mediatek,mt8195-smi-larb[0I apbsmigals(Mclock-controller@15000000mediatek,mt8195-imgsys["larb@15001000mediatek,mt8195-smi-larb[ Y"""  apbsmigals(nsmi@15002000mediatek,mt8195-smi-sub-common[ ""apbsmigals0H(\smi@15003000mediatek,mt8195-smi-sub-common[0""" apbsmigals0X(Yclock-controller@15110000 mediatek,mt8195-imgsys1_dip_top[Zlarb@15120000mediatek,mt8195-smi-larb[ Y"Zapbsmi(oclock-controller@15130000mediatek,mt8195-imgsys1_dip_nr[clock-controller@15220000mediatek,mt8195-imgsys1_wpe["[larb@15230000mediatek,mt8195-smi-larb[# Y"[apbsmi(pclock-controller@15330000mediatek,mt8195-ipesys[3#larb@15340000mediatek,mt8195-smi-larb[4 \##apbsmi(Oclock-controller@16000000mediatek,mt8195-camsys[$larb@16001000mediatek,mt8195-smi-larb[ ]$$$ apbsmigals(qlarb@16002000mediatek,mt8195-smi-larb[ ^$$apbsmi(Psmi@16004000mediatek,mt8195-smi-sub-common[@$$$apbsmigals0X(]smi@16005000mediatek,mt8195-smi-sub-common[P$$apbsmigals0H(^larb@16012000mediatek,mt8195-smi-larb[ ^__apbsmi( Qlarb@16013000mediatek,mt8195-smi-larb[0]``apbsmi( rlarb@16014000mediatek,mt8195-smi-larb[@^aaapbsmi(!Wlarb@16015000mediatek,mt8195-smi-larb[P]bbapbsmi(!wclock-controller@1604f000mediatek,mt8195-camsys_rawa[_clock-controller@1606f000mediatek,mt8195-camsys_yuva[`clock-controller@1608f000mediatek,mt8195-camsys_rawb[aclock-controller@160af000mediatek,mt8195-camsys_yuvb[ bclock-controller@16140000mediatek,mt8195-camsys_mraw[clarb@16141000mediatek,mt8195-smi-larb[]$c$ apbsmigals("vlarb@16142000mediatek,mt8195-smi-larb[ ^ccapbsmi("Vclock-controller@17200000mediatek,mt8195-ccusys[ dlarb@17201000mediatek,mt8195-smi-larb[ ^ddapbsmi(Rlarb@1800d000mediatek,mt8195-smi-larb[Xapbsmi(ularb@1800e000mediatek,mt8195-smi-larb[eapbsmi(Uclock-controller@1800f000mediatek,mt8195-vdecsys_soc[larb@1802e000mediatek,mt8195-smi-larb[Xapbsmi(tclock-controller@1802f000mediatek,mt8195-vdecsys[larb@1803e000mediatek,mt8195-smi-larb[e apbsmi(Tclock-controller@1803f000mediatek,mt8195-vdecsys_core1[ clock-controller@190f3000mediatek,mt8195-apusys_pll[0clock-controller@1a000000mediatek,mt8195-vencsys[flarb@1a010000mediatek,mt8195-smi-larb[Xffapbsmi(sclock-controller@1b000000mediatek,mt8195-vencsys_core1[hsyscon@1c01a0005mediatek,mt8195-vdosys0mediatek,mt8195-mmsyssyscon[ glarb@1b010000mediatek,mt8195-smi-larb[Hhh  apbsmigals(Sovl@1c0000002mediatek,mt8195-disp-ovlmediatek,mt8183-disp-ovl[G|(i&grdma@1c002000mediatek,mt8195-disp-rdma[ G~(i&g color@1c0030006mediatek,mt8195-disp-colormediatek,mt8173-disp-color[0G(&g0ccorr@1c0040006mediatek,mt8195-disp-ccorrmediatek,mt8192-disp-ccorr[@G(&g@aal@1c0050002mediatek,mt8195-disp-aalmediatek,mt8183-disp-aal[PG(&gPgamma@1c0060006mediatek,mt8195-disp-gammamediatek,mt8183-disp-gamma[`G(&g`dither@1c0070008mediatek,mt8195-disp-dithermediatek,mt8183-disp-dither[pG( &gpdsc@1c009000mediatek,mt8195-disp-dsc[G(&gmerge@1c014000mediatek,mt8195-disp-merge[@G(&g@mutex@1c016000mediatek,mt8195-disp-mutex[`G(>Ularb@1c018000mediatek,mt8195-smi-larb[X((  apbsmigals(jlarb@1c019000mediatek,mt8195-smi-larb[H(  apbsmigals(Jsyscon@1c100000mediatek,mt8195-vdosys1syscon[!smi@1c01b000mediatek,mt8195-smi-common-vdo[ %&)$apbsmigals0gals1(Xiommu@1c01f000mediatek,mt8195-iommu-vdo[8jklmnopqrstuvwG'bclk(ilarb@1c102000mediatek,mt8195-smi-larb[ X!!! apbsmigals(klarb@1c103000mediatek,mt8195-smi-larb[0H!!  apbsmigals(KchosenRserial0:921600n8firmwareopteelinaro,optee-tzfsmcgpio-keys gpio-keys-default;xkey-0 Ej ^volume_updssomemory@40000000Omemory[@reserved-memory+secmon@54600000[T` optee@43200000[C  compatibleinterrupt-parent#address-cells#size-cellsmodelgce0gce1serial0device_typeregenable-methodperformance-domainsclock-frequencycapacity-dmips-mhzcpu-idle-statesnext-level-cache#cooling-cellsphandlecpuentry-methodarm,psci-suspend-paramlocal-timer-stopentry-latency-usexit-latency-usmin-residency-usinterruptscpusnum-channelswakeup-delay-msmediatek,platformstatus#clock-cellsclocksclock-divclock-multclock-output-names#performance-domain-cellsranges#interrupt-cells#redistributor-regionsinterrupt-controlleraffinity#reset-cellsreg-namesgpio-controller#gpio-cellsgpio-rangespinmuxinput-enablebias-pull-updrive-strengthbias-pull-down#power-domain-cellsclock-namesmediatek,infracfgmediatek,disable-extrstassigned-clocksassigned-clock-parentsinterrupts-extendedregulator-nameregulator-min-microvoltregulator-max-microvoltregulator-enable-ramp-delayregulator-always-onregulator-ramp-delayregulator-allowed-modes#iommu-cells#mbox-cellspower-domainsmbox-namesmboxesmediatek,topckgenresetsreset-namespinctrl-namespinctrl-0#io-channel-cellsphysmediatek,syscon-wakeupwakeup-sourcevusb33-supplyvbus-supplypinctrl-1bus-widthmax-frequencycap-mmc-highspeedmmc-hs200-1_8vmmc-hs400-1_8vcap-mmc-hw-resetno-sdiono-sdhs400-ds-delayvmmc-supplyvqmmc-supplynon-removablecd-gpioscap-sd-highspeedsd-uhs-sdr50sd-uhs-sdr104bits#phy-cellsinterrupt-namesrichtek,vinovp-microvoltregulator-compatibleLDO_VIN3-supplynvmem-cellsnvmem-cell-namesmediatek,smimediatek,larb-idmediatek,larbsiommusmediatek,gce-client-regmediatek,gce-eventsstdout-pathlabellinux,codedebounce-intervalno-map