k 8d\(d$.rockchip,px5-evbrockchip,px5rockchip,rk3368 +7Rockchip PX5 EVBaliases=/ethernet@ff290000G/i2c@ff650000L/i2c@ff660000Q/i2c@ff140000V/i2c@ff150000[/i2c@ff160000`/i2c@ff170000e/serial@ff180000m/serial@ff190000u/serial@ff690000}/serial@ff1b0000/serial@ff1c0000/spi@ff110000/spi@ff120000/spi@ff130000/mmc@ff0c0000/mmc@ff0f0000cpus+cpu-mapcluster0core0core1core2core3cluster1core0core1core2core3 cpu@0cpuarm,cortex-a53pscicpu@1cpuarm,cortex-a53pscicpu@2cpuarm,cortex-a53pscicpu@3cpuarm,cortex-a53psci cpu@100cpuarm,cortex-a53pscicpu@101cpuarm,cortex-a53pscicpu@102cpuarm,cortex-a53pscicpu@103cpuarm,cortex-a53psciarm-pmuarm,armv8-pmuv3`pqrstuvw  psci arm,psci-0.2smctimerarm,armv8-timer0   oscillator fixed-clockn6 xin24m Fmmc@ff0c00000rockchip,rk3368-dw-mshcrockchip,rk3288-dw-mshc @-р ;  D r vBbiuciuciu-driveciu-sampleN Y `resetlokays}default Z mmc@ff0d00000rockchip,rk3368-dw-mshcrockchip,rk3288-dw-mshc @-р ;  E s wBbiuciuciu-driveciu-sampleN !Y `reset ldisabledmmc@ff0f00000rockchip,rk3368-dw-mshcrockchip,rk3288-dw-mshc@-р ;  G u yBbiuciuciu-driveciu-sampleN #Y `resetlokays}р#28default  saradc@ff100000rockchip,saradc $F; I [Bsaradcapb_pclkY W `saradc-apb ldisabledspi@ff110000(rockchip,rk3368-spirockchip,rk3066-spi; A RBspiclkapb_pclk ,default+ ldisabledspi@ff120000(rockchip,rk3368-spirockchip,rk3066-spi; B SBspiclkapb_pclk -default+ ldisabledspi@ff130000(rockchip,rk3368-spirockchip,rk3066-spi; C TBspiclkapb_pclk )default !+ ldisabledi2c@ff140000(rockchip,rk3368-i2crockchip,rk3288-i2c >+Bi2c; Ndefault"lokaytouchscreen@40silead,gsl1680@ # X#d wi2c@ff150000(rockchip,rk3368-i2crockchip,rk3288-i2c ?+Bi2c; Odefault$ ldisabledi2c@ff160000(rockchip,rk3368-i2crockchip,rk3288-i2c @+Bi2c; Pdefault% ldisabledi2c@ff170000(rockchip,rk3368-i2crockchip,rk3288-i2c A+Bi2c; Qdefault& ldisabledserial@ff180000&rockchip,rk3368-uartsnps,dw-apb-uartn6; M UBbaudclkapb_pclk 7 ldisabledserial@ff190000&rockchip,rk3368-uartsnps,dw-apb-uartn6; N VBbaudclkapb_pclk 8 ldisabledserial@ff1b0000&rockchip,rk3368-uartsnps,dw-apb-uartn6; P XBbaudclkapb_pclk : ldisabledserial@ff1c0000&rockchip,rk3368-uartsnps,dw-apb-uartn6; Q YBbaudclkapb_pclk ;lokaydma-controller@ff250000arm,pl330arm,primecell%@;  Bapb_pclkthermal-zonescpu-thermald'tripscpu_alert0%$1passive(cpu_alert1%81passive)cpu_crit%s1 criticalcooling-mapsmap0<(0Amap1<)0A gpu-thermald'tripsgpu_alert0%81passive*gpu_crit%81 criticalcooling-mapsmap0<*0Atsadc@ff280000rockchip,rk3368-tsadc( %; H ZBtsadcapb_pclkY  `tsadc-apbinitdefaultsleep+P,Z+dzslokay'ethernet@ff290000rockchip,rk3368-gmac) macirq-8;  f g c ]MBstmmacethmac_clk_rxmac_clk_txclk_mac_refclk_mac_refoutaclk_macpclk_mac ldisabledusb@ff500000 generic-ehciP ; lokayusb@ff5800002rockchip,rk3368-usbrockchip,rk3066-usbsnps,dwc2X ; Botgotg @@ lokaydma-controller@ff600000arm,pl330arm,primecell`@;  Bapb_pclkGi2c@ff650000(rockchip,rk3368-i2crockchip,rk3288-i2ce; LBi2c <default.+lokaypmic@1brockchip,rk808 /default0192E2Q2]2i2u2222 xin32krk808-clkout2 regulatorsDCDC_REG1 ``vdd_cpuDCDC_REG2 ``vdd_logDCDC_REG3vcc_ddrDCDC_REG42Z2Zvcc_ioLDO_REG1w@w@ vcc18_flashLDO_REG22Z2Zvcca_33LDO_REG3B@B@vdd_10LDO_REG42Z2Zavdd_33LDO_REG5w@2Z vccio_sdLDO_REG6B@B@ vdd10_lcdLDO_REG7w@w@vcc_18LDO_REG8w@w@ vcc18_lcdSWITCH_REG1vcc_sdSWITCH_REG2 vcc33_lcdi2c@ff660000(rockchip,rk3368-i2crockchip,rk3288-i2cf =+Bi2c; Mdefault3lokayaccelerometer@18 bosch,bma250 4pwm@ff680000(rockchip,rk3368-pwmrockchip,rk3288-pwmh%default5; _ ldisabledpwm@ff680010(rockchip,rk3368-pwmrockchip,rk3288-pwmh%default6; _ ldisabledpwm@ff680020(rockchip,rk3368-pwmrockchip,rk3288-pwmh %; _ ldisabledpwm@ff680030(rockchip,rk3368-pwmrockchip,rk3288-pwmh0%default7; _ ldisabledserial@ff690000&rockchip,rk3368-uartsnps,dw-apb-uarti; O WBbaudclkapb_pclk 9default8 ldisabledmbox@ff6b0000rockchip,rk3368-mailboxk0; E Bpclk_mailbox0 ldisabledpower-management@ff730000&rockchip,rk3368-pmusysconsimple-mfdspower-controller!rockchip,rk3368-power-controller<+Jpower-domain@12 ;       c h g n o r s f d d h i l k j n m$P9:;<=>?@A<power-domain@14 ;  o p PBCD<power-domain@16; @PE<syscon@ff738000)rockchip,rk3368-pmugrfsysconsimple-mfdsKio-domains&rockchip,rk3368-pmu-io-voltage-domain ldisabledreboot-modesyscon-reboot-modeW^RBjRBxRB RBclock-controller@ff760000rockchip,rk3368-cruv;FBxin24m-  syscon@ff770000&rockchip,rk3368-grfsysconsimple-mfdw-io-domains"rockchip,rk3368-io-voltage-domain ldisabledwatchdog@ff800000 rockchip,rk3368-wdtsnps,dw-wdt; p Olokaytimer@ff810000,rockchip,rk3368-timerrockchip,rk3288-timer  B; a U Bpclktimerspdif@ff880000rockchip,rk3368-spdif 6; S  BmclkhclkGtxdefaultH ldisabledi2s-2ch@ff890000(rockchip,rk3368-i2srockchip,rk3066-i2s (Bi2s_clki2s_hclk; T GGtxrx ldisabledi2s-8ch@ff898000(rockchip,rk3368-i2srockchip,rk3066-i2s 5Bi2s_clki2s_hclk; R GGtxrxdefaultI ldisablediommu@ff900800rockchip,iommu ;  BaclkifaceJ  ldisablediommu@ff914000rockchip,iommu @P ;  BaclkifaceJ  ldisablediommu@ff930300rockchip,iommu ;  BaclkifaceJ  ldisablediommu@ff9a0440rockchip,iommu @@@ ;  Baclkiface ldisablediommu@ff9a0800rockchip,iommu  ;  Baclkiface ldisabledqos@ffad0000rockchip,rk3368-qossyscon 9qos@ffad0080rockchip,rk3368-qossyscon :qos@ffad0100rockchip,rk3368-qossyscon ;qos@ffad0180rockchip,rk3368-qossyscon <qos@ffad0200rockchip,rk3368-qossyscon =qos@ffad0280rockchip,rk3368-qossyscon >qos@ffad0300rockchip,rk3368-qossyscon ?qos@ffad0380rockchip,rk3368-qossyscon @qos@ffad0400rockchip,rk3368-qossyscon Aqos@ffae0000rockchip,rk3368-qossyscon Bqos@ffae0100rockchip,rk3368-qossyscon Cqos@ffae0180rockchip,rk3368-qossyscon Dqos@ffaf0000rockchip,rk3368-qossyscon Eefuse@ffb00000rockchip,rk3368-efuse +; q Bpclk_efusecpu-leakage@17temp-adjust@1finterrupt-controller@ffb71000 arm,gic-400@ @ `   pinctrlrockchip,rk3368-pinctrl- K+gpio@ff750000rockchip,gpio-banku; @ Q 0/gpio@ff780000rockchip,gpio-bankx; A R 0gpio@ff790000rockchip,gpio-banky; B S 04gpio@ff7a0000rockchip,gpio-bankz; C T 0#pcfg-pull-up<Mpcfg-pull-downIpcfg-pull-noneXLpcfg-pull-none-12maXe Nemmcemmc-clktLemmc-cmdtMemmc-pwrtMemmc-bus1tMemmc-bus4@tMMMMemmc-bus8tMMMMMMMMgmacrgmii-pinstLLLN N NNN NLLLLLLrmii-pinstLLLN N NLLLLi2c0i2c0-xfer tLL.i2c1i2c1-xfer tLL3i2c2i2c2-xfer t LL"i2c3i2c3-xfer tLL$i2c4i2c4-xfer tLL%i2c5i2c5-xfer tLL&i2si2s-8ch-bust L LLLLLLLLIpwm0pwm0-pintL5pwm1pwm1-pintL6pwm3pwm3-pintL7sdio0sdio0-bus1tMsdio0-bus4@tMMMMsdio0-cmdtMsdio0-clktLsdio0-cdtMsdio0-wptMsdio0-pwrtMsdio0-bkpwrtMsdio0-inttMsdmmcsdmmc-clkt L sdmmc-cmdt M sdmmc-cdt Msdmmc-bus1tMsdmmc-bus4@tMMMM spdifspdif-txtLHspi0spi0-clktMspi0-cs0tMspi0-cs1tMspi0-txtMspi0-rxtMspi1spi1-clktMspi1-cs0tMspi1-cs1tMspi1-rxtMspi1-txtMspi2spi2-clkt Mspi2-cs0t M!spi2-rxt M spi2-txt Mtsadcotp-pintL+otp-outtL,uart0uart0-xfer tMLuart0-ctstLuart0-rtstLuart1uart1-xfer tMLuart1-ctstLuart1-rtstLuart2uart2-xfer tML8uart3uart3-xfer tMLuart3-ctstLuart3-rtstLuart4uart4-xfer tMLuart4-ctstLuart4-rtstLkeyspwr-keytLOpmicpmic-sleeptL1pmic-inttM0chosenserial4:115200n8memory@0@memorygpio-keys gpio-keysdefaultOkey-power ^/ GPIO Powertvcc-sys-regulatorregulator-fixedvcc_sysLK@LK@2 compatibleinterrupt-parent#address-cells#size-cellsmodelethernet0i2c0i2c1i2c2i2c3i2c4i2c5serial0serial1serial2serial3serial4spi0spi1spi2mmc0mmc1cpudevice_typeregenable-method#cooling-cellsphandleinterruptsinterrupt-affinityclock-frequencyclock-output-names#clock-cellsmax-frequencyclocksclock-namesfifo-depthresetsreset-namesstatusbus-widthcap-mmc-highspeedcap-sd-highspeedcard-detect-delayno-sdiosd-uhs-sdr12sd-uhs-sdr25pinctrl-namespinctrl-0rockchip,default-sample-phasevmmc-supplyvqmmc-supplymmc-hs200-1_8vno-sdnon-removable#io-channel-cellspower-gpiostouchscreen-size-xtouchscreen-size-ysilead,max-fingersreg-shiftreg-io-width#dma-cellsarm,pl330-broken-no-flushparm,pl330-periph-burstpolling-delay-passivepolling-delaythermal-sensorstemperaturehysteresistripcooling-devicepinctrl-1pinctrl-2#thermal-sensor-cellsrockchip,hw-tshut-temprockchip,hw-tshut-moderockchip,hw-tshut-polarityinterrupt-namesrockchip,grfdr_modeg-np-tx-fifo-sizeg-rx-fifo-sizeg-tx-fifo-sizerockchip,system-power-controllervcc1-supplyvcc2-supplyvcc3-supplyvcc4-supplyvcc6-supplyvcc7-supplyvcc8-supplyvcc9-supplyvcc10-supplyvcc11-supplyvcc12-supplyregulator-always-onregulator-boot-onregulator-min-microvoltregulator-max-microvoltregulator-name#pwm-cells#mbox-cells#power-domain-cellspm_qosoffsetmode-normalmode-recoverymode-bootloadermode-loader#reset-cellsdmasdma-namespower-domains#iommu-cellsrockchip,disable-mmu-resetinterrupt-controller#interrupt-cellsrockchip,pmurangesgpio-controller#gpio-cellsbias-pull-upbias-pull-downbias-disabledrive-strengthrockchip,pinsstdout-pathlabellinux,codewakeup-source