؅8θ( ΀%pine64,pinephone-prorockchip,rk3399 +7Pine64 PinePhonePro=handsetaliasesJ/ethernet@fe300000T/i2c@ff3c0000Y/i2c@ff110000^/i2c@ff120000c/i2c@ff130000h/i2c@ff3d0000m/i2c@ff140000r/i2c@ff150000w/i2c@ff160000|/i2c@ff3e0000/serial@ff180000/serial@ff190000/serial@ff1a0000/serial@ff1b0000/serial@ff370000/mmc@fe310000/mmc@fe320000/mmc@fe330000cpus+cpu-mapcluster0core0core1core2core3cluster1core0core1cpu@0cpuarm,cortex-a53pscid - A Lcpu@1cpuarm,cortex-a53pscid - A Lcpu@2cpuarm,cortex-a53pscid - A Lcpu@3cpuarm,cortex-a53pscid - A Lcpu@100cpuarm,cortex-a72psci  - ALthermal-idleT'`cpu@101cpuarm,cortex-a72psci  - ALthermal-idleT'`idle-statesppscicpu-sleeparm,idle-state}x`L cluster-sleeparm,idle-state}`L display-subsystemrockchip,display-subsystemmemory-controllerrockchip,rk3399-dmcdmc_clk disabledpmu_a53arm,cortex-a53-pmupmu_a72arm,cortex-a72-pmupsci arm,psci-1.0smctimerarm,armv8-timer@   xin24m fixed-clockn6.xin24mALpcie@f8000000rockchip,rk3399-pcie Naxi-baseapb-basepci+Xiu Gaclkaclk-perfhclkpm0123syslegacyclient` ,pcie-phy-0pcie-phy-1pcie-phy-2pcie-phy-38ւ8(coremgmtmgmt-stickypipepmpclkaclk disabledinterrupt-controllerXLethernet@fe300000rockchip,rk3399-gmac0 macirq8ighfjfMstmmacethmac_clk_rxmac_clk_txclk_mac_refclk_mac_refoutaclk_macpclk_mac stmmaceth  disabledmmc@fe3100000rockchip,rk3399-dw-mshcrockchip,rk3288-dw-mshc1@@+р Mbiuciuciu-driveciu-sample9yreset disabledmmc@fe3200000rockchip,rk3399-dw-mshcrockchip,rk3288-dw-mshc2@A+рDT  Lbiuciuciu-driveciu-sample9zresetokayis default mmc@fe330000+rockchip,rk3399-sdhci-5.1arasan,sdhci-5.13 DNT Nclk_xinclk_ahb.emmc_cardclockA! phy_arasanokayiLusb@fe380000 generic-ehci8"#usb disabledusb@fe3a0000 generic-ohci:"#usb disabledusb@fe3c0000 generic-ehci<$%usb disabledusb@fe3e0000 generic-ohci> $%usb disableddebug@fe430000&arm,coresight-cpu-debugarm,primecellCM apb_pclkdebug@fe432000&arm,coresight-cpu-debugarm,primecellC M apb_pclkdebug@fe434000&arm,coresight-cpu-debugarm,primecellC@M apb_pclkdebug@fe436000&arm,coresight-cpu-debugarm,primecellC`M apb_pclkdebug@fe610000&arm,coresight-cpu-debugarm,primecellaL apb_pclkdebug@fe710000&arm,coresight-cpu-debugarm,primecellqL apb_pclkusb@fe800000rockchip,rk3399-dwc3+0Gref_clksuspend_clkbus_clkaclk_usb3_rksoc_axi_perfaclk_usb3grf_clk% usb3-otg disabledusb@fe800000 snps,dwc3irefbus_earlysuspend otg&'usb2-phyusb3-phy utmi_wide6Wp disabledusb@fe900000rockchip,rk3399-dwc3+0Gref_clksuspend_clkbus_clkaclk_usb3_rksoc_axi_perfaclk_usb3grf_clk& usb3-otg disabledusb@fe900000 snps,dwc3nrefbus_earlysuspend otg()usb2-phyusb3-phy utmi_wide6Wp disableddp@fec00000rockchip,rk3399-cdn-dp DrT  ruocore-clkpclkspdifgrf*+ HJspdifdptxapbcore disabledportsport+endpoint@0,Lendpoint@1-Linterrupt-controller@fee00000 arm,gic-v3X+P  Linterrupt-controller@fee20000arm,gic-v3-itsLppi-partitionsinterrupt-partition-0Linterrupt-partition-1Lsaradc@ff100000rockchip,rk3399-saradc>Pesaradcapb_pclk saradc-apb disabledi2c@ff110000rockchip,rk3399-i2cDAT AU i2cpclk;default.+ disabledi2c@ff120000rockchip,rk3399-i2cDBT BV i2cpclk#default/+ disabledi2c@ff130000rockchip,rk3399-i2cDCT CW i2cpclk"default0+ disabledi2c@ff140000rockchip,rk3399-i2cDDT DX i2cpclk&default1+ disabledi2c@ff150000rockchip,rk3399-i2cDET EY i2cpclk%default2+ disabledi2c@ff160000rockchip,rk3399-i2cDFT FZ i2cpclk$default3+ disabledserial@ff180000&rockchip,rk3399-uartsnps,dw-apb-uartQ`baudclkapb_pclkc default4 disabledserial@ff190000&rockchip,rk3399-uartsnps,dw-apb-uartRabaudclkapb_pclkb default5 disabledserial@ff1a0000&rockchip,rk3399-uartsnps,dw-apb-uartSbbaudclkapb_pclkd default6okayserial@ff1b0000&rockchip,rk3399-uartsnps,dw-apb-uartTcbaudclkapb_pclke default7 disabledspi@ff1c0000(rockchip,rk3399-spirockchip,rk3066-spiG[spiclkapb_pclkD 8 8 %txrxdefault9:;<+ disabledspi@ff1d0000(rockchip,rk3399-spirockchip,rk3066-spiH\spiclkapb_pclk5 8 8 %txrxdefault=>?@+ disabledspi@ff1e0000(rockchip,rk3399-spirockchip,rk3066-spiI]spiclkapb_pclk4 88%txrxdefaultABCD+ disabledspi@ff1f0000(rockchip,rk3399-spirockchip,rk3066-spiJ^spiclkapb_pclkC 88%txrxdefaultEFGH+ disabledspi@ff200000(rockchip,rk3399-spirockchip,rk3066-spi K_spiclkapb_pclk II %txrxdefaultJKLM+ disabledthermal-zonescpu-thermal/dESNtripscpu_alert0coEpassiveLOcpu_alert1c oEpassiveLPcpu_critcso Ecriticalcooling-mapsmap0zOmap1zPHgpu-thermal/dESNtripsgpu_alert0c$oEpassiveLQgpu_critcso Ecriticalcooling-mapsmap0zQ Rtsadc@ff260000rockchip,rk3399-tsadc&aDOT qOdtsadcapb_pclk tsadc-apbsinitdefaultsleepSTSokayLNqos@ffa58000rockchip,rk3399-qossyscon L\qos@ffa5c000rockchip,rk3399-qossyscon L]qos@ffa60080rockchip,rk3399-qossyscon qos@ffa60100rockchip,rk3399-qossyscon qos@ffa60180rockchip,rk3399-qossyscon qos@ffa70000rockchip,rk3399-qossyscon L`qos@ffa70080rockchip,rk3399-qossyscon Laqos@ffa74000rockchip,rk3399-qossyscon@ L^qos@ffa76000rockchip,rk3399-qossyscon` L_qos@ffa90000rockchip,rk3399-qossyscon Lbqos@ffa98000rockchip,rk3399-qossyscon LUqos@ffaa0000rockchip,rk3399-qossyscon Lcqos@ffaa0080rockchip,rk3399-qossyscon Ldqos@ffaa8000rockchip,rk3399-qossyscon Leqos@ffaa8080rockchip,rk3399-qossyscon Lfqos@ffab0000rockchip,rk3399-qossyscon LVqos@ffab0080rockchip,rk3399-qossyscon LWqos@ffab8000rockchip,rk3399-qossyscon LXqos@ffac0000rockchip,rk3399-qossyscon LYqos@ffac0080rockchip,rk3399-qossyscon LZqos@ffac8000rockchip,rk3399-qossyscon Lgqos@ffac8080rockchip,rk3399-qossyscon Lhqos@ffad0000rockchip,rk3399-qossyscon Liqos@ffad8080rockchip,rk3399-qossyscon qos@ffae0000rockchip,rk3399-qossyscon L[power-management@ff310000&rockchip,rk3399-pmusysconsimple-mfd1power-controller!rockchip,rk3399-power-controller+Lpower-domain@34"Upower-domain@33!VWpower-domain@31Xpower-domain@32 YZpower-domain@35#[power-domain@25lpower-domain@23\power-domain@22f]power-domain@27L^power-domain@28_power-domain@8~}power-domain@9 power-domain@24`apower-domain@15+power-domain@21rbpower-domain@19cdpower-domain@20efpower-domain@16+power-domain@17ghpower-domain@18isyscon@ff320000)rockchip,rk3399-pmugrfsysconsimple-mfd2Lio-domains&rockchip,rk3399-pmu-io-voltage-domainokayjspi@ff350000(rockchip,rk3399-spirockchip,rk3066-spi5kkspiclkapb_pclk<defaultlmno+ disabledserial@ff370000&rockchip,rk3399-uartsnps,dw-apb-uart7kk"baudclkapb_pclkf defaultp disabledi2c@ff3c0000rockchip,rk3399-i2c<Dk T k k i2cpclk9defaultq+okay+Bpmic@1crockchip,rk818 rA.xin32krk808-clkout2defaultsZ{ttttttregulatorsDCDC_REG1 vdd_cpu_l  Y6NqL regulator-state-memcDCDC_REG2 vdd_center  56B@Nqregulator-state-memcDCDC_REG3vcc_ddr regulator-state-mem|DCDC_REG4vcc_1v8 w@6w@Ljregulator-state-mem|LDO_REG1vcca3v0_codec-6-LDO_REG2 vcc3v0_touch-6-LDO_REG3vcca1v8_codecw@6w@LLDO_REG4 rk818_pwr_on 2Z62Zregulator-state-mem|LDO_REG5vcc_3v0 -6-Lregulator-state-mem|LDO_REG6vcc_1v5 `6`regulator-state-mem|LDO_REG7 vcc1v8_dvpw@6w@LLDO_REG8 vcc3v3_s3 2Z62Zregulator-state-memcLDO_REG9 vccio_sdw@62ZL SWITCH_REG vcc3v3_s0 regulator-state-mem|regulator@40silergy,syr827@defaultu vdd_cpu_b Y60N Lregulator-state-memcregulator@41silergy,syr828Adefaultvvdd_gpu Y6N regulator-state-memci2c@ff3d0000rockchip,rk3399-i2c=Dk T k k i2cpclk8defaultw+ disabledi2c@ff3e0000rockchip,rk3399-i2c>Dk T k k i2cpclk:defaultx+ disabledpwm@ff420000(rockchip,rk3399-pwmrockchip,rk3288-pwmBdefaultyk disabledpwm@ff420010(rockchip,rk3399-pwmrockchip,rk3288-pwmBdefaultzk disabledpwm@ff420020(rockchip,rk3399-pwmrockchip,rk3288-pwmB default{k disabledpwm@ff420030(rockchip,rk3399-pwmrockchip,rk3288-pwmB0default|k disableddfi@ff630000c@rockchip,rk3399-dfiy pclk_ddr_mon disabledLvideo-codec@ff650000rockchip,rk3399-vpue rq vepuvdpu aclkhclk}iommu@ff650800rockchip,iommue@s aclkifaceL}video-codec@ff660000rockchip,rk3399-vdecft axiahbcabaccore~ iommu@ff660480rockchip,iommu f@f@u aclkiface L~iommu@ff670800rockchip,iommug@* aclkiface disabledrga@ff680000rockchip,rk3399-rgah7maclkhclksclkjgi coreaxiahb!efuse@ff690000rockchip,rk3399-efusei+} pclk_efusecpu-id@7cpu-leakage@17gpu-leakage@18center-leakage@19cpu-leakage@1alogic-leakage@1bwafer-info@1cdma-controller@ff6d0000arm,pl330arm,primecellm@  apb_pclkLIdma-controller@ff6e0000arm,pl330arm,primecelln@  apb_pclkL8clock-controller@ff750000rockchip,rk3399-pmucruuxin24mADkT(JLkclock-controller@ff760000rockchip,rk3399-cruvxin24mAD@BCxDT#g/;рxh<4`#Fׄׄ ׄLsyscon@ff770000&rockchip,rk3399-grfsysconsimple-mfdw+Lio-domains"rockchip,rk3399-io-voltage-domainokay  &mipi-dphy-rx0rockchip,rk3399-mipi-dphy-rx0wodphy-refdphy-cfggrf6 disabledLusb2phy@e450rockchip,rk3399-usb2phyP{phyclkA.clk_usbphy0_480m disabledL"host-port6 linestate disabledL#otg-port60ghjotg-bvalidotg-idlinestate disabledL&usb2phy@e460rockchip,rk3399-usb2phy`|phyclkA.clk_usbphy1_480m disabledL$host-port6 linestate disabledL%otg-port60lmootg-bvalidotg-idlinestate disabledL(phy@f780rockchip,rk3399-emmc-phy$emmcclkA26okayL!pcie-phyrockchip,rk3399-pcie-phyrefclk6phy disabledLphy@ff7c0000rockchip,rk3399-typec-phy|~}tcpdcoretcpdphy-refD~TLuphyuphy-pipeuphy-tcphy disableddp-port6L*usb3-port6L'phy@ff800000rockchip,rk3399-typec-phytcpdcoretcpdphy-refDT Muphyuphy-pipeuphy-tcphy disableddp-port6L+usb3-port6L)watchdog@ff848000 rockchip,rk3399-wdtsnps,dw-wdt|xrktimer@ff850000rockchip,rk3399-timerQhZ pclktimerspdif@ff870000rockchip,rk3399-spdifB I%tx mclkhclkUdefault disabledi2s@ff880000(rockchip,rk3399-i2srockchip,rk3066-i2s' II%txrxi2s_clki2s_hclkVbclk_onbclk_off disabledi2s@ff890000(rockchip,rk3399-i2srockchip,rk3066-i2s( II%txrxi2s_clki2s_hclkWdefault disabledi2s@ff8a0000(rockchip,rk3399-i2srockchip,rk3066-i2s) II%txrxi2s_clki2s_hclkX disabledLvop@ff8f0000rockchip,rk3399-vop-lit wDTׄaclk_vopdclk_vophclk_vop axiahbdclk disabledport+Lendpoint@0Lendpoint@1Lendpoint@2Lendpoint@3Lendpoint@4L-iommu@ff8f3f00rockchip,iommu?w aclkiface disabledLvop@ff900000rockchip,rk3399-vop-big vDTׄaclk_vopdclk_vophclk_vop axiahbdclk disabledport+Lendpoint@0Lendpoint@1Lendpoint@2Lendpoint@3Lendpoint@4L,iommu@ff903f00rockchip,iommu?v aclkiface disabledLisp0@ff910000rockchip,rk3399-cif-isp@+nispaclkhclkdphy disabledports+port@0+iommu@ff914000rockchip,iommu @P+ aclkifaceULisp1@ff920000rockchip,rk3399-cif-isp@,oispaclkhclkdphy disabledports+port@0+iommu@ff924000rockchip,iommu @P, aclkifaceULhdmi-soundsimple-audio-cardpi2s hdmi-sound disabledsimple-audio-card,cpusimple-audio-card,codechdmi@ff940000rockchip,rk3399-dw-hdmi(tqpoiahbisfrcecgrfref disabledLportsport+endpoint@0Lendpoint@1Lmipi@ff960000*rockchip,rk3399-mipi-dsisnps,dw-mipi-dsi- porefpclkphy_cfggrfapb+ disabledports+port@0+endpoint@0Lendpoint@1Lmipi@ff968000*rockchip,rk3399-mipi-dsisnps,dw-mipi-dsi. qorefpclkphy_cfggrfapb+6 disabledLports+port@0+endpoint@0Lendpoint@1Ledp@ff970000rockchip,rk3399-edp jlo dppclkgrfdefaultdp disabledports+port@0+endpoint@0Lendpoint@1Lgpu@ff9a0000#rockchip,rk3399-maliarm,mali-t8600 jobmmugpu# disabled-LRpinctrlrockchip,rk3399-pinctrl+gpio@ff720000rockchip,gpio-bankrkXLgpio@ff730000rockchip,gpio-bankskXLrgpio@ff780000rockchip,gpio-bankxPXgpio@ff788000rockchip,gpio-bankxQXLgpio@ff790000rockchip,gpio-bankyRXpcfg-pull-upLpcfg-pull-downLpcfg-pull-noneLpcfg-pull-none-12ma Lpcfg-pull-none-13ma Lpcfg-pull-none-18ma pcfg-pull-none-20ma pcfg-pull-up-2ma pcfg-pull-up-8ma pcfg-pull-up-18ma pcfg-pull-up-20ma pcfg-pull-down-4ma pcfg-pull-down-8ma pcfg-pull-down-12ma pcfg-pull-down-18ma pcfg-pull-down-20ma pcfg-output-high pcfg-output-low $pcfg-input-enable /pcfg-input-pull-up /pcfg-input-pull-down /clockclk-32k <cifcif-clkin < cif-clkouta < edpedp-hpd <Lgmacrgmii-pins <    rmii-pins <     i2c0i2c0-xfer <Lqi2c1i2c1-xfer <L.i2c2i2c2-xfer <L/i2c3i2c3-xfer <L0i2c4i2c4-xfer <  Lwi2c5i2c5-xfer <  L1i2c6i2c6-xfer <  L2i2c7i2c7-xfer <L3i2c8i2c8-xfer <Lxi2s0i2s0-2ch-bus` <i2s0-8ch-bus <Li2s0-8ch-bus-bclk-off <Li2s1i2s1-2ch-busP <Li2s1-2ch-bus-bclk-offP <sdio0sdio0-bus1 <sdio0-bus4@ <sdio0-cmd <sdio0-clk <sdio0-cd <sdio0-pwr <sdio0-bkpwr <sdio0-wp <sdio0-int <sdmmcsdmmc-bus1 <sdmmc-bus4@ <   Lsdmmc-clk < Lsdmmc-cmd < Lsdmmc-cd <Lsdmmc-wp <suspendap-pwroff <ddrio-pwroff <spdifspdif-bus <Lspdif-bus-1 <spi0spi0-clk <L9spi0-cs0 <L<spi0-cs1 <spi0-tx <L:spi0-rx <L;spi1spi1-clk < L=spi1-cs0 < L@spi1-rx <L?spi1-tx <L>spi2spi2-clk < LAspi2-cs0 < LDspi2-rx < LCspi2-tx < LBspi3spi3-clk <Llspi3-cs0 <Lospi3-rx <Lnspi3-tx <Lmspi4spi4-clk <LEspi4-cs0 <LHspi4-rx <LGspi4-tx <LFspi5spi5-clk <LJspi5-cs0 <LMspi5-rx <LLspi5-tx <LKtestclktest-clkout0 <test-clkout1 <test-clkout2 <tsadcotp-pin <LSotp-out <LTuart0uart0-xfer <L4uart0-cts <uart0-rts <uart1uart1-xfer <  L5uart2auart2a-xfer < uart2buart2b-xfer <uart2cuart2c-xfer <L6uart3uart3-xfer <L7uart3-cts <uart3-rts <uart4uart4-xfer <Lpuarthdcpuarthdcp-xfer <pwm0pwm0-pin <Lypwm0-pin-pull-down <vop0-pwm-pin <vop1-pwm-pin <pwm1pwm1-pin <Lzpwm1-pin-pull-down <pwm2pwm2-pin <L{pwm2-pin-pull-down <pwm3apwm3a-pin <L|pwm3bpwm3b-pin <hdmihdmi-i2c-xfer <hdmi-cec <pciepci-clkreqn-cpm <pci-clkreqnb-cpm <buttonspwrbtn-pin <Lpmicpmic-int-l <Lsvsel1-pin <Luvsel2-pin <Lvsoundvcc1v8-codec-en <Lopp-table-0operating-points-v2 JL opp00 UQ \  j@opp01 U#F \ opp02 U0, \ P Popp03 U< \HHopp04 UG \B@B@ disabledopp05 UTfr \** disabledopp-table-1operating-points-v2 JL opp00 UQ \  j@opp01 U#F \ opp02 U0, \ opp03 U< \ Y Yopp04 UG \~~opp05 UTfr \opp06 UYh/ \0opp07 UkI \OO disabledopp-table-2operating-points-v2Lopp00 U  \ 0opp01 U@ \ 0opp02 Uׄ \ 0opp03 Ue \ Y Y0opp04 U#F \HH0opp05 U/ \0chosen {serial2:115200n8gpio-keys gpio-keysdefaultkey-power   Power t{vcc-sys-regulatorregulator-fixedvcc_sys Ltvcc3v3-sys-regulatorregulator-fixed vcc3v3_sys 2Z62Z tLvcc1v8-s3-regulatorregulator-fixed vcca1v8_s3w@6w@  vcc1v8-codec-regulatorregulator-fixed  default vcc1v8_codecw@6w@  compatibleinterrupt-parent#address-cells#size-cellsmodelchassis-typeethernet0i2c0i2c1i2c2i2c3i2c4i2c5i2c6i2c7i2c8serial0serial1serial2serial3serial4mmc0mmc1mmc2cpudevice_typeregenable-methodcapacity-dmips-mhzclocks#cooling-cellsdynamic-power-coefficientcpu-idle-statesoperating-points-v2cpu-supplyphandleduration-usexit-latency-usentry-methodlocal-timer-stoparm,psci-suspend-paramentry-latency-usmin-residency-usportsrockchip,pmudevfreq-eventsclock-namesstatusinterruptsarm,no-tick-in-suspendclock-frequencyclock-output-names#clock-cellsreg-names#interrupt-cellsaspm-no-l0sbus-rangeinterrupt-namesinterrupt-map-maskinterrupt-mapmax-link-speedmsi-mapphysphy-namesrangesresetsreset-namesinterrupt-controllerpower-domainsrockchip,grfsnps,txpblmax-frequencyfifo-depthassigned-clocksassigned-clock-ratesbus-widthcap-sd-highspeedcd-gpiosdisable-wppinctrl-namespinctrl-0vmmc-supplyvqmmc-supplyarasan,soc-ctl-syscondisable-cqe-dcmdmmc-hs200-1_8vnon-removabledr_modephy_typesnps,dis_enblslpm_quirksnps,dis-u2-freeclk-exists-quirksnps,dis_u2_susphy_quirksnps,dis-del-phy-power-chg-quirksnps,dis-tx-ipgap-linecheck-quirk#sound-dai-cellsremote-endpointmsi-controller#msi-cellsaffinity#io-channel-cellsreg-shiftreg-io-widthdmasdma-namespolling-delay-passivepolling-delaythermal-sensorstemperaturehysteresistripcooling-devicerockchip,hw-tshut-temppinctrl-1pinctrl-2#thermal-sensor-cellsrockchip,hw-tshut-moderockchip,hw-tshut-polarity#power-domain-cellspm_qospmu1830-supplyi2c-scl-rising-time-nsi2c-scl-falling-time-nsrockchip,system-power-controllerwakeup-sourcevcc1-supplyvcc2-supplyvcc3-supplyvcc4-supplyvcc6-supplyvcc7-supplyvcc8-supplyvcc9-supplyregulator-nameregulator-always-onregulator-boot-onregulator-min-microvoltregulator-max-microvoltregulator-ramp-delayregulator-off-in-suspendregulator-on-in-suspendfcs,suspend-voltage-selector#pwm-cellsiommus#iommu-cells#dma-cellsarm,pl330-periph-burst#reset-cellsbt656-supplyaudio-supplysdmmc-supplygpio1830-supply#phy-cellsdrive-impedance-ohmrockchip,disable-mmu-resetsimple-audio-card,formatsimple-audio-card,mclk-fssimple-audio-card,namesound-daigpio-controller#gpio-cellsbias-pull-upbias-pull-downbias-disabledrive-strengthoutput-highoutput-lowinput-enablerockchip,pinsopp-sharedopp-hzopp-microvoltclock-latency-nsstdout-pathdebounce-intervallabellinux,codevin-supplyenable-active-highgpio