X8x(hx$mediatek,mt8173-evbmediatek,mt8173 +!7MediaTek MT8173 evaluation boardaliases=/soc/ovl@1400c000B/soc/ovl@1400d000G/soc/rdma@1400e000M/soc/rdma@1400f000S/soc/rdma@14010000Y/soc/wdma@14011000_/soc/wdma@14012000e/soc/color@14013000l/soc/color@14014000s/soc/split@14018000z/soc/split@14019000/soc/dpi@1401d000/soc/dsi@1401b000/soc/dsi@1401c000/soc/rdma@14001000/soc/rdma@14002000/soc/rsz@14003000/soc/rsz@14004000/soc/rsz@14005000/soc/wdma@14006000/soc/wrot@14007000/soc/wrot@14008000/soc/serial@11002000/soc/serial@11003000/soc/serial@11004000/soc/serial@11005000opp_table0operating-points-v2 opp-50700000084 xopp-702000000)׫ opp-1001000000; @opp-1105000000A@ehopp-1209000000H@opp-1300000000M|m opp-1508000000YAopp-1703000000e*opp_table1operating-points-v2 opp-50700000084 `opp-702000000)׫ :opp-1001000000; @%opp-1209000000H@@opp-1404000000SW]opp-1612000000`+opp-1807000000kopp-2106000000}*cpus+cpu-mapcluster0core0%core1%cluster1core0%core1%cpu@0)cpuarm,cortex-a5359psciGWf cpuintermediate  cpu@1)cpuarm,cortex-a5359psciGWf cpuintermediate  cpu@100)cpuarm,cortex-a7259psciGWfcpuintermediate   cpu@101)cpuarm,cortex-a7259psciGWfcpuintermediate   idle-statespscicpu-sleep-0arm,idle-state@"pmu_a53arm,cortex-a53-pmu9 Dpmu_a72arm,cortex-a72-pmu9  Dpsci#arm,psci-1.0arm,psci-0.2arm,psci@smcWckoscillator0 fixed-clockrclk26moscillator1 fixed-clockr}clk32koscillator2 fixed-clockrcpum_ckthermal-zonescpu_thermaltripstrip-point0 0passivetrip-point1L0passivecpu_crit08 0criticalcooling-mapsmap0 map1reserved-memory+ vpu_dma_mem_region@b7000000shared-dma-pool5P'1timerarm,armv8-timer 09   8soc+ simple-bus clock-controller@10000000mediatek,mt8173-topckgen5rpower-controller@10001000 mediatek,mt8173-infracfgsyscon5rOpower-controller@10003000mediatek,mt8173-pericfgsyscon50rOsyscfg_pctl_a@10005000%mediatek,mt8173-pctl-a-syscfgsyscon5Ppinctrl@1000b000mediatek,mt8173-pinctrl5\q$9xxxApins1i2c0pins1-.i2c1pins1}~i2c2 pins1+,i2c3$pins1jki2c4%pins1i2c6&pins1dedisp_pwm0_pins?pins1Wmmc0default'pins_cmd_dat$9:;<=>?@Bpins_clkApins_rstDmmc1default+pins_cmd_datIJKLN fpins_clkM pins_insertmmc0(pins_cmd_dat$9:;<=>?@B epins_clkA epins_rstDmmc1,pins_cmd_datIJKLN fpins_clkM fusb_iddig_pull_up5pins_iddigusb_iddig_pull_down6pins_iddigspi0!pins_spiEFGHpower-controller@10006000mediatek,mt8173-scpsys5`UXimfgmmvencvenc_lt0watchdog@10007000(mediatek,mt8173-wdtmediatek,mt6589-wdt5ptimer@10008000,mediatek,mt8173-timermediatek,mt6577-timer5 9 xpwrap@1000d000mediatek,mt8173-pwrap59pwrap 9CJpwrap   spiwrapVmt6397mediatek,mt6397 9 mt6397regulatormediatek,mt6397-regulatorbuck_vpca15 dbuck_vpca15yvpca15 `p0 buck_vpca7 dbuck_vpca7yvpca7 `p0sbuck_vsramca15dbuck_vsramca15 yvsramca15 `p0buck_vsramca7dbuck_vsramca7 yvsramca7 `p0 buck_vcore dbuck_vcoreyvcore `p0buck_vgpu dbuck_vgpuyvgpu `p0sbuck_vdrm dbuck_vdrmyvdrmO\0buck_vio18 dbuck_vio18yvio18 6`0*ldo_vtcxo dldo_vtcxoyvtcxoldo_va28 dldo_va28yva28ldo_vcama dldo_vcamayvcama`*ldo_vio28 dldo_vio28yvio28ldo_vusb dldo_vusbyvusb2ldo_vmcdldo_vmcyvmcw@2Z.ldo_vmch dldo_vmchyvmch-2Z-ldo_vemc3v3 dldo_vemc3v3 yvemc_3v3-2Z)ldo_vgp1 dldo_vgp1yvcamd2Zldo_vgp2 dldo_vgp2yvcamioB@2Zldo_vgp3 dldo_vgp3yvcamafO2Zldo_vgp4 dldo_vgp4yvgp4O2Zldo_vgp5 dldo_vgp5yvgp5O-ldo_vgp6 dldo_vgp6yvgp6O2Zldo_vibr dldo_vibryvibr 2Zcec@10013000mediatek,mt8173-cec50 9 okayvpu@10020000mediatek,mt8173-vpu 5 9tcmcfg_reg 9gmain;intpol-controller@10200620.mediatek,mt8173-sysirqmediatek,mt6577-sysirq 5  iommu@10205000mediatek,mt8173-m4u5 P 9bclk!:efuse@10206000mediatek,mt8173-efuse5 `+calib@5285( #clock-controller@10209000mediatek,mt8173-apmixedsys5 rhdmi-phy@10209100mediatek,mt8173-hdmi-phy5 $pll_refhdmitx_dig_cts. =rOokayBmailbox@10212000mediatek,mt8173-gce5!  9gceZ8mipi-dphy@10215000mediatek,mt8173-mipi-tx5!P mipi_tx0_pllrO disabled<mipi-dphy@10216000mediatek,mt8173-mipi-tx5!` mipi_tx1_pllrO disabled=interrupt-controller@10221000 arm,gic-400 @5"" "@ "`  9 auxadc@11001000mediatek,mt8173-auxadc5mainf"serial@11002000*mediatek,mt8173-uartmediatek,mt6577-uart5  9S$ baudbusokayserial@11003000*mediatek,mt8173-uartmediatek,mt6577-uart50 9T% baudbus disabledserial@11004000*mediatek,mt8173-uartmediatek,mt6577-uart5@ 9U& baudbus disabledserial@11005000*mediatek,mt8173-uartmediatek,mt6577-uart5P 9V' baudbus disabledi2c@11007000mediatek,mt8173-i2c 5pp 9Lx  maindmadefault+ disabledi2c@11008000mediatek,mt8173-i2c 5p 9Mx  maindmadefault+okayda9211@68 dlg,da92115hregulatorsBUCKAyVBUCKA `0C#' BUCKByVBUCKB `0-'i2c@11009000mediatek,mt8173-i2c 5p 9Nx  maindmadefault + disabledspi@1100a000mediatek,mt8173-spi+5 9n4\parent-clksel-clkspi-clkokaydefault!thermal@1100b000mediatek,mt8173-thermal5 9F thermauxadcC"#"calibration-dataspi@1100d000mediatek,mt8173-nor5!rspisf+ disabledi2c@11010000mediatek,mt8173-i2c 5p 9Ox  maindmadefault$+ disabledi2c@11011000mediatek,mt8173-i2c 5p 9Px  maindmadefault%+ disabledi2c@11012000mediatek,mt8173-hdmi-ddc 9Q5 ddc-i2ci2c@11013000mediatek,mt8173-i2c 50p 9Rx#  maindmadefault&+ disabledaudio-controller@11220000mediatek,mt8173-afe-pcm5" 9VPdeybinfra_sys_audio_clktop_pdn_audiotop_pdn_aud_intbusbck0bck1i2s0_mi2s1_mi2s2_mi2s3_mi2s3_b3mnCmmc@11230000mediatek,mt8173-mmc5# 9G_ sourcehclkokaydefaultstate_uhs'Z(dn|)*mmc@11240000mediatek,mt8173-mmc5$ 9HR sourcehclkokaydefaultstate_uhs+Z,dn# 0-.mmc@11250000mediatek,mt8173-mmc5% 9IR sourcehclk disabledmmc@11260000mediatek,mt8173-mmc5& 9Ju sourcehclk disabledusb@11271000mediatek,mt8173-mtu3 5'0( 9macippc 9@9/01V ^sys_ckref_ck >+ okayU2c3o4votg~defaultid_floatid_ground5Z56xhci@11270000mediatek,mt8173-xhci5'9mac 9sV ^sys_ckref_ckokayU2c7usb-phy@11290000mediatek,mt8173-u3phy5)+ okayusb-phy@112908005)refOokay/usb-phy@112909005) refOokay0usb-phy@112910005)refOokay1syscon@14000000mediatek,mt8173-mmsyssyscon5V3Uׄr8889rdma@14001000-mediatek,mt8173-mdp-rdmamediatek,mt8173-mdp599V:;rdma@14002000mediatek,mt8173-mdp-rdma5 99V:rsz@14003000mediatek,mt8173-mdp-rsz509Vrsz@14004000mediatek,mt8173-mdp-rsz5@9Vrsz@14005000mediatek,mt8173-mdp-rsz5P9Vwdma@14006000mediatek,mt8173-mdp-wdma5`9 V:wrot@14007000mediatek,mt8173-mdp-wrot5p9 V:wrot@14008000mediatek,mt8173-mdp-wrot59 V:ovl@1400c000mediatek,mt8173-disp-ovl5 9V9:8ovl@1400d000mediatek,mt8173-disp-ovl5 9V9:8rdma@1400e000mediatek,mt8173-disp-rdma5 9V9:8rdma@1400f000mediatek,mt8173-disp-rdma5 9V9:8rdma@14010000mediatek,mt8173-disp-rdma5 9V9:8wdma@14011000mediatek,mt8173-disp-wdma5 9V9:8wdma@14012000mediatek,mt8173-disp-wdma5  9V9:8 color@14013000mediatek,mt8173-disp-color50 9V980color@14014000mediatek,mt8173-disp-color5@ 9V98@aal@14015000mediatek,mt8173-disp-aal5P 9V98Pgamma@14016000mediatek,mt8173-disp-gamma5` 9V98`merge@14017000mediatek,mt8173-disp-merge5pV9split@14018000mediatek,mt8173-disp-split5V9split@14019000mediatek,mt8173-disp-split5V9ufoe@1401a000mediatek,mt8173-disp-ufoe5 9V9dsi@1401b000mediatek,mt8173-dsi5 9V9$9%<enginedigitalhs9<dphy disableddsi@1401c000mediatek,mt8173-dsi5 9V9&9'=enginedigitalhs9=dphy disableddpi@1401d000mediatek,mt8173-dpi5 9V9(9)pixelenginepllokayportendpoint>Cpwm@1401e0002mediatek,mt8173-disp-pwmmediatek,mt6595-disp-pwm59!9 mainmmokaydefault?pwm@1401f0002mediatek,mt8173-disp-pwmmediatek,mt6595-disp-pwm59#9"mainmm disabledmutex@14020000mediatek,mt8173-disp-mutex5 9V956larb@14021000mediatek,mt8173-smi-larb5%@V99apbsmismi@14022000mediatek,mt8173-smi-common5 V99apbsmi@od@14023000mediatek,mt8173-disp-od509hdmi@14025000mediatek,mt8173-hdmi5P 9 9,9-9.9/pixelpllbclkspdifdefaultA9Bhdmi29 3sCBokayports+port@05endpointC>port@15endpointDIlarb@14027000mediatek,mt8173-smi-larb5p%@V9292apbsmiclock-controller@15000000mediatek,mt8173-imgsyssyscon5rElarb@15001000mediatek,mt8173-smi-larb5%@VEEapbsmiclock-controller@16000000mediatek,mt8173-vdecsyssyscon5rFvcodec@16000000mediatek,mt8173-vcodec-dec5 0@Phpx 9@: :!:%:&:':":#:$;V@ >lWMiNZvcodecpllunivpll_d2clk_cci400_selvdec_selvdecpllvencpllvenc_lt_selvdec_bus_clk_src(3ilW CN>MXU/larb@16010000mediatek,mt8173-smi-larb5%@VFFapbsmiclock-controller@18000000mediatek,mt8173-vencsyssyscon5rGlarb@18001000mediatek,mt8173-smi-larb5%@VGGapbsmivcodec@18002000mediatek,mt8173-vcodec-enc 5  9:`:a:b:c:d:i:j:k:l:m:n:::::::::; PX?i2venc_sel_srcvenc_selvenc_lt_sel_srcvenc_lt_sel3XiCMNjpegdec@18004000mediatek,mt8173-jpgdec5@ 9GGjpgdec-smijpgdecV:g:hclock-controller@19000000!mediatek,mt8173-vencltsyssyscon5rHlarb@19001000mediatek,mt8173-smi-larb5%@VHHapbsmimemory@40000000)memory5@chosenconnectorhdmi-connectorGhdmi0dportendpointIDextcon_iddiglinux,extcon-usb-gpio M4regulator@0regulator-fixed yusb_vbusLK@LK@ PU7regulator@1regulator-fixedyvbusLK@LK@ P U3 compatibleinterrupt-parent#address-cells#size-cellsmodelovl0ovl1rdma0rdma1rdma2wdma0wdma1color0color1split0split1dpi0dsi0dsi1mdp-rdma0mdp-rdma1mdp-rsz0mdp-rsz1mdp-rsz2mdp-wdma0mdp-wrot0mdp-wrot1serial0serial1serial2serial3opp-sharedphandleopp-hzopp-microvoltcpudevice_typeregenable-methodcpu-idle-states#cooling-cellsdynamic-power-coefficientclocksclock-namesoperating-points-v2capacity-dmips-mhzproc-supplysram-supplyentry-methodlocal-timer-stopentry-latency-usexit-latency-usmin-residency-usarm,psci-suspend-paraminterruptsinterrupt-affinitycpu_suspendcpu_offcpu_on#clock-cellsclock-frequencyclock-output-namespolling-delay-passivepolling-delaythermal-sensorssustainable-powertemperaturehysteresistripcooling-devicecontributionrangesalignmentno-maparm,no-tick-in-suspend#reset-cellsmediatek,pctl-regmappins-are-numberedgpio-controller#gpio-cellsinterrupt-controller#interrupt-cellspinmuxinput-enablebias-pull-downbias-disableoutput-lowbias-pull-updrive-strength#power-domain-cellsinfracfgreg-namesresetsreset-namespower-domainsregulator-compatibleregulator-nameregulator-min-microvoltregulator-max-microvoltregulator-ramp-delayregulator-always-onregulator-enable-ramp-delaystatusmemory-regionmediatek,larbs#iommu-cellsmediatek,ibiasmediatek,ibias_up#phy-cells#mbox-cells#io-channel-cellsclock-divpinctrl-namespinctrl-0regulator-min-microampregulator-max-microampmediatek,pad-select#thermal-sensor-cellsmediatek,auxadcmediatek,apmixedsysnvmem-cellsnvmem-cell-namesassigned-clocksassigned-clock-parentspinctrl-1bus-widthmax-frequencycap-mmc-highspeedmediatek,hs200-cmd-int-delaymediatek,hs400-cmd-int-delaymediatek,hs400-cmd-resp-sel-risingvmmc-supplyvqmmc-supplynon-removablecap-sd-highspeedsd-uhs-sdr25cd-gpiosphysmediatek,syscon-wakeupvusb33-supplyvbus-supplyextcondr_modewakeup-sourcepinctrl-2assigned-clock-ratesmboxesmediatek,gce-client-regiommusmediatek,larbmediatek,vpuphy-namesremote-endpoint#pwm-cellsmediatek,gce-eventsmediatek,smimediatek,syscon-hdmilabelid-gpioenable-active-high