*\8'('#adapteva,parallellaxlnx,zynq-7000&Adapteva Parallella boardcpuscpu@0arm,cortex-a9,cpu8<CQ] ,+B@B@ncpu@1arm,cortex-a9,cpu8<nfpga-full fpga-regionvpmu@f8891000arm,cortex-a9-pmu80fixedregulatorregulator-fixedVCCPINTB@B@nreplicator arm,coresight-static-replicator<./apb_pclkdbg_trcdbg_apbout-portsport@08endpointn port@18endpointn in-portsportendpointn axi simple-busadc@f8007100xlnx,zynq-xadc-1.00.a8q  < can@e0008000xlnx,zynq-can-1.0 #disabled<$ can_clkpclk8 *@8@can@e0009000xlnx,zynq-can-1.0 #disabled<% can_clkpclk8 3*@8@gpio@e000a000xlnx,zynq-gpio-1.0F<*Rbw 8i2c@e0004000cdns,i2c-r1p10#okay<& 8@isl9305@68 isil,isl93058hregulatorsdcd1VDD_DSPdcd21P35Vldo1VDD_ADJldo2 VDD_GPIOi2c@e0005000cdns,i2c-r1p10 #disabled<' 08Pinterrupt-controller@f8f01000arm,cortex-a9-gicwb8ncache-controller@f8f02000arm,pl310-cache8    memory-controller@f8006000xlnx,zynq-ddrc-a058`serial@e0000000xlnx,xuartpscdns,uart-r1p8 #disabled<(uart_clkpclk8 serial@e0001000xlnx,xuartpscdns,uart-r1p8#okay<)uart_clkpclk8 2spi@e0006000xlnx,zynq-spi-r1p68` #disabled <" ref_clkpclkspi@e0007000xlnx,zynq-spi-r1p68p #disabled 1<# ref_clkpclkspi@e000d000xlnx,zynq-qspi-1.08 < + ref_clkpclk #disabledethernet@e000b000xlnx,zynq-gemcdns,gem8#okay < pclkhclktx_clk rgmii-idethernet-phy@04ethernet-phy-id0141.0e90ethernet-phy-ieee802.3-c228 ,ethernet-phy  nethernet@e000c000xlnx,zynq-gemcdns,gem8 #disabled -<pclkhclktx_clkmemory-controller@e000e000!arm,pl353-smc-r2p1arm,primecell8 #disabledmemclkapb_pclk< ,0nand-controller@0,0arm,pl353-nand-r2p1 8 #disabledmmc@e0100000arasan,sdhci-8.9a #disabledclk_xinclk_ahb<  8mmc@e0101000arasan,sdhci-8.9a#okayclk_xinclk_ahb<! /8slcr@f8000000!xlnx,zynq-slcrsysconsimple-mfd8n clkc@100xlnx,ps7-clkcjarmpllddrplliopllcpu_6or4xcpu_3or2xcpu_2xcpu_1xddr2xddr3xdcilqspismcpcapgem0gem1fclk0fclk1fclk2fclk3can0can1sdio0sdio1uart0uart1spi0spi1dmausb0_aperusb1_apergem0_apergem1_apersdio0_apersdio1_aperspi0_aperspi1_apercan0_apercan1_aperi2c0_aperi2c1_aperuart0_aperuart1_apergpio_aperlqspi_apersmc_aperswdtdbg_trcdbg_apb8$Unrstc@200xlnx,zynq-reset8H5B pinctrl@700xlnx,pinctrl-zynq8B dma-controller@f8003000arm,pl330arm,primecell80l ()*+I< apb_pclkdevcfg@f8007000xlnx,zynq-devcfg-1.08p < ref_clkB ntimer@f8f00200arm,cortex-a9-global-timer8   <timer@f8001000$    cdns,ttc<8timer@f8002000$%&' cdns,ttc<8 timer@f8f00600  arm,cortex-a9-twd-timer8 <usb@e0002000"xlnx,zynq-usb-2.20achipidea,usb2 #disabled< 8 Tulpiusb@e0003000"xlnx,zynq-usb-2.20achipidea,usb2 #disabled< ,80Tulpiwatchdog@f8005000<-cdns,wdt-r1p2 8P] etb@f8801000"arm,coresight-etb10arm,primecell8<./apb_pclkdbg_trcdbg_apbin-portsportendpoint ntpiu@f8803000!arm,coresight-tpiuarm,primecell80<./apb_pclkdbg_trcdbg_apbin-portsportendpoint nfunnel@f8804000*arm,coresight-static-funnelarm,primecell8@<./apb_pclkdbg_trcdbg_apbout-portsportendpoint nin-portsport@08endpoint nport@18endpointnport@28endpointptm@f889c000"arm,coresight-etm3xarm,primecell8<./apb_pclkdbg_trcdbg_apbiout-portsportendpointn ptm@f889d000"arm,coresight-etm3xarm,primecell8<./apb_pclkdbg_trcdbg_apbiout-portsportendpointnaliasesm/axi/ethernet@e000b000w/axi/serial@e0001000memory@0,memory8@chosen0root=/dev/mmcblk0p2 rootfstype=ext4 rw rootwaitserial0:115200n8 #address-cells#size-cellscompatiblemodeldevice_typeregclocksclock-latencycpu0-supplyoperating-pointsphandlefpga-mgrrangesinterruptsinterrupt-parentregulator-nameregulator-min-microvoltregulator-max-microvoltregulator-boot-onregulator-always-onclock-namesremote-endpointstatustx-fifo-depthrx-fifo-depth#gpio-cellsgpio-controllerinterrupt-controller#interrupt-cellsclock-frequencyarm,data-latencyarm,tag-latencycache-unifiedcache-levelphy-modephy-handlemarvell,reg-init#clock-cellsfclk-enableclock-output-namesps-clk-frequency#reset-cellssyscon#dma-cellsphy_typetimeout-seccpuethernet0serial0bootargsstdout-path