.8*(%* MangOH Green with WP8548 Module2!swir,mangoh-green-wp8548swir,wp8548qcom,mdm9615,cpuscpu@0!arm,cortex-a5=AcpuMcpu-pmu!arm,cortex-a5-pmu ^ clockscxo_board !fixed-clockiv$vsdcc-regulator!regulator-fixed SDCC Power)2)2soc !simple-buscache-controller@2040000!arm,pl310-cache= interrupt-controller@2000000!qcom,msm-qgic2(= timer@200a0005!qcom,kpss-wdt-mdm9615qcom,kpss-timerqcom,msm-timer$^=v9pinctrl@800000!qcom,mdm9615-pinctrlDTX` ^(=@lvdefaultgsbi3-stategsbi3-pinsgpio8gpio9gpio10gpio11gsbi3gsbi4-state gsbi4-pinsgpio12gpio13gpio14gpio15gsbi4gsbi5-i2c-state sda-pinsgpio16 gsbi5_i2cscl-pinsgpio17 gsbi5_i2cgsbi5-uart-stategsbi5-uart-pinsgpio18gpio19 gsbi5_uartreset-out-statereset-out-pinsgpio66gpiogpioext1-stategpioext1-pinsgpio2gpiosdc-cd-statesdc-cd-pinsgpio42gpioclock-controller@900000!qcom,gcc-mdm9615i=@ clock-controller@28000000!qcom,lcc-mdm9615=(i$cxopll4_votemi2s_codec_clkcodec_i2s_mic_codec_clkspare_i2s_mic_codec_clkcodec_i2s_spkr_codec_clkspare_i2s_spkr_codec_clkpcm_codec_clkclock-controller@2011000+!qcom,kpss-gcc-mdm9615qcom,kpss-gccsyscon=rng@1a500000 !qcom,prng=Pcore Hgsbi@16100000!qcom,gsbi-v1.0.0 =iface +disabledi2c@16180000!qcom,i2c-qup-v1.1.1= ^ coreiface +disabledgsbi@16200000!qcom,gsbi-v1.0.0 = iface+okay2spi@16280000!qcom,spi-qup-v1.1.1=( ^ coreiface+okaylvdefault n6spi@0!swir,mangoh-iotport-spi<n6=gsbi@16300000!qcom,gsbi-v1.0.0 =0iface+okayN 2serial@16340000%!qcom,msm-uartdm-v1.3qcom,msm-uartdm=40 ^ coreiface+okayl vdefaultgsbi@16400000!qcom,gsbi-v1.0.0 =@iface+okayN 2i2c@16480000!qcom,i2c-qup-v1.1.1=H ^ n6 coreiface+okayv @l vdefaultmux@71 !nxp,pca9548=qi2c@0=i2c@1=i2c@2=i2c@3=hub@8!smsc,usb3503a= Z  h si2c@4=pinctrl@3e`(!semtech,sx1509q=>, ^Di2c@5=pinctrl@3flvdefault`(!semtech,sx1509q=?,^D i2c@6=pinctrl@70`(!semtech,sx1509q=p, ^D i2c@7=serial@16440000%!qcom,msm-uartdm-v1.3qcom,msm-uartdm=D@ ^ coreiface+okaylvdefaultqcom,ssbi@500000 !qcom,ssbi=P pmic-arbiterpmic!qcom,pm8018qcom,pm8921 ^(pwrkey@1c&!qcom,pm8018-pwrkeyqcom,pm8921-pwrkey=,^23= mpps@50!qcom,pm8018-mppqcom,ssbi-mpp(=PD`Trtc@11d !qcom,pm8018-rtcqcom,pm8921-rtc,^'=gpio@150 !qcom,pm8018-gpioqcom,ssbi-gpio=P(DT`usb-vbus-5v-stategpio4normaldma-controller@12182000!qcom,bam-v1.3.0=  ^bnbam_clkdma-controller@12142000!qcom,bam-v1.3.0=  ^aobam_clkmmc@12180000+okay!arm,pl18xarm,primecell=  ^hxnmclkapb_pclk @l'9EJtxrxx lvdefaultT _*mmc@12140000!arm,pl18xarm,primecell +disabled=  ^gyomclkapb_pclk '@lh9EJtxrxy syscon@1a400000!qcom,tcsr-mdm9615syscon=@ rpm@108000!qcom,rpm-mdm9615= q$^zackerrwakeupregulators!qcom,rpm-pm8018-regulatorss1 0js2( js3w@w@js4 !js5ppjl2w@w@l3w@w@l42Z2Zl5+|+|l6w@+|l7:l8OOl9 q0l10l11l12l13:-pl14+|+|lvs1memory@48000000Amemory=Haliases /soc/gsbi@16200000/spi@16280000#/soc/gsbi@16300000/serial@16340000#/soc/gsbi@16400000/serial@16440000 /soc/gsbi@16400000/i2c@16480000/soc/mmc@12180000chosenserial1:115200n8 #address-cells#size-cellsmodelcompatibleinterrupt-parentregdevice_typenext-level-cacheinterrupts#clock-cellsclock-frequencyphandleregulator-nameregulator-min-microvoltregulator-max-microvoltregulator-always-onrangesarm,data-latencycache-unifiedcache-levelinterrupt-controller#interrupt-cellscpu-offsetgpio-controllergpio-ranges#gpio-cellspinctrl-0pinctrl-namespinsfunctiondrive-strengthbias-disablebias-pull-upoutput-high#power-domain-cells#reset-cellsclocksclock-namesassigned-clocksassigned-clock-ratescell-indexstatusqcom,modespi-max-frequencysyscon-tcsrconnect-gpiosintn-gpiosinitial-modesemtech,probe-resetqcom,controller-typedebounceallow-set-timeqcom,drive-strengthpower-source#dma-cellsqcom,eearm,primecell-periphidbus-widthcap-sd-highspeedcap-mmc-highspeedvmmc-supplydmasdma-namesdisable-wpcd-gpiosno-1-8-vqcom,ipcinterrupt-namesvin_lvs1-supplyvdd_l7-supplyvdd_l8-supplyvdd_l9_l10_l11_l12-supplyqcom,switch-mode-frequencybias-pull-downspi0serial0serial1i2c0mmc0stdout-path